Until now every AML package had to be closed using acpigen_pop_len().
This commit introduces set of package closing functions corresponding
with their opening function names. For example acpigen_write_if()
opens if-statement package, acpigen_write_if_end() closes it.
Now acpigen_write_else() closes previously opened acpigen_write_if(),
so acpigen_pop_len() is not required before it.
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Icfdc3804cd93bde049cd11dec98758b3a639eafd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Use the common PCIEXP_HOTPLUG code to generate a dummy device for PCIe
ports supporting hotplug. This allows to have control over how much
resources are allocated to hotplug ports.
Tested on thinkpad X220: now hotplugging a dGPU via the expresscard
slot sometimes works.
Change-Id: I3eec5214c9d200ef97d1ccfdc00e8ea0ee7cfbc6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Rudolph
Based on the detected OS the HPET ACPI device needs to
be hidden sometimes.
Change-Id: I4c6f87f30ea0de5c073b1fcf57794bb9e19d4d91
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49483
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
IASL complains that creation of named objects within a method is highly
inefficient. Avoid this by moving these named objects out of the method.
Change-Id: Iabfb20dcb3f655658844d99ab7a3b479684d9d19
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50475
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Create `FIXED_RCBA_MMIO_BASE` and use it everywhere, except in cases
where a pointer cast would be necessary. Instances in Sandy Bridge MRC
code were left as-is intentionally, so as not to collide with another
cleanup patch train.
Tested with BUILD_TIMELESS=1, these boards remain identical:
- Asus P8Z77-V LX2
- Packard Bell MS2290
Change-Id: I642958fbd6f02dbf54812d6a75d6bc3087acc77a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50036
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The patch defines default value for ME_REGION_ALLOW_CPU_READ_ACCESS config.
It sets value 'y' if CSE Lite SKU is integrated, otherwise value 'n'. The
config ME_REGION_ALLOW_CPU_READ_ACCESS ensures host has read access to ME
region when the LOCK_MANAGEMENT_ENGINE is enabled and CSE Lite SKU is
integrated.
TEST=Verified build for JSL
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I680a23e27ae2bf4d85bf919134c47882f308af56
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49891
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that intermediate coreboot.pre manipulation is serialized within
the build system, remove the flock calls.
Change-Id: I8a767918aec5fcb7127ebb19ac46e58bed7967fb
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
To allow other platforms to reuse this code, extract it into a separate
compilation unit. Since HPET is enabled through the southbridge, place
the code in the southbridge scope. Finally, select the newly-added
Kconfig option from i82801gx and replace lpc.c `enable_hpet` function.
Change-Id: I7a28cc4d12c6d79cd8ec45dfc8100f15e6eac303
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Target added to INTERMEDIATE all operate on coreboot.pre, each modifying
the file in some way. When running them in parallel, coreboot.pre can be
read from and written to in parallel which can corrupt the result.
Add a function to create those rules that also adds existing
INTERMEDIATE targets to enforce an order (as established by evaluation
order of Makefile.inc files).
While at it, also add the addition to the PHONY target so we don't
forget it.
BUG=chromium:1154313, b:174585424
TEST=Built a configuration with SeaBIOS + SeaBIOS config files (ps2
timeout and sercon) and saw that they were executed.
Change-Id: Ia5803806e6c33083dfe5dec8904a65c46436e756
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49358
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Trying to do multiple operations on the same CBFS image at the same time
likely leads to data corruption. For this reason, add BSD advisory file
locking (flock()) to cbfstool (and ifittool which is using the same file
I/O library), so that only one process will operate on the same file at
the same time and the others will wait in line. This should help resolve
parallel build issues with the INTERMEDIATE target on certain platforms.
Unfortunately, some platforms use the INTERMEDIATE target to do a direct
dd into the CBFS image. This should generally be discouraged and future
platforms should aim to clearly deliminate regions that need to be
written directly by platform scripts with custom FMAP sections, so that
they can be written with `cbfstool write`. For the time being, update
the legacy platforms that do this with explicit calls to the `flock`
utility.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I022468f6957415ae68a7a7e70428ae6f82d23b06
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Using `pci_dev_read_resources` works just as well on bd82x6x (the
allocator does the same) and allows dropping the i82801gx check.
Change-Id: I1cb05131a82ebb7c45827eff8e09e445d9c695b3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48538
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since common smbus.c gets built for romstage as well, create a new file
to hold this common code. Account for ICH7 not having a memory BAR, too.
Change-Id: I4ab46750c6fb7f71cbd55848e79ecc3e44cbbd04
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48364
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The patch modifies KConfig behaviour if CSE Lite SKU is integrated into
the coreboot. When the CSE Lite SKU is integrated, the KConfig prevents
writing to ME region but keeps read access enabled. Since CSE Lite driver
checks the signature of RW partition to identify the interrupted CSE
firmware update, so host must have read access to the ME region. Also, the
patch modifies the KConfig's help text to reflect the change.
When CSE Lite SKU is integrated, master access permissions:
FLMSTR1: 0x002007ff (Host CPU/BIOS)
EC Region Write Access: disabled
Platform Data Region Write Access: disabled
GbE Region Write Access: disabled
Intel ME Region Write Access: disabled
Host CPU/BIOS Region Write Access: enabled
Flash Descriptor Write Access: disabled
EC Region Read Access: disabled
Platform Data Region Read Access: disabled
GbE Region Read Access: disabled
Intel ME Region Read Access: enabled
Host CPU/BIOS Region Read Access: enabled
Flash Descriptor Read Access: enabled
BUG=b:174118018
TEST=Built and verified the access permissions.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I2f6677ab7b59ddce827d3fcaae61508a30dc1b28
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
This file is no longer specific to 6 and 7 series PCHs.
Change-Id: Ib89378bd6ba1d80281b92a79d37b9fdeaaed40fb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46762
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The outb() call is replaced with the post_code()
The post_codes.h is replaced with console.h since console.h
includes both the post_code definition and post_codes.h
Change-Id: I21345260e86de30614c416e2f509bd77b9e00cb7
Signed-off-by: Sindhoor Tilak <sindhoor@sin9yt.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
We will update the other platforms to use this common code in
susbsequent commits. While we are at it, reflow a broken line,
define the SMBus PCI device in the header and fix whitespace.
Change-Id: I1fdff2feead4165f02b24cb948d8c03318969014
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41999
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Make it default to 0x400, which is what the touched southbridges use.
Change-Id: I95cb1730d5bf6f596ed1ca8e7dba40b6a9e882fe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
IRQ 10 and IRQ 11 are valid for all southbridges using this code, as per
their respective datasheets. So, add them for the sake of completeness.
Change-Id: Ib4504861ed316a95b9735e0ed79f108f18071b3b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43158
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Files are identical for all southbridges, except bd82x6x. We will take
care of that in subsequent commits.
Change-Id: I38e5d440e188d26f8997bc22a956187b728487ca
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43157
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Files are identical between all three southbridges, and differ for PCH.
Change-Id: Ic6a926af675bda3db3a5795df9e8f490caf3ebf4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43156
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The `ENABLE_SMBUS_METHODS` symbol is not defined anywhere, so this code
isn't even being tested. So, throw it into the bitbucket before it rots
any further. If anyone needs that code ever again, it's in git history.
Change-Id: I22e3f1ad54e81f811c9660d54f3765f3c6b83f01
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
All Intel southbridges with SPI perform this write. Put it inside a
function in common code. Use a different name to avoid a name clash.
As it is only one statement, make it inline so that it can be defined
on the header itself. It is only called once per southbridge anyway.
Change-Id: I3c284d6cffd22949d50b4c4f9846ceaef38d7cda
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Except for whitespace and varying casts the codes were
the same when implemented.
Platforms that did not implement this are tagged with
ACPI_NO_SMI_GNVS.
Change-Id: I31ec85ebce03d0d472403806969f863e4ca03b6b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Kconfig 4.17 started using the $(..) syntax for environment variable
expansion while we want to keep expansion to the build system.
Older Kconfig versions (like ours) simply drop the escapes, not
changing the behavior.
While we could let Kconfig expand some of the variables, that only
splits the handling in two places, making debugging harder and
potentially messing with reproducible builds (e.g. when paths end up
in configs), so escape them all.
Change-Id: Ibc4087fdd76089352bd8dd0edb1351ec79ea4faa
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Add functionality to use process call cycle. It can be used to
write/read data to/from e.g. EEPROM attached to SMBus Controller
via I2C.
Tested on:
* C246
Change-Id: Ifdac6cf70a4ce744601f5d152a83d2125ea88360
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39875
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
