Commit Graph

4820 Commits

Author SHA1 Message Date
Marc Jones 5c3126936d Generate and extract debug sysmbols for coreboot. *.debug files can be
used for source level debug.

Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5827 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-23 15:38:55 +00:00
Uwe Hermann a34a0b1876 Fix a compiler warning in src/lib/usbdebug.c (trivial).
The 'delay' variable shadows the global 'delay()' function, yielding
this compiler warning/error:

src/pc80/../lib/usbdebug.c: In function `ehci_reset_port':
src/pc80/../lib/usbdebug.c:281: error: declaration of `delay' shadows a global declaration
src/lib/delay.c:9: error: shadowed declaration is here

This fixes the issue by renaming the 'delay' variable to 'delay_ms'.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5826 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-22 23:42:32 +00:00
Rudolf Marek 7df50a8b0e Here is a proposed way how to handle the SATA PHY settings on SB700. It
consits of weak function which always exists (with defaults) and a possibility to 
 override this with normal function in main.c. This is the other way of 
 doing that and not using the devictree.cb.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5825 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-22 22:46:47 +00:00
Uwe Hermann 138cdbb17b First round of i82801ax clean-ups (trivial).
After we splitted up the old i82801xx driver which was supposed to support
multiple generations of ICH* chipsets, some of the generified code
is now obsolete in i82801ax which should only cover ICH/ICH0 and none of
the later ICH* generations.

Hence:
 
 - Drop "struct pci_driver" entries for chipsets other than ICH/ICH0.

 - Drop drivers for hardware that is not present on ICH/ICH0: NIC, SATA, EHCI.

 - Drop PIRQE-PIRQH #defines and code, not available on this chipset.

 - Simplify some parts of the code (more will follow).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5824 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-21 23:53:47 +00:00
Uwe Hermann 8fa90ec274 Cut the crap.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5823 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-21 21:16:27 +00:00
Zheng Bao 0c51ddd98b Complete the code which was missing.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5822 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-21 02:51:31 +00:00
Zheng Bao 951a0feb2d Fix the typo. Field DisAutoRefresh is in DramTimngHi.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5821 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-21 01:24:55 +00:00
Keith Hui df35cdc198 A number of cleanups for 440BX raminit code.
Resolves a number of TODOs items within, and clarified a number of other TODOs.

Change register_values[] from long to u8 (byte). For what we are doing
this is sufficient and makes it only 1/4 the size.

Remove a hard-coding of SDRAMC register that is redundant and now
incorrect, now that SDRAMC is conditioned on SDRAMPWR_4DIMM Kconfig
and set through register_values[].
This fixes all boards with 3 DIMM slots (e.g. ASUS P2B, A-Trend ATC-6220).

RPS registers are now set in runtime code; remove it from
register_values[] table.

Bring DUMPNORTH() back. The code it refers to is still there.

Move #define of NB up so the DUMPNORTH() macro can use it.

Signed-off-by: Keith Hui <buurin@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5820 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-20 23:41:37 +00:00
Uwe Hermann 0865b4d9c0 Make ASUS P3B-F RAM init actually work by enabling SPD access.
On this board all reads from SPD return 0xff by default, there's a custom
GPIO fiddling needed to enable access to the SPD SMBus offsets at
0x50-0x53. While coreboot actually sort of booted sometimes before r5193,
that was just sheer luck as the RAM init was hardcoded in certain ways.
Since the proper, more heavily SPD-based RAM init the brokenness of the
ASUS P3B-F RAM init was becoming visible.

This patch uses GPIOs to enable access to the SPD SMBus offsets,
and resets the GPIOs again after RAM init (this is needed to allow for
lm-sensors to work, for example).

Tested successfully on hardware.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Idwer Vollering <vidwer@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5819 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-19 21:12:05 +00:00
Scott Duplichan 78301d02b0 AMD Fam10 code breaks with gcc 4.5.0.
Root cause: After function STOP_CAR_AND_CPU disables cache as
ram, the cache as ram stack can no longer be used. Called
functions must be inlined to avoid stack usage. Also, the
compiler must keep local variables register based and not
allocated them from the stack. With gcc 4.5.0, some functions
declared as inline are not being inlined. This patch forces
these functions to always be inlined by adding the qualifier
__attribute__((always_inline)) to their declaration.


Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5818 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-17 21:38:40 +00:00
Arne Georg Gleditsch 01d56d4276 Clear bit 35 of msr c001_102a in Fam10 rev C cores.
Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numascale.com>
Acked-by: Scott Duplichan <scott@notabs.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5817 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-17 00:13:52 +00:00
Marc Jones 8985ef179b Add default libpayload build, xcompile, and lpgcc setup to tint.
Signed-off-by: Marc Jones <marc.jones@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Myles Watson <mylesgw@gmail.com>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5816 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-16 21:36:44 +00:00
Marc Jones 1c5637d926 Add more Fam10 CPUID strings from the AMD revision guide. Includes
newer Phenom II.

Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Paul Menzel <paulepanter@users.sourceforge.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5815 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-16 21:04:54 +00:00
Scott Duplichan 9b0c690c09 This patch corrects a coding error in the original implementation
of 'Erratum 343 for AMD Fam10h CPUs' (rev 4345). The original code
sets msr c001_102a bit 3 when bit 35 was intended.


Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5814 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-14 17:28:41 +00:00
Marc Jones 3f1d29c408 IEI Kino added to IEI mainboard Kconfig. I missed this in r5812
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Marc Jones <marcj303@gmail.com>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5813 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-13 19:31:21 +00:00
Marc Jones 738347e7c3 IEI Kino mainboard support based on Mahogany Fam10.
svn copy amd/mahogany iei/kino-780am2-fam10; then apply the patch.

Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5812 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-13 19:24:38 +00:00
Myles Watson 2b28614cc5 CONFIG_MMCONF_SUPPORT is always defined. Fix build.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5811 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-13 17:46:13 +00:00
Arne Georg Gleditsch e7a5b76a74 Move initialization of MMCONF BAR to cache_as_ram setup phase, in order
to make sure MMCONF is set up before use.  Otherwise, PCI config
accesses run before init_cpus() will be lost if MMCONF is enabled
(unless explicitly done as port-based accesses).

This obsoletes removal of RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78) in
mcp55_early_setup, so reinsert.

Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numascale.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5810 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-13 15:11:35 +00:00
Juhana Helovuo d09d1f7846 Add support for Asus M4A785-M.
Signed-off-by: Juhana Helovuo <juhe@iki.fi>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5809 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-13 14:51:26 +00:00
Myles Watson 6c029e6963 Add reserved areas for fam10.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5808 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-13 14:50:20 +00:00
Myles Watson 687b3ba327 Port k8 UMA handling to fam10.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5807 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-13 14:49:02 +00:00
Juhana Helovuo 6b56e43b6d Generate multiboot tables from coreboot tables.
Signed-off-by: Juhana Helovuo <juhe@iki.fi>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5806 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-13 14:47:22 +00:00
Juhana Helovuo 50b78b66d3 Print an error and correct pci scan limits. Skip sb700 ISA DMA init if needed.
Signed-off-by: Juhana Helovuo <juhe@iki.fi>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5805 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-13 14:43:02 +00:00
Myles Watson cb817beb67 Fix a typo reported by Sylvain Hitier.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5804 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-13 13:23:20 +00:00
Myles Watson 25d1213e3f Convert i945 boards to use reserved resources instead of directly adding
coreboot table entries in every mainboard.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5803 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-13 13:14:48 +00:00
Marc Jones 43882f1714 Add F71859 SIO.
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5802 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-10 22:13:34 +00:00
Jens Rottmann 36224b479b Add support for LiPPERT Hurricane-LX (EPIC board with AMD Geode-LX,
CS5536, ITE IT8712F).  Board support is based on the SpaceRunner-LX
(with tiny bits from the RoadRunner-LX) even though the hardware really
was the ancestor of our three other -LX boards and in fact among the
earliest Geode-LX boards on the market.  (Might even have been the first
Geode-LX EPIC?)

Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5801 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-10 21:51:34 +00:00
Myles Watson 6ea2115cea Move memory type information out of some AMD sockets.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5800 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-10 18:33:24 +00:00
Patrick Georgi 17daf9a941 Adapt comment, too. (trivial)
Noticed-by: Uwe Hermann
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5799 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-09 22:12:40 +00:00
Scott Duplichan 9c934d1d46 This patch avoids a timeout during PS/2 keyboard
initialization. It can reduce KBC init time by up to 400 ms on
real hardware, and by a minute or so on AMD simnow.


Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5798 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-09 20:37:00 +00:00
Myles Watson 8f8a51cded Make huge macros inline functions for readability. Remove warnings. Trivial.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5797 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-09 16:00:20 +00:00
Arne Georg Gleditsch d6689ed781 Please find appended. This patch gets rid of the %gs magic altogether,
fixes a few alignment wrinkles and sets up and registers the MMCONF area
for AMD Fam10h CPUs (where selected by mainboard configuration).  It
removes a bit of code that proved troublesome in MMCONF setups from
mcp55_early_setup_car.c, as per earlier discussion.

Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numascale.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5796 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-09 14:54:07 +00:00
Myles Watson e0a000cc12 Add support for reserved regions to resources and coreboot tables.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5795 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-09 14:51:17 +00:00
Patrick Georgi 6b247d3ef8 Only try to beep when speaker support is compiled in.
Trivial change.

Reported-by: Aurelien Guillaume <aurelien@iwi.me>
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5794 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-09 14:44:51 +00:00
Myles Watson f53eaa3966 My Jmicron SATA card writes the name of the hard drive to the screen.
This redirects that output to the console and implements a basic
keyboard stub.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5793 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-09 14:42:58 +00:00
Arne Georg Gleditsch e150e9a571 Also improve boot time on AMD for the DDR3 code path.
Fix a typo, too.

Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numscale.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5792 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-09 10:35:52 +00:00
Arne Georg Gleditsch 6556534bab Apparently, it's not crucial to clear this at the exact moment we switch
to using ram, so something like the appended is perhaps more
appropriate.  Confirmed to work on hw.

Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numscale.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5791 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-09 09:56:19 +00:00
Kevin O'Connor 9c35c8409d Add a DRIVERS_PS2_KEYBOARD option which controls the PS2 keyboard
initialization.  Not all payloads require it and some keyboards take a
long time to init.

Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5790 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-09 08:34:02 +00:00
Marc Jones 080ed7c5d5 Trivial - remove stray characters from a comment block.
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Marc Jones <marcj303@gmail.com>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5789 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-08 21:30:07 +00:00
Kevin O'Connor c3c9b01efb Code must not access the smbus registers before the RTC power well is
ready (PSON gating).  Some boards boot faster than this power well
stabilization, and thus see bad data when accessing the smbus
registers.

Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5788 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-08 11:00:25 +00:00
Patrick Georgi a4c0a1d6e6 Make timer2 the default choice for TSC initialization.
For boards where timer2 is unusable, there's still the IO based
initialization available using the Kconfig option TSC_CALIBRATE_WITH_IO

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Kevin O'Connor <kevin@koconnor.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5787 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-08 10:58:02 +00:00
Kevin O'Connor 24f83a76ae It should not be necessary to read in the rom during CAR setup.
Removing the code preloading reduces the boot time.

Preload code is enabled when doing CARTEST (not exposed
to Kconfig given that it's a pure debugging measure)

Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5786 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-08 10:53:44 +00:00
Liu Tao e914b501d2 Changes to str*cmp functions. Fixes a couple more corner cases.
Signed-off-by: Liu Tao <liutao1980@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5785 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-08 10:27:13 +00:00
Myles Watson fe09fd1dac My Jmicron SATA card depends on the BIOS not clearing AL when setting AH.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5784 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-07 23:27:59 +00:00
Myles Watson 6c9bc01b0e Make a Kconfig option for debugging output from realmode emulation. Trivial.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5783 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-07 22:30:15 +00:00
Jens Rottmann c137385404 Add support for LiPPERT Cool LiteRunner-LX (PC/104 board with AMD
Geode-LX, CS5536, ITE IT8712F), based on very similar SpaceRunner-LX.

Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5782 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-07 17:33:17 +00:00
Rudolf Marek 625a0cb433 Remove unused ide0_enable and sata0_enable entries from SB7xx
and SB600.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5781 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-07 09:18:08 +00:00
Kevin O'Connor 3e4daf1345 2ms is enough time to accurately obtain the clock rate.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5780 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-07 07:53:26 +00:00
Aurelien Guillaume 34697d67c1 Set up an arbitrary amount of system memory on Geode LX, so
coreboot_ram can be unpacked to 1MB. The value is quickly
replaced with the real value later, thus causing no harm.

Move RAMBASE to the default of 1MB for the affected boards

Signed-off-by: Aurelien Guillaume <aurelien@iwi.me>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5779 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-07 07:43:10 +00:00
Kevin O'Connor 31b2e8f566 Instead of requiring users to modify qemu to allow writes to
0xc0000-0xfffff, have coreboot qemu support enable the memory range at
startup.

Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5778 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-06 20:20:47 +00:00