This patch adds support for the Gru rev1 board. This board differs from
rev0 by no longer relying on the I2C backlight booster and requiring the
same ODT SDRAM settings as newer Kevin boards.
BRANCH=None
BUG=chrome-os-partner:55087
TEST=None
Change-Id: I1428760540a0aaaa0c02c6cb5b0981294ba4df33
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 8de7bcc78c6c48c251c85185e238cea7812f7a28
Original-Change-Id: I3cb49bc644190f35300e6c618b2934956fa88e5b
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/364624
Original-Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://review.coreboot.org/16028
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The Chrome EC codebase no longer supports the google/lars and
intel/kunimitsu boards. Disable the build in those platforms.
Change-Id: Ic4f5a1a34bb19ee31632c1ad8430c30f7154f138
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/15869
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
per hw team's check and info from EDS, this pin needs to be pu 20K.
Otherwise SoC may not notice interrupt request from
EC over LPC because SERIRQ line is floating.
BUG=chrome-os-partner:55586
BRANCH=none
TEST=boot ok and Quanta factory verified the keyboard issue is gone
Signed-off-by: Kane Chen <kane.chen@intel.com>
Change-Id: I5b0213514ce152d4e2cecdda8786925495a0f24a
Reviewed-on: https://review.coreboot.org/15951
Tested-by: build bot (Jenkins)
Reviewed-by: Freddy Paul <freddy.paul@intel.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
This patch enables DPTF support for Google Reef
platform, adds the ASL settings specific to Reef
boards.
BUG=chrome-os-partner:53096
TEST=Verify that the thermal zones are enumerated
under /sys/class/thermal in Reef boards. Navigate to
/sys/class/thermal, and verify that a thermal
zone of type TCPU exists there.
Change-Id: Ib43e4e9dd0d92fffc1b2c8459c552acd04ca0150
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15640
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This removes the newlines from all files found by the new
int-015-final-newlines script.
Change-Id: I65b6d5b403fe3fa30b7ac11958cc0f9880704ed7
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/15975
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Keep this enabled by default as most x86 platforms could have PCI-e
slots equipped with one of these Intel WiFi adapters.
The Kconfig entries under google boards had no function previously,
the variable was never referenced.
Change-Id: I728ce3fd83d51d4e5e32b848a2079c5fcee29349
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15931
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Use the ACPI generator for creating the Chrome OS gpio
package. Each mainboard has its own list of Chrome OS
gpios that are fed into a helper to generate the ACPI
external OIPG package. Additionally, the common
chromeos.asl is now conditionally included based on
CONFIG_CHROMEOS.
Change-Id: I1d3d951964374a9d43521879d4c265fa513920d2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15909
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Due to GPE routing, raw GPIO cannot be used for indicating the wake
signal for touchpad. Instead we need to reference GPE pins.
BUG=chrome-os-partner:55670
Change-Id: Ie5d8473df4301c7beef0cae8fe84e71b2838261b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15947
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
We need to enable DRAM ODT on kevin/gru board to improve the
DRAM signal. Note, if the DRAM ODT is enabled and set to 120ohms,
the sdram VREF need to adjust to 840mv.
This patch also makes following changes:
1. For compatiblity with the old board, add the
"sdram-lpddr3-hynix-4GB-666-no-odt.inc" and
"sdram-lpddr3-hynix-4GB-800-no-odt.inc" files
which do not enable sdram ODT.
2. Delete the 300MHz dram inc file. The 300MHz sdram config just
reduced 666MHz to 300MHz based on the 666MHz config file, and it is
not stable, so delete it.
3. Delete the 928MHz dram inc file, 928MHz sdram config still in
debuging, delete it for now.
BRANCH=none
BUG=chrome-os-partner:54871
TEST=run "stressapptest -M 1024 -s 1000" on kevin board and pass
Change-Id: If0248e1bc4cef2c298762080f1ca018653af0521
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 78d8a28e2d3489c99c9bba2c1c9aa76812e2e33f
Original-Change-Id: I35f0685782d6fb178a95780ec77c45f565dd2194
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/358763
Original-Commit-Ready: Dan Shi <dshi@chromium.org>
Original-Tested-by: Caesar Wang <wxt@rock-chips.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/15813
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Update the write protect GPIO reported in ACPI to GPIO_75.
Also update the controller ID to "INT3452:01" which will
point at the goldmont device and includes write protect GPIO.
BUG=chrome-os-partner:55604
BRANCH=none
TEST=verify crossystem output for wpsw_cur.
Change-Id: Ibe6a013aaab18bfa2436698298177218ca934fab
Signed-off-by: Susendra Selvaraj <susendra.selvaraj@intel.com>
Reviewed-on: https://coreboot.intel.com/7929
Reviewed-by: Petrov, Andrey <andrey.petrov@intel.com>
Tested-by: Petrov, Andrey <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15691
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
1. Currenty, boot reason is being added to elog only for some
ARM32/ARM64 platforms. Change this so that boot reason is logged by
default in elog for all devices which have CHROMEOS selected.
2. Add a new option to select ELOG_WATCHDOG_RESET for the devices that
want to add details about watchdog reset in elog. This requires a
special region WATCHDOG to be present in the memlayout.
3. Remove calls to elog add boot reason and watchdog reset from
mainboards.
BUG=chrome-os-partner:55639
Change-Id: I91ff5b158cfd2a0749e7fefc498d8659f7e6aa91
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15897
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
This is required to enable elog support in ChromeOS by default.
BUG=chrome-os-partner:55639
Change-Id: I9c97143d794de4bf220ddf67c0ca2eac2f7a326d
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15896
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
With VBOOT_VERIFY_FIRMWARE separated from CHROMEOS, move recovery and
developer mode check functions to vboot. Thus, get rid of the
BOOTMODE_STRAPS option which controlled these functions under src/lib.
BUG=chrome-os-partner:55639
Change-Id: Ia2571026ce8976856add01095cc6be415d2be22e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15868
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
VBOOT_VERIFY_FIRMWARE should be independent of CHROMEOS. This allows use
of verified boot library without having to stick to CHROMEOS.
BUG=chrome-os-partner:55639
Change-Id: Ia2c328712caedd230ab295b8a613e3c1ed1532d9
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15867
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The slippy board was a proof of concept device that has never
made it out in the wild. Moreover, I don't think any of these
boards exist any longer.
Change-Id: I24fb08d9be35b2367e7aa64520ce5778ab861535
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15902
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
The bolt board was a proof of concept device that has never
made it out in the wild. Moreover, I don't think any of these
boards exist any longer.
Change-Id: I5ca055d448659a2b8e2eafcfc2114a6b8f8a56a4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15901
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
All mainboards (nyans) utilizing the cache_policy option
has it set to DCACHE_WRITETHROUGH. This option is for setting
the framebuffer's cache attribute. However, this option is
reliant on an architecture-specific enumeration. Just remove
the option and use DCACHE_WRITETHROUGH across the board. If
someone wants to reconfigure it at a later date one can
introduce a non-architecture specific option.
Change-Id: I6a0848231f5e28d36ec2d56b239bed67619fe5a7
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15838
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
We set this driving control to prevent signal attenuation caused by
LVDS DRV termination.
When DA_LVDSTX_PWR_ON is not set, LVSH has no power and LVDS DRV
termination status is unknown(floating). This creates a chance that MIPI
output would be influenced. The DSI's LP signal will be half voltage
attenuation. There will be no display on panel.
When DA_LVDSTX_PWR_ON is set, LVSH and LVDS DRV termination are
effective and termination is fixed OFF. The DSI won't be influenced.
We only need to set this register once, so we set it here to prevent
repeat setting in the kernel when the system goes to recovery mode.
BUG=chrome-os-partner:55296
BRANCH=none
TEST=build pass elm and show ui
The original commit in the cros repo combined the chipset and mainboard
code changes. This has been split for the push to coreboot.org
Change-Id: I733bdd115950b71493856220414ac0dd75d28122
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 0d25a27f300acc4b65a894110d3ee0cc9676cd12
Original-Change-Id: Ie71f9cc41924787be8539c576392034320b57a49
Original-Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/360850
Original-Commit-Ready: jitao shi <jitao.shi@mediatek.com>
Original-Tested-by: jitao shi <jitao.shi@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/15808
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
_Static_assert() gets evaluated even when the code path it's in is
unreachable (e.g. inside an if (0) block). Unfortunately, Kconfigs that
depend on a disabled Kconfig are always 0, meaning that
CONFIG_CONSOLE_SERIAL_UART_ADDRESS on Gru cannot evaluate to UART2 when
CONFIG_CONSOLE_SERIAL (which it depends on) is disabled. Switch the
condition it is wrapped in to a preprocessor #if so that the
_Static_assert() is not evaluated when building without serial support.
BRANCH=None
BUG=None
TEST=Built and booted Kevin without serial
Change-Id: I391325fcc4b7d64b4866a7fce4444e2f28365b7d
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: f5e5cf0644154eca5b347ea381df3f6b28287524
Original-Change-Id: I33d51d4ef09b218c14173d39a12795f0cef6bb40
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/361581
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/15810
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Fix the board ID handling.
Recovery switch and WP status GPIO has been reassigned in board rev3.
Configure related GPIOs based on Board ID.
BUG=chrome-os-partner:55320
TEST=Verified GPIO assignment for Rev.1 board.
BRANCH=None
Change-Id: Id8e1ba1c039f8b5b503f0da038e5cfc84b72678f
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: d295ab514e31d9ebd1b77e0af9b769e64cbf567e
Original-Change-Id: I6d3d5df2e9017f7845edc3cd0b2c19ad7c58a97c
Original-Signed-off-by: Kan Yan <kyan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/361393
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://review.coreboot.org/15809
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
1. Remove unused functions/structures.
2. Add checks for NULL return values.
3. Change prefixes to vb2 instead of vboot for functions used internally
within vboot2/
4. Get rid of vboot_handoff.h file and move the structure definition to
vboot_common.h
5. Rename all functions using handoff structure to have prefix
vboot_handoff_*. All the handoff functions can be run _only_ after cbmem
is online.
6. Organize vboot_common.h content according to different
functionalities.
BUG=chrome-os-partner:55431
Change-Id: I4c07d50327d88cddbdfbb0b6f82c264e2b8620eb
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15799
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
All the mainboards share the same config options for CHROMEOS. Instead
of duplicating those in every mainboard, move the CHROMEOS config to SoC
and make it dependent on MAINBOARD_HAS_CHROMEOS.
BUG=chrome-os-partner:55431
Change-Id: Iafabb6373dfe16aaf0fe2cbc4e978952adeb403e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15822
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
All the mainboards share the same config options for CHROMEOS. Instead
of duplicating those in every mainboard, move the CHROMEOS config to SoC
and make it dependent on MAINBOARD_HAS_CHROMEOS.
BUG=chrome-os-partner:55431
Change-Id: I2d54ff6beac9fca7596a8f104e3c1447cada5c05
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15821
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
This device has a built-in keyboard that should be enabled by default
or it will not work in firmware. This was tested to ensure that TAB
(display info) and Ctrl+D (enter developer mode) are functional at the
Chrome OS recovery screen.
BUG=chrome-os-partner:55549
Change-Id: I60156f1fc001b88deac69e03e02e9d8277fbc38d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15782
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
The 'dram density' is a misnomer because the memory initialization
code treats that input parameter as a per rank density. Therefore,
update the variables to further clarify how it's actually being
used.
BUG=chrome-os-partner:55446
Change-Id: Ie4c944f35b531812205ac0bb1c70f39ac401495e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15773
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The 16Gb devices use two ranks per channel within the DRAM module.
However, the density settings are really on a per rank basis so
indicate dual rank with a device density of 8Gb.
BUG=chrome-os-partner:55446
Change-Id: Ib5dba6f9ed248750d68b726996c71def9b75961e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15772
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
The EVT board uses an active high power control signal while
the previous board used an active low signal. Update the tables
to reflect the differences.
BUG=chrome-os-partner:55470
Change-Id: I198c0e4e019fcffe2cf748d382351ac965a81077
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15763
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
I mistakenly assumed the order of the bits matched how one
would assign values as they wrote them msb .. lsb. However, the
gpio lib doesn't do that. Correct the order so that values are
read out correctly.
BUG=chrome-os-partner:54949t
Change-Id: I5304dfe2ba6f8eb073acab3377327167573ec2cc
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15753
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
EVT has a wake signal for track pad which is routed to GP_15.
BUG=chrome-os-partner:54960
Change-Id: I9a73a3dc74e3bbed63509a3c076ec17a6559da55
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15723
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The Chrome OS options that will be shipped on this platform were
being set in the chromium repo with an external config file. Set
the options in the mainboard Kconfig file so there's no discrepancy
as to what will be used.
Change-Id: I05f0d1245611c16f54273728519a08e6edff3429
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15733
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
In order to save power in S3, we remove reset gpio setting in kernel.
We still need to initialize touchscreen ic.
Do it by pulling low reset gpio for 500us and then pulling high
in firmware.
BRANCH=none
BUG=chrome-os-partner:55170
TEST=build on elm.
Change-Id: Idbe0175a1fc1fa0b05e81706194c79d52c6101f6
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: f40cc9a22c2551c2c9455cb8b60f36353602bca6
Original-Change-Id: If2ac815c4fd5c5ae15443348a49eb31449b724b1
Original-Signed-off-by: YH Huang <yh.huang@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/360312
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Johnny Chuang <johnny.chuang@emc.com.tw>
Reviewed-on: https://review.coreboot.org/15719
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Asserting this GPIO will send a signal to the EC to trigger a reset
for the AP and the CR50.
BRANCH=none
BUG=chrome-os-partner:55252
TEST=the device now reboots when it needs to switch between different
boot modes instead of hanging with "failed to reboot" message.
Change-Id: I8d168e313b6983c96c80f7ad6d70bb84c1ec1d9c
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 83a4c8ff68ab24a103f2166e948eb23624ea97f7
Original-Change-Id: Idfd20977cf3682bd8933f89e8eec53005e55864e
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/360238
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/15718
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Since the Integrated Sensor Hub can be disabled through devicetree.cb
as a PCI device, there is no need for a separate register variable.
Remove handling the register and update mainboards' devicetrees. Also
keep ISH disabled on both Reef and Amenia.
Change-Id: I90dbf57b353ae1b80295ecf39877b10ed21de146
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15710
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch adds support to wake up from S3 on lidopen.
mainboard.asl has the _PRW defined for the wakeup support
in S3.
BUG = chrome-os-partner:53992
TEST = Reef board wakes up from S3 on lidopen.
Change-Id: Ic3bae26cea0642f98d938b3523d08f5902a1f4b5
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15643
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use the acpi_is_wakeup_s3() API instead of comparing
a raw value to a global variable. This allows for
easier refactoring.
Change-Id: I2813b5d275cbe700be713272e3a88fdb5759db99
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15690
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The mainboard_smi_sleep() function takes ACPI sleep values
of the form S3=3, S4=4, S5=5, etc. All the chipsets ensure
that whatever hardware PM1 control register values are used
the interface to the mainboard is the same. Move all the
SMI handlers in the mainboard directory to not open code
the literal values 3 and 5 for ACPI_S3 and ACPI_S5.
There were a few notable exceptions where the code was
attempting to use the hardware values and not the common
translated values. The few users of SLEEP_STATE_X were
updated to align with ACPI_SX as those defines are
already equal. The removal of SLEEP_STATE_X defines is
forthcoming in a subsequent patch.
BUG=chrome-os-partner:54977
Change-Id: I76592c9107778cce5995e5af764760453f54dc50
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15664
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch adds a mainboard SMI handler file which has
functions to set proper Wake mask before going to sleep
so that system can wake up on lidopen, key press etc.
Also SCI mask is set on boot which will enable timely update
of battery UI on charger connect/disconnect.
BUG = chrome-os-partner:53992
TEST = Reef Platform wakes from S3 on lidopen, key press and also
sysfs entry for AC is updated on charger connect/disconnect.
Change-Id: I8c087994b48223b253dcf1cbb3ed3c3a0f366e36
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15615
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
