Commit graph

1801 commits

Author SHA1 Message Date
Uwe Hermann
7f3d48c9af CK804 coding-style fixed based on an 'indent' run (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3631 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-02 18:19:17 +00:00
Ronald G. Minnich
5107174459 This is so that people can see it. This is the sb600 for v3. It almost
certainly won't build -- that comes later. I am hoping to get some 
eyeballs on it for simple errors. 

rs690 is next. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3630 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-02 15:42:14 +00:00
Carl-Daniel Hailfinger
248a7df94a Fix a typo.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3629 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-02 01:35:03 +00:00
Carl-Daniel Hailfinger
bdb96f8abe Use easily readable macros to setup interrupt routing.
Change a few PCI bus/dev/fn to use hexadecimal numbers.
Kill unused variables.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3628 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-02 00:52:53 +00:00
Marc Jones
5263b01657 Missed a CONFIG_USE_PRINTK_IN_CAR define for the Asus m2v-mx_se.
This fixes that build error. (trivial)

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Marc Jones <marc.jones@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3627 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-01 22:15:20 +00:00
Uwe Hermann
b816d332a3 Enable all available devices on the ASUS A8N-E (trivial).
This is in preparation for actually making the devices work (which needs
some extra code). Also, fix the incorrect mainboard subsystem IDs.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3625 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-01 13:10:39 +00:00
Carl-Daniel Hailfinger
2ee6779a64 The ARRAY_SIZE macro is convenient, yet mostly unused. Switch lots of
code to use it. That makes the code more readable and also less
error-prone.

Abuild tested.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3624 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-01 12:52:52 +00:00
Uwe Hermann
336935c378 Coding-style fixes and simplifications for the ASUS A8N-E (trivial).
The only non-cosmetic change is s/A8NE/A8N-E/ for the board name.
This is build-tested by me.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3622 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-30 15:02:40 +00:00
Mats Erik Andersson
45db366d5c A duplicate register address is incremented in table register_values.
A trivial fix to correct the address of the high byte in SDRAMC.
Thus the leadoff timing IPDLT will be correctly referenced.

Signed-off-by: Mats Erik Andersson <mats.andersson@gisladisker.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3620 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-30 04:52:29 +00:00
Marc Jones
2080bd9a41 AMD K8 platforms must use CAR so it makes sense to use the PRINK_IN_CAR
option.
This patch converts the following patches to use PRTINK_IN_CAR
amd/serngeti_cheetah
msi/ms9185
msi/ms9828
supermicro/h8dmr

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3617 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-29 22:59:23 +00:00
Marc Jones
b5623d18cc This patch for the AMD K8 allows a single DIMM to be populated in the
ChannelB slot. Previously a DIMM could only be populated in ChannelB
if there was a DIMM already in ChannelA. This patch doesn't allow unmatched
DIMMs to be populate in ChannelA and ChannelB. In an A & B configuration
the DIMM must still be matched.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3614 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-29 18:09:51 +00:00
Stefan Reinauer
830b17d3e3 fix ppc mainboards (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3612 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-27 08:51:11 +00:00
Marc Jones
ecd176f304 This patch fixes the dbm690t keyboard not working issue. It should also
fix the a8n_e and any other it8712f SIO keyboard issues. The it8712f
requires an archaic PS/2 mode setting to the keyboard controller before
accessing the keyboard. Beyond that, I made the keyboard controller and
keyboard init more robust and added more informative debug output.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3610 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-26 19:15:38 +00:00
Marc Jones
96bcc53071 Add IRQ12 to the dbm690t mptable for mouse interrupt support.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3603 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-26 17:41:34 +00:00
Ed Swierk
f69d5ee13c Support for the memory controller and PCIe interface of the Intel
EP80579 Integrated Processor (codename "Tolapai"). The memory
controller code supports only 64-bit-wide DIMMs with x8 devices and
ECC. It has been tested on a development board using a single Micron
MT9HTF6472PY-667D2 DIMM. Your mileage will definitely vary with other
DIMMs.

Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Joseph Smith <joe@settoplinux.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3600 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-24 15:06:34 +00:00
Rudolf Marek
4590ce2b3c This patch adds support for watchdog kill and adds it to Asus M2V-MX SE.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Marc Jones <marc.jones@amd.com> 



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3595 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-23 22:26:27 +00:00
Marc Jones
3aca4b5734 The AMD dbm690t mainboard uses the it8712f SIO with the
default 48MHz clock input. The Asus a8n_e uses the it8712f
with a 24MHz clock input. The it8712f early init code was
setting a 24MHz input clock(to support the a8n_e).
Since 48Mhz is the default I added a function to set 24MHz
input clock to the a8n_e.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Rudolf Marek <r.marek@assembler.cz>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3594 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-23 22:19:27 +00:00
Rudolf Marek
0f4282b538 Attached patch removes HPET info from ACPI tables. HPET does not work fine on
VT8237R (random keyboard/mouse lockups).

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3593 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-23 21:57:33 +00:00
Rudolf Marek
05839975bf Following patch adds support for Asus M2V-E SE. Works pretty well, the only
problem left is with CPU scaling setup. No VGA - may work with the Xorg drivers
recently released, maybe with OpenChrome too.

It wont work with the little patch which will hop in soon

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Ward Vandewege <ward@gnu.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3591 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-23 20:36:03 +00:00
Michael Xie
80d7c85fb9 Patch for AMD DBM690T board.
Signed-off-by:  Michael Xie <Michael.Xie@amd.com>
Reviewed-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3590 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-22 13:16:18 +00:00
Michael Xie
7586cef37a Patch for AMD SB600 chipset.
Most of the functions in SB600 are enabled except power management.

Signed-off-by:  Michael Xie <Michael.Xie@amd.com>
Reviewed-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3589 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-22 13:11:39 +00:00
Michael Xie
06755e404e Patch for AMD RS690 chipset.
All the PCIe slots are enabled in this patch except power management.

Signed-off-by: Michael Xie <Michael.Xie@amd.com>
Reviewed-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3588 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-22 13:07:20 +00:00
Rudolf Marek
0b0771d180 Attached patch fixes at least one issue ;) During the PCI BAR sizing must be the
D1F0 bridge without activated I/O and MEM resources, otherwise it will hang
 whole PCI bus.

 U-boot is also disabling the IO/MEM decode when sizing the BARs, dont know why
 does we not.

 Second small change just changes a bit which controls the PSTATECTL logic.

 Third change deals with the integrated VGA, which needs to be enabled early,
 so the VGA_EN is set along the bridges, and PCI K8 resource maps are set
 correctly. Finally the CPU accessible framebuffer is now disabled as it is not
 needed.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3587 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-19 22:58:59 +00:00
Marc Jones
c4128cfbec Whitespace and style cleanup. (trivial)
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Marc Jones <marc.jones@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3586 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-19 21:19:46 +00:00
Michael Xie Michael.Xie
8d183c5846 Add AMD K8 S1G1 socket support.
Signed-off-by:  Michael Xie Michael.Xie@amd.com
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3585 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-19 20:16:25 +00:00
Myles Watson
64caf3607e ck804 whitespace fixes
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3584 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-18 16:27:00 +00:00
Myles Watson
a67c354cbf Fix whitespace in tyan s289{1,2,5} files. Also removes some #if 0 and #if 1
that don't seem to clarify anything.  Abuild tested.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3583 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-18 15:30:42 +00:00
Alex Mauer
229c20f3e2 For the jetway jf2/4 series of mainboards:
* change the comment for device f.0 from "IDE" to "SATA"
* turn on firewire device a.0
* turn on pata device f.1
* don't turn on the unusable device 10.5 (built-in vt8237 ethernet?)

Signed-off-by: Alex Mauer <hawke@hawkesnest.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3577 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-12 20:39:04 +00:00
Stefan Reinauer
f657d75375 From Vincent Legoll:
Use dev_path() to have nice debug output
patch is run-time tested

Trivial, thus:
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3572 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-11 06:52:22 +00:00
Alex Mauer
9196dd553d Add the "jetway j7f[24]*" mainboard. As compared to the Via Epia CN, this
changes the superio to a Fintek F71805F as described at
http://www.coreboot.org/Jetway_J7F2_Build_Tutorial

It also creates the mainboard tree for this series of motherboards
(Jetway J7F2 and J7F4).  I've tested it with one motherboard
(J7F2WE1G3), and I believe it works with the others, as the differences
among them are mostly trivial (processor speed, chipset and quantity of
LAN cards, audio chipset, etc.).  A list of the relevant motherboards
with specs can be found at
http://www.jetway.com.tw/jw/ipcboard_socket.asp?platid=16

The irq_tables.c is copied directly from the epia-cn, because the one
generated by getpir with the factory BIOS did not work properly while
the EPIA-CN one did.

Minor changes on checkin to cope with moved romcc in latest revision.

NOTE: This board is broken until the issue introduced in r3567 is resolved.

Signed-off-by: Alex Mauer <hawke@hawkesnest.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3571 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-10 20:40:46 +00:00
Rudolf Marek
d9f29c8e5e This patch adds support for the VIA VT8237S south bridge. The VT8237R programming remains unchanged (tested
on mine desktop) except of reverting the small change introduced by Bari
(gpio/inta setup reg 0x5b). This should go for some board specific file. The
change would broke at least mine board. But seems to be needed for jakllsch.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Bari Ari <bari@onelabs.com> 



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3567 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-05 18:20:57 +00:00
Carl-Daniel Hailfinger
00809ebf02 This changes the python generated makefiles
targets/*/*/Makefile
        targets/*/*/normal/Makefile
        targets/*/*/fallback/Makefile

to use a common copy of romcc, and to leave this compiler untouched by
'make clean' in targets/*/*/fallback/ and targets/*/*/normal/ .
'make clean' in targets/*/*/ will clean romcc.

Thanks to Mats for the initial idea and implementation of a tool to do
this. This patch has almost the same behaviour as the original tool
without having to run the tool each time.
Tested for abuild-friendliness.

The patch saves ~10-12 seconds for every target using romcc. For a full
abuild run, this is ~20% time saved.
For the first 38 abuild targets, total build time is down to 13m24s
instead of 16m22s on my machine.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Mats Erik Andersson <mats.andersson@gisladisker.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3564 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-04 13:44:00 +00:00
Ed Swierk
1149a3692f Tidy up identifiers, per Uwe's suggestion. Trivial.
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Ed Swierk <eswierk@arastra.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3563 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-03 23:32:30 +00:00
Bari Ari
d4759d0f22 This patch gets the Epia-CN working without ACPI or APIC.
All devices work, no irq storms. Enjoy.

Signed-off-by: Bari Ari <bari@onelabs.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3556 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-01 01:48:07 +00:00
Ed Swierk
d39aad9323 Add definitions for DDR2 SPD registers.
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3547 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-28 18:23:58 +00:00
Ed Swierk
7eda890d9a Eric Biederman believes that he and Tom Zimmerman of the defunct
LinuxNetworx own the copyright for the Intel e7520, e7525 and 3100
raminit code.

Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3546 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-28 18:22:40 +00:00
Ward Vandewege
ec2bd53c37 If you have
option CONFIG_COMPRESSED_PAYLOAD_LZMA=1
  option CONFIG_PRECOMPRESSED_PAYLOAD=1

set in Config.lb but accidentally use an uncompressed payload, coreboot (v2)
bombs out like this:

  elfboot: Attempting to load payload.
  rom_stream: 0xfffc0000 - 0xfffdefff
  Uncompressing to RAM 0x01000000 Decoder scratchpad too small!
  Decoding error = 1
  Unexpected Exception: 6 @ 10:04000408 - Halting
  Code: 0 eflags: 00010057
  eax: 00000101 ebx: 04000400 ecx: 000003d4 edx: fffc0000
  edi: 04000400 esi: 04000401 ebp: 04000400 esp: 0013dfb4

The attached patch modifies v2's lzma code so that it assumes an uncompressed
payload if it fails to find a properly compressed payload.

Compare with the fatal error above:

  elfboot: Attempting to load payload.
  rom_stream: 0xfffc0000 - 0xfffdefff
  Uncompressing to RAM 0x01000000 Decoder scratchpad too small!
   olen = 0x00000000 done.
  Decompression failed. Assuming payload is uncompressed...
  Found ELF candidate at offset 0
  header_offset is 0
  Try to load at offset 0x0

If you don't have CONFIG_COMPRESSED_PAYLOAD_LZMA and
CONFIG_PRECOMPRESSED_PAYLOAD set and use an uncompressed payload, things are as
before:

  elfboot: Attempting to load payload.
  rom_stream: 0xfffc0000 - 0xfffdefff
  Found ELF candidate at offset 0
  header_offset is 0
  Try to load at offset 0x0

One can argue that this is a case of 'builder beware', but my counter argument
is that anything that causes unexpected runtime breakage is really, really,
really bad, and should be avoided where possible.

This patch also fixes one erroneous comment.

Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3542 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-27 21:53:11 +00:00
Ed Swierk
6adfaa690c This patch adds PCI device IDs for the Intel EP80579 Integrated Processor,
and renames some existing macros for clarity.

Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3536 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-25 17:02:09 +00:00
Ed Swierk
6c66c95787 This patch modifies the Intel 3100 southbridge code to recognize the
integrated LPC, SMBus, USB and SATA devices of the Intel EP80579
Integrated Processor.

Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3535 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-25 14:45:00 +00:00
Ed Swierk
1996313756 This patch implements support for the CPU core of the Intel EP80579
Integrated Processor.

Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-25 14:41:11 +00:00
Arne Georg Gleditsch
33e6d5dec6 Add Tyan S2912 platform with AMD Family 10 support.
Thanks Arne. Good job.

Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numascale.com>
Acked-by: Marc Jones <marc.jones@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3526 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-19 17:59:34 +00:00
Stefan Reinauer
8e65adb67d Fix outb to 0x80 delay functions to use inb instead (fixes excessive post codes
in a couple of occurences)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3509 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-13 12:16:15 +00:00
Marc Jones
b865070023 License updated to GPL v2.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3504 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-12 19:45:12 +00:00
Ward Vandewege
dc93affe72 Enable both IDE ports for our qemu target.
Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3481 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-08 00:08:01 +00:00
Marc Jones
a2c951edf7 Clean up whitespace and comments style. (trivial)
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Marc Jones <marc.jones@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3480 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-07 22:00:51 +00:00
Uwe Hermann
5f1037cb69 Initial support for the ASI MB-5BLGP (Neoware Eon 4000s).
This works fine in Linux if you use the 'irqpoll' kernel command
line option.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3469 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-04 15:40:45 +00:00
Stefan Reinauer
9ecf8fb1cf Remove welcome message from elfboot. None of the other subsystems have their
own welcome message.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3468 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-03 10:38:26 +00:00
Stefan Reinauer
912857ec6c fix lots of warnings for cache as ram builds (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3467 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-03 10:35:06 +00:00
Stefan Reinauer
87c938f139 adapt Uncompressing.. patch for AMD code. Also replace "linxbios" by "coreboot"
in a number of places.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3466 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-02 19:17:42 +00:00
Stefan Reinauer
685240610b Go back to SIPI WAIT state for those CPUS defining the newly introduced
CONFIG_AP_IN_SIPI_WAIT flag. Newer Intel CPUs need this to operate with
multiple cores.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3465 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-02 15:15:23 +00:00
Stefan Reinauer
a56edacbe3 This patch
* fixes a warning
* puts some debug messages to spew because they're only useful to debug CAR
* print an explicit message "Uncompressing..." instad of "Copying..." when 
  coreboot_ram.rom is compressed.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3463 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-02 15:09:12 +00:00
Stefan Reinauer
db1b608fca oops, forgot these in the cleanup.. (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3461 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01 19:22:34 +00:00
Stefan Reinauer
11a2014f49 a heuristics is something different
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3460 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01 13:08:33 +00:00
Stefan Reinauer
75f519ca86 Typo, thanks to Idwer for spotting this. (trivial patch)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3459 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01 12:53:04 +00:00
Stefan Reinauer
51754a38f2 clarify in the printks what function is actually called. This little smart magic
drove me crazy during debugging. Fix Typos. Add a warning because the
on-chipset devices are hardcoded. For newer machines, a lot more memory space
will have special meanings, and we can't hardcode them all in an ifdef desert.

(trivial)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3458 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01 12:28:38 +00:00
Stefan Reinauer
1409136281 clean out obsoleted config.lb rules and output, fix indenting (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3457 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01 12:20:26 +00:00
Stefan Reinauer
48b85fc6a9 use printk, when possible. (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3456 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01 12:12:37 +00:00
Stefan Reinauer
5a522d4a42 match against all steppings of a CPU model, because these are _model_ drivers.
(trivial)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3455 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01 12:11:00 +00:00
Stefan Reinauer
ac555b1c69 serial.inc is not used anywhere. drop it (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3454 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01 12:06:08 +00:00
Stefan Reinauer
57d2af895e same spelling in all mtrr output.. (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3453 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01 11:54:55 +00:00
Stefan Reinauer
df6c858218 drop unused code (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3452 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01 11:53:39 +00:00
Stefan Reinauer
96a60363f8 coding style fixes (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3451 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01 11:50:52 +00:00
Stefan Reinauer
20ffc03efa fix compile warnings of rom_stream.c (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3450 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01 11:48:00 +00:00
Stefan Reinauer
951c62f074 add some SPD values from specs. (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3449 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01 11:40:16 +00:00
Stefan Reinauer
a91e0fe441 function prototypes don't need extern. (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3448 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01 11:39:35 +00:00
Stefan Reinauer
749c05e0fd fix warning in vga console code (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3447 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01 11:38:23 +00:00
Stefan Reinauer
fec2c4f47f fix typo in coreboot_ram.ld comment (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3446 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01 11:37:33 +00:00
Stefan Reinauer
bba53ed1a7 fix typo in commend of generic_sdram.c (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3445 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01 11:36:40 +00:00
Stefan Reinauer
3c580b539e clean up comment in onboard.c (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3444 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01 11:35:46 +00:00
Stefan Reinauer
807dec0ebc clean up Config.lb in lib/ (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3443 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01 11:32:12 +00:00
Stefan Reinauer
7a4f688f4f fix warnings, make mptable struct members explicitly packed, as they're
supposed to be. rename LXBIOS to CORE in ACPI table identifiers. (trivial)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3442 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01 11:31:08 +00:00
Stefan Reinauer
d98cf5bed9 fix typos and warnings in the device tree code (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3441 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01 11:25:41 +00:00
Roman Kononov
96e3022cd4 This patch fixes the kernel EBDA mislocation problem. Thank you, Yinghai.
The change in tables.c protects the legacy x86 BIOS data segment
(0x400-0x4ff) from being used for storing coreboot tables. Some
bytes from the segment are used by the kernel and should not be
garbled.

The change in coreboot_table.c is not strictly necessary. It removes
some redundancy and confusion.

Signed-off-by: Roman Kononov <kononov@dls.net>
Acked-by: Marc Jones <marc.jones@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3437 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-23 23:22:59 +00:00
Marc Jones
2aa804fdcc Fix r3434 check-in. Added missing end to Options.lb. Not entirely sure how it
went missing....

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Marc Jones <marc.jones@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3436 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-23 22:27:19 +00:00
Marc Jones
35b5361636 Add AMD Fam10 B3 default settings to match AMD example code.
Includes setting for most recent errata.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3435 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-23 21:44:23 +00:00
Marc Jones
51737cf7da Update to the latest AMD Fam10 microcode patches.
Add platform option for patch file name.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3434 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-23 21:11:20 +00:00
Marc Jones
c3ec1ac331 Memory initialization support for AMD Fam10 B3 (B0-B2 already supported).
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3433 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-23 21:04:03 +00:00
Marc Jones
3a8556354d Missed a const in my previous checkin, r3426 (trivial).
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Marc Jones <marc.jones@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3432 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-21 22:23:57 +00:00
Sean Nelson
3d135e6033 Add support for the Winbond W83697HF Super I/O.
Signed-off-by: Sean Nelson <snelson@nmt.edu>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3430 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-21 14:49:04 +00:00
Marc Jones
eafceddf6c Add manual HT BUID fixup to detect previously set BUIDs in early init. This fixes the non-coherent(sb) link running at default speed.
Fix HT event notify to output useful information.

Signed-off-by: Marc Jones <marc.jones@amd.com>

Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3426 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-17 19:54:06 +00:00
Marc Jones
212486e9f6 Clean up AMD FAM10 HT variable initialization. The structure init is cleaner, avoid compiler warnings, and matches the AMD example code more closely.
Signed-off-by: Marc Jones <marc.jones@amd.com>

Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3425 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-17 19:50:37 +00:00
Marc Jones
2df291574d Add Fam10 Gart table walk enable for MCA reporting to match AMD example code.
Signed-off-by: Marc Jones <marc.jones@amd.com>

Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3424 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-17 19:44:08 +00:00
Marc Jones
aee0796506 Clean up comments, whitespace, and copyright date in the AMD HT code.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Marc Jones <marc.jones@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3423 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-16 21:09:31 +00:00
Uwe Hermann
049814cc8f Add missing Intel CPU (trivial).
Tested by me on actual hardware.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3422 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-15 13:22:21 +00:00
Marc Jones
2c39c4c5a9 There was a programming error which made most USB port4 setup wrong. This patch uses byte pointer and the MMIO read and write functions.
Signed-off-by: Marc Jones <marc.jones@amd.com>

Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3421 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-12 00:03:26 +00:00
Patrick Georgi
c2e8fd42b0 Adds a field to the serial port descriptor about the configured line speed.
Signed-Off-By: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3396 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-29 06:41:12 +00:00
Uwe Hermann
98f32bf8ef Initial support for the A-Trend ATC-6240 board.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3391 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-26 19:42:25 +00:00
Ronald Hoogenboom
fb73fa1bcb Enable hardware fan control for m57sli.
Tested on v1 and v2 of the board.

Signed-off-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl>
Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-22 14:33:17 +00:00
Joseph Smith
14669ae023 This patch allows support for multiple so-dimms, single or double sided.
Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Peter Stuge <peter@stuge.se>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3380 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-22 04:22:46 +00:00
Bari Ari
4e48408059 Extend the VIA vt8237r southbridge decode range for the ROM to 1MB.
Signed-off-by: Bari Ari <bari@onelabs.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3369 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-20 00:01:14 +00:00
Myles Watson
42319797a6 This is a simple patch which allows payloads to be placed in memory in
the range of 0xf0000-0x100000, where the Coreboot tables live in v2.
As long as the payload doesn't need the tables, it seems harmless, so
why not just print a warning?

This allows v2 to load "legacybios" without having to have a separate loader.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
It'll be fine for testing and doesn't really break anything that did
work before...

Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3343 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-21 22:10:38 +00:00
Corey Osgood
9d10dc4ffc Add post-RAM init code for the Fintek F71805F Super I/O.
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Richard Stellingwerff <remenic@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3335 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-20 18:10:24 +00:00
Aaron Lwe
fcb2a311c7 Add support for the VIA EPIA-CN baord, which uses C7 + CN700 + VT8237R.
This also contains various improvements of the CN700 code in svn.

Signed-off-by: Aaron Lwe <aaron.lwe@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3334 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-19 12:17:43 +00:00
Uwe Hermann
85e46e6bd6 Doesn't have to be executable (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3330 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-16 18:56:24 +00:00
Marc Jones
2ee5c9e21b Geode platforms that use a LPC Super I/O had the LPC serial IRQ set to all
the possible IRQs generated by the SIO. This included IRQ 7 as the default
parallel port IRQ. This overlapped with the MFGPT driver setting IRQ7 for it's
own use. This fix removes IRQ7 from the serial IRQ list for all the mainboards
that were setting it to prevent the conflict and crash when the MFGPT driver
loads.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3329 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-16 18:08:54 +00:00
Joseph Smith
0fd8ccd7e7 New Target and initial support for the Thomson IP1000.
Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3328 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-16 15:43:35 +00:00
Joseph Smith
da69582ce4 This patch allows the RCA RM4100 to reboot. Upon rebooting in auto.c it detects if the memory is already initialized, if so it issues a hard reset through the southbridge.
Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3322 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-15 13:44:33 +00:00
Jordan Crouse
fa36f5048f coreboot-v2: Disable second serial port on Norwich
There isn't really any good reason to have the second serial port
enabled on Norwich, and this makes the X DDC code stop working.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3294 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-09 15:32:46 +00:00
Ed Swierk
83a965d2ef Implement GPIO configuration routines for the Intel 3100 southbridge,
allowing you to specify per-mainboard GPIO settings.

Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3290 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-07 21:57:12 +00:00
Marc Jones
9d9518ff54 cs5536 IDE PWB flag was not getting set since it is 1<<14 and it was only doing a
pci_write_config8.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3282 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-06 16:56:47 +00:00