Commit Graph

48864 Commits

Author SHA1 Message Date
Sean Rhodes 724c0cd5b4 payloads/edk2: Separate the tasks required to build edk2
Separate the tasks that are required to be completed prior to building
edk2 into a prep recipe. This allows this to be used for building
different targets.

This also ensures that the COREBOOT toolchain is used.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ic4ae8ac4118a5747f38297d0fbf4cb53aa3b6d6d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66359
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-08-24 23:58:15 +00:00
Sean Rhodes 147c9578a1 payloads/edk2: Separate the Release String variable
Separate the Release String from the Build String. This allows
the makefile to locate built files more precisely.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Id98674f0bbf485b2bfdbf5784d325c5ac89ad076
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66358
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-24 23:56:46 +00:00
Moises bcfd757961 mb/google/skyrim: Create morthal variant
Create the morthal variant of the skyrim reference board by copying
the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.5.0).

BUG=b:240970782
BRANCH=None
TEST=util/abuild/abuild -p none -t google/skyrim -x -a
make sure the build includes GOOGLE_MORTHAL

Signed-off-by: Moises <moisesgarcia@google.com>
Change-Id: I25c25f067a040e6930f4fc60fadb8be85dc8eda6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-08-24 21:44:58 +00:00
Isaac Lee efade6dd33 mb/google/skyrim: Check if SPD exists
Update the build script to check if SPD exists, and only if SPD exists
the APCB_SBR_D5.gen could be executed.

BUG=None
TEST=Build

Change-Id: Ib7b977a89d403242e8bb1f684269e70082125e88
Signed-off-by: Isaac Lee <isaaclee@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66978
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-08-24 21:44:20 +00:00
Angel Pons 39cb97d64d soc/intel/common/block: Drop empty smm.h
This file has nothing useful. Get rid of it.

Change-Id: Id2a42005d3b4b5161079c9ff48867cfc6fb0413d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-08-24 21:29:24 +00:00
Tim Wawrzynczak ec11a6e5b1 mb/google/brya/var/agah: Reenable ASPM L1 substates
Now that the GPU CLKREQ# signal is working correctly, ASPM L1 substates
can be enabled and appear functional.

BUG=b:240390998
TEST=lspci reports them as functional, MODS does not hang

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I8297f6bbf7f5a1f7d4ac519bc5b7b3112a74a9a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66811
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-24 21:28:57 +00:00
Tim Wawrzynczak 932783daf8 mb/google/brya/var/agah: Update GPU GPIOs
Converge as many of the GPU's GPIOs to use PLTRST# as the reset signal
explicitly, as the hardware engineers requested this.

BUG=none
TEST=boot and reboot agah, dGPU still visible on PCIe bus

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I78e58eb17cadc95083571affbecb4e1ce0adf16a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66809
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-24 21:28:39 +00:00
Tony Huang a1cc78096f mb/google/brya/var/agah: Enable DPTF oem_variables
Support oem_variables and change based on EC notify event.

BUG=b:238921409
TEST=emerge-draco coreboot
1. check ACPI object ODVX has oem_variable[0]=0
Name (ODVX, Package (0x06)
{
   0x00000000,
   0x00000000,
   0x00000000,
   0x00000000,
   0x00000000,
   0x00000000
}
2. check can get EC oem variable change notify in the kernel log

Change-Id: Ibd856563a43d73a3b1be09b3fbebca1b36b5eab1
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66575
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-24 21:28:19 +00:00
Tony Huang a434f6155c ec/google/chromeec/acpi: Add support for DPTF oem variable event notify
The agah EC code will monitor adapter current to choose corresponding
DPTF oem variable table. When it changes, this event will send to the
ACPI FW through host event and then pass onto the DPTF kernel driver.
This patch adds support for that feature.

BUG=b:238921409
TEST=add Printf() calls to the ACPI,
     and check these Printf() will show up in the kernel log
     when EC send oem variable table change notify.

Change-Id: I1dbbfd9b3d65b56d77050c9ba9957e54530c3a0e
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66574
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-24 21:28:06 +00:00
Yu-Ping Wu 30d8e724e7 libpayload: Add const for dma_coherent argument
Add the const modifier for the ptr argument of dma_coherent to avoid
unnecessary type casting in payloads.

BUG=none
TEST=emerge-corsola libpayload
BRANCH=none

Change-Id: Ic4bb1d8318c7e83fd3ab3054aa0333cb27afe588
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Hsin-Te Yuan <yuanhsinte@google.com>
2022-08-24 21:27:46 +00:00
Sean Rhodes 403d22076c payloads/edk2: Move building to directory called workspace
The current edk2 makefile will work in a directory that's name is
derived from the repository, such as `mrchromebox` or `starlabsltd`.

Move this under a directory, so that it can be ignored by git and
so that the makefile can be adjusted to use file targets, rather
than phony recipes with wildcards.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: If0c80dbc59130f229b78cab9578115e14172301d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66356
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-24 21:27:24 +00:00
Subrata Banik 766bd0040f soc/intel/adl: Consider INTEL_TME config prior TME MSR programming
This patch brings INTEL_TME config check prior programming
TME Set Activation Core MSR on all cores.

TEST=Able to boot Google/Taeko to OS.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8af7e305da1050f443929ab33be556e713e53e9a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66976
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-24 21:26:59 +00:00
Sean Rhodes 184ac20fdc mb/starlabs/lite: Enable P2SB
Enable the P2SB so that the SPI is discoverable by the OS.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I9c12161d4868deae5b8900cfa2f42517a9f0b7e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66977
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-08-24 21:25:52 +00:00
Subrata Banik 3befdf1161 drivers: Implement EFI_PEI_MP_SERVICES_PPI with FSP_UNSUPPORTED type
This patch implements EFI_PEI_MP_SERVICES_PPI structure definitions
with APIs that return mp_api_unsupported().

The reason behind this change is to fix an FSP issue where FSP assumes
ownership of the APs (Application Processors) upon passing a `NULL`
pointer to the CpuMpPpi FSP-S UPD.Hence, this patch implements
`MP_SERVICES_PPI_DEFAULT` config to fill EFI_PEI_MP_SERVICES_PPI with
`mp_api_unsupported` APIs.

Later this data structure can be passed to the CpuMpPpi UPD to avoid
APs from getting hijacked by FSP while coreboot decides to set
SkipMpInit UPD.

TEST=Able to build and boot Google/Taeko with this patch.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I31fcaa2aa633071b6d6bfa05dbe891ef87978d2c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-08-24 21:25:34 +00:00
Michał Żygowski 9b0f169d25 soc/intel/alderlake/hsphy: Add support for HSPHY firmware loading
BIOS must send the IP_LOAD HECI command to fetch the firmware for CPU
PCIe Gen5 and upload it via CPU REG BAR prior FSP Silicon Init.
Implementation based on public Slimbootloader's
"Silicon/AlderlakePkg/Library/CpuPcieHsPhyInitLib".

TEST=Boot MSI PRO Z690-A and see the HSPHY FW is loaded.
PCIe x16 Gen3 GPU card started working in the PCIE 5.0 slot.

[DEBUG]  HECI: Sending Get IP firmware command
[DEBUG]  HECI: Get IP firmware success. Response:
[DEBUG]    Payload size = 0x6944
[DEBUG]    Hash type used for signing payload = 0x3

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I6c6c11581e3d3d9bab0131fae6ef487cafe98080
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2022-08-24 17:18:24 +00:00
Jamie Ryu b6c32d7fe4 soc/intel/meteorlake: Enable GPIO 4 bits pad mode configuration
This enables SOC_INTEL_COMMON_BLOCK_GPIO_PMODE_4BITS to support 4 bits
GPIO pad mode to configure native function 8 to 15.

BUG=b:239690757
TEST=build and verify pad mode configuration with Meteor Lake mtlrvp

Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Change-Id: Ibf4b13a3d19095d15bf857c7fe4ec0affb54a4e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66391
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-08-24 15:59:40 +00:00
Jamie Ryu 4b8092aebb soc/intel/common/gpio: Support 4 bits GPIO pad mode configuration
Intel GPIO pad supports 4 bits pad mode, PAD_CFG_DW0[13:10] for pins
that native function 8 to 15 is assigned. This adds native function
definitions from NF8 to NF15 and updates PAD_CFG0_MODE_MASK to support
4 bits pad mode configuration.

Since PAD_CFG_DW0[16:13] is reserved for pins that NF8 or higher is not
assigned, this change would not cause an issue but Kconfig option is
added to minimize an impact and support 4 bits pad mode configuration.

BUG=b:239690757
TEST=build and verify pad mode configuration with Meteor Lake mtlrvp

Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Change-Id: Iefd2daa92a86402f2154de2a013ea30f95d98108
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66375
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-08-24 15:59:14 +00:00
Kevin Chowski 34aa639a26 mb/google/rex: add arbitrage gpio.c header
This comment header is necessary for supporting propagation of overrides
to variants.

Change-Id: Iee92fa4fbc4851c7032401cff99ea49f87717c7f
Signed-off-by: Kevin Chowski <chowski@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-08-24 15:18:50 +00:00
Fabio Aiuto 0805c7010a src/arch/x86/smbios.c: remove unneeded braces
fix the following checkpatch errors:

WARNING:BRACES: braces {} are not necessary for any arm of this statement
354: FILE: src/arch/x86/smbios.c:354:
+	if (CONFIG_ROM_SIZE >= 1 * GiB) {
[...]
+	} else {
[...]

WARNING:BRACES: braces {} are not necessary for single statement blocks
561: FILE: src/arch/x86/smbios.c:561:
+		if (leaf_b_threads == 0) {
+			leaf_b_threads = 1;
+		}

Signed-off-by: Fabio Aiuto <fabioaiuto83@gmail.com>
Change-Id: I14c29e4358cad4cd5ef169ebab7079db2129d8fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66925
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-08-24 15:18:06 +00:00
Matt DeVillier d77525b5bd vc/amd/fsp/mendocino: Update DMI_T17_MEMORY_TYPE
Synchronize with AGESA/AgesaModulePkg/Include/MemDmi.h.
Add/correct values for DDR5, LPDDR5, LPDDR5X.

BUG=b:239000826
TEST=Build and verify with other patches in train

Change-Id: I127f21bfe2dfcd7794eb543185ea3fb362ff3914
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-08-24 15:14:15 +00:00
Yidi Lin 93447c42a8 drivers/spi/tpm: Add Ti50 entry to dev_map
BUG=none
TEST=See "[INFO ]  Initialized TPM device TI50 revision 83"

Signed-off-by: Yidi Lin <yidilin@chromium.org>
Change-Id: I3af5f4653b6b8ecd086f85ec573530a4e5c57211
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66786
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-08-24 14:25:59 +00:00
Angel Pons 4ed0a830b1 mb/**/hda_verb.c: Drop empty files
These files are no longer required by the build system.

Change-Id: I327e7c9211f46d4694591abab11cb38c9180bddb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-08-23 14:04:47 +00:00
Angel Pons a0be874637 {sb,soc}/intel: Do not require hda_verb.c
Just use the conditional inclusion through `device/Makefile.inc`.

Change-Id: Id363a97460ae2cfe4b10d491d4ef06394eb530c2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-08-23 14:04:47 +00:00
Angel Pons ccf8134b5e drivers/siemens/nc_fpga: Fix typo in comment
earyl ---> early

Change-Id: I06412fd9487aaa1115fdbd86ff44b34db97d97d8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-08-23 14:04:22 +00:00
Nick Vaccaro 6afd7273e6 brya: add new skolas variant
Add a new skolas variant, which is a variant of brya's skolas
baseboard.

BUG=b:242869976
BRANCH=firmware-brya-14505.B
TEST=none

Change-Id: I7f9f0389d8b1bf75d8652cbcc9d0c15d3a529802
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-22 23:03:24 +00:00
Felix Singer bbe0a99d66 lint-000-license-headers: Add src/sbom/TAGS to exception list
Commit 6dac0c54cd makes the linter checking for license headers on all
files from the src directory. Since this TAGS file doesn't have one,
it's causing a linter error and it makes the QA system complain.
However, the TAGS file doesn't need a license header and thus add it to
the exception list.

Usually the build tests detect such issues, but commit 1d7a9debf2,
which introduced that file, was merged independently from the other
commit, which modifies the linter. Also, the patch that is introducing
this file was based on an older commit at which the patch modifying the
linter wasn't merged yet and so this issue was hidden.

Change-Id: I78da3fa70c39b709478a384da8769fc058ca18ce
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66938
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-22 20:51:32 +00:00
Subrata Banik 069b6d0479 soc/intel/alderlake: Perform TME core activation on all CPUs
This patch runs `set_tme_core_activate()` on all CPUs (BSP+APs) as
per Alder Lake Processor EDS.

TEST= Able to build and boot Google/Redrix.
Dumping MSR 0x9FF on all logical processors shows zero value being
set.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I130480d4fba413d47d0d0137932ec1fb041a88d8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66753
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-22 17:51:20 +00:00
Subrata Banik 66cd18462c soc/intel/cmn/cpu: API to set TME core activation
This patch implements API to program TME core activation MSR 0x9FF.

Write zero to TME core activate MSR will translate the
TME_ACTIVATE[MK_TME_KEYID_BITS] value into PMH mask register.

Note: TME_ACTIVATE[MK_TME_KEYID_BITS] = MSR 0x982 Bits[32-35]

TEST=Able to build and boot Google/Redrix.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I48cf8e255b294828ac683ab96eb61ad86578e852
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-08-22 17:50:37 +00:00
Felix Singer 88ffed3df8 util/crossgcc: Remove binutils related MIPS patch
coreboot doesn't support the MIPS architecture anymore. So remove the
MIPS patch.

Change-Id: I62a2bca141b42ac33b628c48c84422570f4dda10
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-08-22 16:18:35 +00:00
Maximilian Brune 1d7a9debf2 Add SBOM (Software Bill of Materials) Generation
Firmware is typically delivered as one large binary image that gets
flashed. Since this final image consists of binaries and data from
a vast number of different people and companies, it's hard to
determine what all the small parts included in it are. The goal of
the software bill of materials (SBOM) is to take a firmware image
and make it easy to find out what it consists of and where those
pieces came from. Basically, this answers the question, who supplied
the code that's running on my system right now? For example, buyers
of a system can use an SBOM to perform an automated vulnerability
check or license analysis, both of which can be used to evaluate
risk in a product. Furthermore, one can quickly check to see if the
firmware is subject to a new vulnerability included in one of the
software parts (with the specified version) of the firmware.
Further reference:
https://web.archive.org/web/20220310104905/https://blogs.gnome.org/hughsie/2022/03/10/firmware-software-bill-of-materials/

- Add Makefile.inc to generate and build coswid tags
- Add templates for most payloads, coreboot, intel-microcode,
  amd-microcode. intel FSP-S/M/T, EC, BIOS_ACM, SINIT_ACM,
  intel ME and compiler (gcc,clang,other)
- Add Kconfig entries to optionally supply a path to CoSWID tags
  instead of using the default CoSWID tags
- Add CBFS entry called SBOM to each build via Makefile.inc
- Add goswid utility tool to generate SBOM data

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Icb7481d4903f95d200eddbfed7728fbec51819d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-08-22 14:48:46 +00:00
Subrata Banik 1e71fe107a soc/intel: Enable TME based on supported CPU SKU and config option
This patch removes the static kconfig being used to fill in TME enable
FSP UPD. Instead use`is_tme_supported()` and `CONFIG(INTEL_TME)` to check
if the CPU has required TME support rather than hardcoding.

TEST=FSP debug log shows `TmeEnable` UPD is set appropriately for the
TME-supported CPU SKUs.

As per FSP-M debug log:

Without this CL, Alder Lake-P CPU SKU without TME support:
[SPEW ]   TmeEnable = 0x1

With this CL, Alder Lake-P CPU SKU without TME support:
[SPEW ]   TmeEnable = 0x0

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8aa2922baaf2a49e6e2762d31eaffa7bdcd43b0a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66750
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-21 15:02:31 +00:00
Yu-Ping Wu 28f1729f15 tpm: Correct TI50_FIRMWARE_VERSION_NOT_SUPPORTED help text
Reading firmware_version register is supported on Ti50 version
0.22.4. Therefore correct the help text of the Kconfig option
TI50_FIRMWARE_VERSION_NOT_SUPPORTED.

Also change the message level to BIOS_WARNING.

BUG=b:234533588
TEST=emerge-corsola coreboot
BRANCH=none

Change-Id: I66a0ef896c9dc4cd0f586555a55dbcd1cfd863f9
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66906
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andrey Pronin <apronin@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2022-08-21 15:01:19 +00:00
Yu-Ping Wu 6aec7c57b2 mg/google/corsola: Disable TI50_FIRMWARE_VERSION_NOT_SUPPORTED
Reading Ti50 version is now supported on Ti50 version 0.22.4. Therefore
stop selecting TI50_FIRMWARE_VERSION_NOT_SUPPORTED for corsola.

BUG=b:234533588
TEST=emerge-corsola coreboot
TEST=cbmem -1 | grep 'Firmware version'
BRANCH=none

Change-Id: Id8d849eaf99542363c64e27411549eb6dddfd059
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66905
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andrey Pronin <apronin@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2022-08-21 14:59:51 +00:00
Eran Mitrani 814dded4cd mb/google/rex: Reshuffle CHROMEEC_* related configs
1. Moved CHROMEEC_* to common (required for all boards)
2. added missing EC_GOOGLE_CHROMEEC_SKUID

TEST=Verified with simics on RVP

Change-Id: I26a01e5d1c78d4cd83b1aa53e68b2c3059da6061
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66762
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-21 14:59:08 +00:00
Subrata Banik 29a92e87ca soc/intel/common/block/cpu: API to check if TME is supported
As per the Alder Lake FAS coreboot shall detect the existence of TME
feature by running the CPUID instruction:
CPUID leaf 7/sub-leaf 0
Return Value in ECX [bit 13]=1

If TME is supported then only access to TME MSRs are allowed otherwise
accessing those MSRs would result in GP#.

TEST=Able to detect the existence of TME feature across different
Alder Lake and Meteor Lake CPU SKUs.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ibd4fcf15a66d27748ac7fbb52b18d7264b901cd8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66749
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-08-21 14:58:21 +00:00
Angel Pons 086a91c05c soc/intel: Unravel `INTEL_TME` Kconfig option
The `INTEL_TME` Kconfig option has a prompt, which means it is meant to
be user-configurable. However, it has been selected from Alder Lake and
Meteor Lake Kconfig, so `INTEL_TME` cannot be disabled on them. Replace
the `select INTEL_TME` statements with default values in order for this
option to be user-configurable on all platforms that support it.

Change-Id: Ib37c108fcc1004840b82be18fd23c340a68ca748
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66756
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-08-21 14:55:59 +00:00
V Sowmya 248708533b Revert "mb/intel/adlrvp: Set EPP to 45% for all Adl RVP variants"
This reverts commit 2b19d547c0.

A power and performance analysis performed on Alder Lake demonstrated
that with an EPP (Energy Performance Preference) at 50% along with
EET (Energy Efficient Turbo) disabled, the overall SoC performance are
similar or better and the SoC uses less power.

For instance some browser benchmark results improved by 2% and some
multi-core tests by 4% while at the same time power consumption
lowered by approximately 7.6%.

BUG=b:240669428
TEST=verify that EPP is back to the by default 50% setting
     `iotools rdmsr 0 0x774'

Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I76d3914e51c5320af4c202558e1e7c57b7c0de54
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Baieswara Reddy Sagili <baieswara.reddy.sagili@intel.com>
Reviewed-by: Saurabh Mishra <mishra.saurabh@intel.com>
Reviewed-by: Usha P <usha.p@intel.com>
2022-08-21 14:54:38 +00:00
Raihow Shi 6eda41743e mb/google/brask/variants/moli: Support DPTF oem_variables
Enable DPTF oem_variables and override based on CPU match id.

BUG=b:236294162
TEST=emerge-brask coreboot and check the value in odvp0 is correct.

Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: Ic935ec42f4de0cbec996da37b44f354978fe4b62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66907
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-21 14:53:22 +00:00
Leo Chou 50b45d35f0 mb/google/nissa/var/pujjo: Add FW_CONFIG probe for Pujjoteen disable
bypass power

Add FW_CONFIG probe to separate ext fivr settings for Pujjoteen
and others(Pujjo and Pujjoflex)

BUG=b:242663554
TEST=Boot to OS and verify that ext_fivr_settings are set based on
fw_config.

Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: I6bb6d1701c55459cf331dd2f3ffe07f91bca2fa5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-08-21 14:52:22 +00:00
Tony Huang d6bf000a0e mb/google/dedede/var/shotzo: Enable ILITEK touchscreen
The current reset delay is not enough to make touchscreen IC ready,
ILITEK feedback their requiremt is 400ms in spec T2.
After changing the reset_delay_ms and check touchscreen works,
ILITE also change the IRO to low level trigger.
This CL is to reflect that.

BUG=b:235929123
BRANCH=firmware-dedede-13606.B
TEST=check touchscreen function work

Change-Id: I126b2d74c1d7a1799e2f67a8ab01cba074447c06
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-08-21 14:51:08 +00:00
Wisley Chen 0225591a2e mb/google/nissa/var/yaviks: Update GPIO setting
Configure GPIOs according to schematics.

BUG=b:242277219
TEST=emerge-nissa coreboot

Change-Id: Id7412059ba98d58f7014ab7201ea8958ede5905e
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-08-21 14:49:58 +00:00
Wisley Chen 77963b9d81 mb/google/nissa/var/yaviks: Update devicetree setting
Update Devicetree according to yaviks's design.

BUG=b:242277219
TEST=emerge-nissa coreboot

Change-Id: I5d91cccbb44787bcbe7258a817ff97b6dce86c2e
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-08-21 14:48:10 +00:00
Nico Huber bbd07043ff intel/systemagent: Align debug output
Output should be easier to read as a table.

Change-Id: I32e3e0aab5afd25c0b004d18f64de76445d9a0ed
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-08-21 14:46:54 +00:00
Sean Rhodes f06ec60b48 mb/starlabs/*: Disable INTEL_LPSS_UART_FOR_CONSOLE
Disable INTEL_LPSS_UART_FOR_CONSOLE to stop debug output on UART 2.

This decreases boot time on all boards by around 60%.

TGL before:
    Total Time: 10,110,807

TGL after:
    Total Time: 3,851,641

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I8f8d5cd46e87e7dafe0669b4a29c872b1789eb60
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-08-21 14:46:22 +00:00
Sean Rhodes cee3abdbaf mb/starlabs/starbook/kbl: Update verb table
The ALC269 does not support the hardware equaliser, so remove the
entries related to this, as they have no effect.

Revert to the ALC269 defaults which work correctly with Linux. This
also corrects the subsystem id from 0x10ec111e to 0x10ec10d0.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I82647f67730ec344591f7dbd759a421c116d4fdd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-08-21 14:45:04 +00:00
Amanda Huang 6cc6f42673 mb/google/skyrim: Add ELAN touchscreen
Add ELAN touch support

BUG=b:243120074
TEST=emerge coreboot and check ELAN touch screen is workable

Change-Id: If30232b3da9af0015d6d87535b53f905c5a30bcb
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66912
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Isaac Lee <isaaclee@google.com>
2022-08-20 20:44:15 +00:00
Felix Held 2badaa5b6a soc/amd/common/block/psp/psb: add missing amdblocks/smn.h include
smn_read32 is used in this file, so include the header file with the
function prototype so that the file compiles successfully.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5bef96cd08f22b3475e8b5ba4e984a6e1ab4da36
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66913
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2022-08-20 20:43:36 +00:00
Felix Held 02b61ae9c0 soc/amd/stoneyridge: move early I2C init to early_fch.c
Since the I2C controller is part of the FCH, move the early
initialization from bootblock.c to early_fch.c which also matches what
the newer AMD SoCs do.

TEST=Successfully boots on google/liara and all I2C/cr50/TPM functions
appear to work properly

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I22d3a8888eaa34ea612da719c408c0083769e806
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66866
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-20 20:43:17 +00:00
Felix Held f7d86f21e1 soc/amd/stoneyridge/early_fch: use common lpc_early_init function
The functionality of sb_enable_lpc is implemented in the common LPC
support code as lpc_enable_controller. This gets called by the common
lpc_early_init which also calls lpc_disable_decodes and lpc_set_spibase.
The lpc_set_spibase call was already done in bootblock_fch_early_init,
so the main change in code behavior is that now lpc_disable_decodes gets
called during early FCH initialization. The lpc_enable_port80 and
sb_lpc_decode calls after the lpc_early_init code will reenable some of
the decodes.

TEST=Successfully boots on google/liara, cbmem and dmesg logs look clean

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia58a6f609fa149a6c09ed99f08bdc4f05eb56f96
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66841
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-20 20:43:17 +00:00
Matt DeVillier e943e9fc24 soc/amd/common/dmi: Add missing newline in printk
Change-Id: I35dd9a2f0520077913bd3d8f408206dea1b30acb
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66867
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-20 04:33:35 +00:00