Commit Graph

42704 Commits

Author SHA1 Message Date
Mark Hsieh 72bdda2582 mb/google/brya: add generic LPDDR4 SPDs for Gimble
Add Makefile.inc to include three generic LPDDR4 SPDs for the following
parts for Gimble:

  DRAM Part Name                 DRAM ID to assign
  MT53E512M32D2NP-046 WT:E       0 (0000)
  H9HCNNNCPMMLXR-NEE             1 (0001)
  H9HCNNNBKMMLXR-NEE             0 (0000)

BUG=b:191574298
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.

Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I60f95ac5ed7f3134882f6580335ec33632676796
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-06-25 03:14:55 +00:00
Mark Hsieh 62b9ed27ea mb/google/brya/variants/gimble: set up gpio
Set the GPIO configuration of gimble

BUG=b:191213263

Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I667943578a2bf58cc5841564b8df5b6469d7594b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55717
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-25 03:14:32 +00:00
Zanxi Chen 4dce0990f9 mb/google/trogdor: Add new vaviant mrbland
New boards introduced to trogdor family.

BUG=b:191800434
BRANCH=none
TEST=make

Change-Id: I93b74e79188bd0cc36c8b48e552230ae0d6f593a
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-06-24 21:06:20 +00:00
Arthur Heymans 890d4fbea6 arch/x86/bootblock.ld: Align the bottom of the bootblock to 64 bytes
Align the bootblock size to 64 bytes because:
- cachelines are often 64 bytes large
- Bootguard/CBnT requires a 64 byte alignment

Change-Id: I69cdacdd15bfca1b91b6f271f2ff76889969fd91
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55046
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-06-24 11:22:54 +00:00
Arthur Heymans 6da7fa26b0 soc/intel/cache_as_ram.S: Fix SOC_INTEL_APOLLOLAKE
Intel Apollolake does not support the bootguard MSRs 0x139 MSR_BC_PBEC
and 0x13A MSR_BOOT_GUARD_SACM_INFO.

Change-Id: Ief40028a1c85084e012a83db8080d478e407487b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-06-24 10:02:06 +00:00
Arthur Heymans cd96fed5dc soc/intel/cache_as_ram.S: Add macro to detect bootguard nem
Change-Id: I3867fce29d23b647fad9845b9a5c08bb949fa354
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55783
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-24 09:00:50 +00:00
Subrata Banik 0007fa96a1 soc/intel/alderlake: Update mainboard_memory_init_params() argument
This patch updates mainboard_memory_init_params() function argument from
FSPM_UPD to FSP_M_CONFIG. Ideally mainboard_memory_init_params()
function don't need to override anything other than FSP_M_CONFIG UPDs
hence passing config block alone rather passing entire FSP-M UPD
structure.

Change-Id: I238870478a1427918abf888d71ba9c9fa80d3427
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-24 07:55:12 +00:00
Subrata Banik b03cadf84b soc/intel/alderlake: Refactor soc_silicon_init_params function
This patch create separate helper functions to fill-in required
FSP-S UPDs as per IP initialization categories.

This would help to increase the code readability and in future
meaningful addition of FSP-S UPDs is possible rather adding UPDs randomly.

TEST=FSP-S UPD dump shows no change without and with this code change.

Change-Id: Iba51aebc74456449e24e51e2f309f14f951464a0
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55233
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-24 07:54:46 +00:00
Subrata Banik c0983c9e9b soc/intel/alderlake: Rename FSP_S_CONFIG variable from params to s_cfg
Align FSP-S UPD structure (FSP_S_CONFIG) variable name (s_cfg) as FSP-M
UPD structure variable (m_cfg).

TEST=Able to build and boot ADLRVP to ChromeOS. FSP-S UPD dump shows
no change in UPD values with this CL.

Change-Id: I795f733f5f0cc64d3a556a1cd401323b35ba5a23
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-24 07:54:23 +00:00
Subrata Banik 6f1cb40ee6 soc/intel/alderlake: Refactor platform_fsp_silicon_init_params_cb function
Align platform_fsp_silicon_init_params_cb() function implementation
with romstage/fsp_params.c file platform_fsp_memory_init_params_cb() as:
|- Override FSP-S Arch UPD(s) using arch_silicon_init_params().
|- Override FSP-S SoC UPDs using soc_silicon_init_params().
|- Override FSP-S Mainboard UPDs using mainboard_silicon_init_params().

TEST=FSP-S UPD dump shows no change without and with this code change.

Change-Id: I4cf0b8423fb4038a7feddd97ff585027b3012605
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-24 07:53:47 +00:00
Kangheui Won a8b419b37b mb/google/guybrush: configure eSPI mux on psp_verstage
Temporarily set eSPI mux in verstage_mainboard_early_init.
Ideally cezanne code should have common function to do this and
mb-specific code would just call it, but for now PCI access doesn't work
in the PSP so we can't do it.

AMD team confirmed that the current PSP doesn't configure LPC so we
don't have to disable LPC when configuring eSPI mux so we can
temporarliy skip the LPC part here.

BUG=b:183149183
TEST=boot guybrush with psp_verstage

Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I8317409fa5efd1adffc184d75affbb4d305183f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-06-24 04:16:47 +00:00
Ryan Chuang 2ecb0ed266 vc/mediatek/mt8195: Allow adjusting DRAM voltage in DRAM calibration
To support DRAM HQA HV/LV test, add an interface for adjusting the DRAM
voltage in DRAM fast calibration flow.
Normal boot flow will not be affected.

Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: I4dbb4cb546e6e60693743ffe26b0df28ea501618
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55752
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-24 03:15:21 +00:00
Rex-BC Chen 506b4c9093 mb/google/cherry: Implement regulator interface
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Iab58edd019ccf9130e96fae55f147ab20cd0f45b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55751
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-24 03:15:00 +00:00
Ryan Chuang da63f09b80 mb/google/cherry: Initialize DPM in romstage
Add initialization of DPM drvier used by DRAM calibration test.

Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: I8bd10864267dfa4db8528d40483eccee2d05c1d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-06-24 03:14:28 +00:00
Ryan Chuang d5b0000856 mb/google/cherry: Add mt6360 driver for PMIC access
Add initialization of mt6360 drvier used by DRAM calibration test.

Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: Id74835d8395afac9e7e2c987a0a033f1b524fbfb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-06-24 03:14:05 +00:00
Ryan Chuang a9be096fa7 soc/mediatek/mt8195: Support 4 channel DRAM in DPM init flow
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: If2e9d8a4dcfad28c48a2b5fa7c92f70fae879e67
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-06-24 03:13:53 +00:00
Karthikeyan Ramasubramanian 6ce71e3bb1 mb/google/guybrush: Indicate the presence of ACP DMIC
In order to enable ACP DMIC hardware runtime detection, indicate that
ACP DMIC is present.

BUG=b:182960979
TEST=Build and boot to OS in guybrush. Ensure that the _WOV ACPI method
is populated in the ACP device.

Change-Id: I9a53d158ed08a6b46c29bcb8fe3a2a0d108bd6cd
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55030
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-23 19:19:33 +00:00
Karthikeyan Ramasubramanian 4ce48b3a37 soc/amd/common/acp: Populate _WOV ACPI method
In order to support Audio Co-processor (ACP) DMIC hardware runtime
detection on the platform, ACPI _WOV method is populated on the
concerned ACP device. This method returns the ACPI Integer value as 1
if ACP DMIC exists on the platform.

BUG=b:182960979
TEST=Build and boot to OS in guybrush. Ensure that the _WOV ACPI method
is populated under the scope of ACP device.
    Scope (\_SB.PCI0.GP41.ACPD)
    {
        Method (_WOV, 0, NotSerialized)
        {
            Return (One)
        }
    }

Change-Id: Ide84f45f5ea2ae42d5efe71ac6d1595886157045
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55029
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-23 19:19:19 +00:00
Martin Roth 6662fe60e1 soc/amd/cezanne: Init eSPI early if required
If the NO_EARLY_BOOTBLOCK_POSTCODES config option is enabled, configure
eSPI as early as possible in the x86 boot sequence.

We found that there are situations that can cause the system to hang if
there are any port80h postcodes sent out before eSPI is initialized.

BUG=b:191370340
TEST=Build & Boot with and without NO_EARLY_BOOTBLOCK_POSTCODES enabled.

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I0badb1c529e96ee4f81134287db53ce32473de6e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55732
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-23 19:01:16 +00:00
Martin Roth 7c21c20821 mb/google/guybrush: Add guybrush specific AMDFW config file
This takes the "generic" AMD firmware config file from the cezanne
directory and removes pieces unnecessary for guybrush.

Removed:
- PSPTRUSTLETS_FILE         TypeId0x0C_FtpmDrv_CZN.csbin
- PSP_MP2FW0_FILE           TypeId0x25_Mp2Fw_CZN.sbin
- PSP_KVM_ENGINE_DUMMY_FILE TypeId0x29_KvmEngineDummy.csbin
- DRTMTA_FILE               TypeId0x47_DrtmTA_CZN.sbin
- PSP_MP2CFG_FILE           MP2FWConfig.sbin

BUG=b:187103438
TEST=Build & Boot

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I5a0ed1edd7616a890f906b7f3e4a7d364758ca47
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-23 19:00:17 +00:00
David Wu 7abdb6560a mb/google/dedede/var/magolor: Enable weida touchscreen for magister
Add weida touchscreen support for magister.

BUG=b:191633024
BRANCH=dedede
TEST=Build and verify that touchscreen works on magister.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I3de6a84d2d58ef87f0ae13e8a117a980a0210ac4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Randy Lai <randy.lai@weida.corp-partner.google.com>
2021-06-23 18:26:14 +00:00
Felix Held 8c3a8df102 soc/amd/common/block/cpu/noncar/memmap: move BERT region back into CBMEM
The original reason the BERT table was moved out of CBMEM was because
the OS was not able to access the region. This happened because the
CBMEM region was marked as type 16 in the e820 table. The OS isn't aware
of this type, so it prevents any drivers from accessing it. Depthcharge
now correctly labels the CBMEM region as reserved in the e820 table so
we can move the BERT table into CBMEM.

TEST=BERT ACPI table generation still works on AMD/Mandolin with SeaBIOS
as payload and BERT region inside CBMEM is inside a BIOS-e820 reserved
range. BERT generation also works on Zork with depthcharge.

Link: https://crrev.com/c/2939677
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie640e91c19ae5f9b275cc333284b4be34211fbf6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55279
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-06-23 14:36:19 +00:00
Zhi Li 3694cc737a mb/google/dedede/var/sasukette: Change ELAN touchpad driver
Use drivers/i2c/hid can't update firmware by kernel update script,
so change to drivers/i2c/generic.

BUG=b:188602529
BRANCH=dedede
TEST=can update ELAN touchpad firmware(277.0_1.0) by kernel script

Change-Id: I3592403fe5d0f8d0f67059f8296277e3c028c117
Signed-off-by: Zhi Li <lizhi7@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55248
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-23 14:35:39 +00:00
Arthur Heymans ab090a11ee mb/{fb/fbg1701,portwell/m107}: Don't select HAVE_FSP_BIN
This selected by default if 3rdparty/fsp is used. There is no need to
override this behavior in the mainboard Kconfig.

Change-Id: I01ee2e90e0eceaa3100d911b5460cf99f413b185
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2021-06-23 14:35:27 +00:00
Frans Hendriks 6cd4cfa30d mb/facebook/fbg1701/Kconfig: Correct dependency
Config items depends on USE_VENDORCODE_ELTAN but are VBOOT specific.

Correct dependency of these items on VENDORCODE_ELTAN_VBOOT.

BUG = NA
TEST = Boot facebook FBG-1701 with possible combinations of Eltan
security.

Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Change-Id: Icd1c3e5c70ca562190308752f45aac734826649a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52132
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-23 14:35:08 +00:00
Kyösti Mälkki 6c7e945ab2 soc/intel/common: Fix X2APIC NMI entry in ACPI MADT
For X2APIC mode, replicate the APIC NMI entry flags and
intention to address all the logical processors.

Change-Id: I9c0537a3efba942329f80d7cfdbd910b8958516f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55182
Reviewed-by: Lance Zhao
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-23 10:14:17 +00:00
Subrata Banik 93632a9f1f mb/intel/sm: Skip FSP to program UART0
Set "SerialIoUartMode" for UART0 as PchSerialIoSkipInit

Change-Id: Idc7da7bf38634c04b0f4acd4c7c2ea9fa88545e5
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55207
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-23 09:08:50 +00:00
Subrata Banik 194f0eb59c soc/intel/elkhartlake: Use is_devfn_enabled() for Device4Enable UPD
1. Replace pcidev_path_on_root() and is_dev_enabled() functions
combination with is_devfn_enabled() while enabling Thermal config.
2. Remove unused local variable of device structure type (struct device *).

Change-Id: Icc2a44d6d3f1a78bf47354049dd9e2a0ed2282ba
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55728
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-23 08:26:37 +00:00
Subrata Banik e633804375 soc/intel/alderlake: Use devfn_disable() function for XDCI
Use devfn_disable() for disabling a PCI device rather than
using `dev->enabled = 0`.

Also, use is_devfn_enabled() to get the device current state prior
updating the FSP-S UPD for XDCI.

TEST=FSP-S disabled XDCI when `xdci_can_enable` returns 0 and XDCI
is disabled at PCI enumeration `PCI: 00:14.1: enabled 0`.

Change-Id: I5e10e5d0b80986e1e73573a86a957985840fe0b3
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55727
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-23 08:26:27 +00:00
Subrata Banik 3b374bebac soc/intel/cannonlake: Use devfn_disable() function for XDCI
Use devfn_disable() for disabling a PCI device rather than
using `dev->enabled = 0`.

Also, use is_devfn_enabled() to get the device current state prior
updating the FSP-S UPD for XDCI.

TEST=FSP-S disabled XDCI when `xdci_can_enable` returns 0 and XDCI
is disabled at PCI enumeration `PCI: 00:14.1: enabled 0`.

Change-Id: I64ab77bc49d93aca1da0126d849e69ff75b182a3
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55726
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-23 08:26:17 +00:00
Subrata Banik 5dea316250 soc/intel/elkhartlake: Use devfn_disable() function for XDCI
Use devfn_disable() for disabling a PCI device rather than
using `dev->enabled = 0`.

Also, use is_devfn_enabled() to get the device current state prior
updating the FSP-S UPD for XDCI.

TEST=FSP-S disabled XDCI when `xdci_can_enable` returns 0 and XDCI
is disabled at PCI enumeration `PCI: 00:14.1: enabled 0`.

Change-Id: I8ca0813e18da0f95eb9293b6d0bbdf933a1e7039
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55725
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-23 08:26:05 +00:00
Subrata Banik 1369544b3f soc/intel/icelake: Use devfn_disable() function for XDCI
Use devfn_disable() for disabling a PCI device rather than
using `dev->enabled = 0`.

Also, use is_devfn_enabled() to get the device current state prior
updating the FSP-S UPD for XDCI.

TEST=FSP-S disabled XDCI when `xdci_can_enable` returns 0 and XDCI
is disabled at PCI enumeration `PCI: 00:14.1: enabled 0`.

Change-Id: I568cd39792eba1bbace4901e96d708d80f73c60a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55724
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-23 08:25:56 +00:00
Subrata Banik 7bfee2d70f soc/intel/jasperlake: Use devfn_disable() function for XDCI
Use devfn_disable() for disabling a PCI device rather than
using `dev->enabled = 0`.

Also, use is_devfn_enabled() to get the device current state prior
updating the FSP-S UPD for XDCI.

TEST=FSP-S disabled XDCI when `xdci_can_enable` returns 0 and XDCI
is disabled at PCI enumeration `PCI: 00:14.1: enabled 0`.

Change-Id: I038e43deead70d598cf26f320dd9993f17591b88
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55723
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-23 08:25:45 +00:00
Subrata Banik c3a5c0558d soc/intel/tigerlake: Use devfn_disable() function for XDCI
Use devfn_disable() for disabling a PCI device rather than
using `dev->enabled = 0`.

Also, use is_devfn_enabled() to get the device current state prior
updating the FSP-S UPD for XDCI.

TEST=FSP-S disabled XDCI when `xdci_can_enable` returns 0 and XDCI
is disabled at PCI enumeration `PCI: 00:14.1: enabled 0`.

Change-Id: I0e400ded7ba268a5f289b0ac568598e0dad1899a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55722
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-23 08:25:37 +00:00
Subrata Banik 1a5d4120e6 soc/intel/icelake: Make use of is_devfn_enabled() function
1. Replace all pcidev_path_on_root() and is_dev_enabled() functions
combination with is_devfn_enabled().
2. Remove unused local variable of device structure type
(struct device *).
3. Replace pcidev_path_on_root() and dev->enabled check with
is_devfn_enabled() call.
4. Leave SATA, eMMC controller FSP UPDs at default state if
controller is not enabled and FSP UPDs are set to disable.

TEST=Able to build and boot without any regression seen on ICLRVP.

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: Id6861af3b5d1ce4f44b6d2109301bd4f5857f324
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-23 08:25:11 +00:00
Ryan Chuang d41a5ae489 soc/mediatek/common: Add DPM_FOUR_CHANNEL option
Add DPM_FOUR_CHANNEL option for 4 channel configuration for DPM.
Publicize reset_dpm() as dpm_reset() for external reference.

Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: If6e0d5c4d16a7ddd69c4a427488f8899870db327
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-06-23 05:50:37 +00:00
Ryan Chuang aff42bc6a4 soc/mediatek/mt8195: Add DPM firmware files
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: I51e8ebf5a75ac629bed51665e12bafa740b4b81d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-06-23 05:50:25 +00:00
Andrew SH Cheng 0865b4fc09 soc/mediatek/mt8195: Add mt6360 driver for PMIC access
Signed-off-by: Andrew SH Cheng <andrew-sh.cheng@mediatek.com>
Change-Id: Ieaf234f35f2b7d440bdf1e6ec4c455af7b311623
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55710
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-23 05:50:12 +00:00
Martin Roth 0a5837e9f1 soc/amd/common: Add GPIO config for native func w/ output drive
Our existing native function gpio configuration macro (PAD_NF) only sets
the pull.  For PCIe reset, we now need to be able to set it to its
native function (PCIE_RST_L), and drive it low, then high.

BUG=b:182805349
TEST=Configure GPIO, see correct behavior.

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I636371517c99f94f76834abc4575795d51aa0368
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55652
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-22 21:30:05 +00:00
Martin Roth 1687c243f5 mb/google/guybrush: Only enable early port80s if using psp_verstage
PSP_Verstage will enable eSPI early in the boot sequence.  If the
platform isn't using psp_verstage, the system can hang on the first
port 80h postcode that comes out because they aren't routed to an
active device until eSPI is configured.

BUG=b:191370340
TEST=Build without PSP_Verstage, verify system doesn't hang.

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I37fbb251cd79609b856c4480ca29ce94b08897d7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55738
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-22 21:20:40 +00:00
Tim Wawrzynczak f2801f455c soc/intel/common: Unbreak master
Commit 54b03569c moved a call to cse_trigger_recovery () around, and
commit 09635f418 renamed the function, but was tested before the first
commit was submitted, thus breaking the tree. Fix it.

Change-Id: If21ea0c1ebf9ce85c59ee25ec7f879abde2e3259
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55766
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-22 18:11:26 +00:00
Tim Wawrzynczak 09635f418b soc/intel/common/block/cse: Move cse_trigger_recovery function
This function could be applicable in situations other than just for the
CSE Lite SKU, therefore move this from cse_lite.c to cse.c

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ibc541f2e30ef06856da10f1f1219930dff493afa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55673
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-22 16:51:52 +00:00
Meera Ravindranath f100e204ec mb/intel/adlrvp: Update Mainboard part number and Vendor
dmidecode output should match with the CrOS kernel updated string.

TEST=dmidecode grep "Manufacturer" = Intel Corporation
     dmidecode grep "Product name" = Alder Lake Client Platform

Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I7cce423de624e7056e88b52a1443c554fd9123bc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51408
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-22 13:28:21 +00:00
Malik_Hsu cc7538475e mb/google/brya/variants/primus: set up gpio
Set the GPIO configuration of primus

BUG=b:190643562

Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com>
Change-Id: I405561ae8a44d95ffdc526241f9c52761f67ed35
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-22 13:23:44 +00:00
Arthur Heymans 5e8c906cab soc/intel/{apl,cnl}: Remove FSP CAR option
One of the reason FSP-T support had to be kept in place was for
Intel Bootguard. This now works with native CAR code, so there is no
reason to keep FSP-T as an option for these platforms.

APL did not even build with FSP_CAR and finding FSP-T using walkcbfs
was only recently fixed using FMAP, so there can be no doubt that this
option was never used with coreboot master.

Change-Id: I0d5844b5a6fd291a13e5f467f4fc682b17eafa63
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-22 13:15:39 +00:00
Arthur Heymans 481c52ddd5 soc/intel/car: Add support for bootguard CAR
Bootguard sets up CAR/NEM on its own so the only thing needed is to
find free MTRRs for our own CAR region and clear that area to fill in
cache lines.

TESTED on prodrive/hermes with bootguard enabled.

Change-Id: Ifac5267f8f4b820a61519fb4a497e2ce7075cc40
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-06-22 13:15:09 +00:00
Arthur Heymans 99a48bc824 soc/intel/common/cache_as_ram.S: Add macro to clear CAR
Add a macro to clear CAR which is replicated 3 times in this code.

TEST: with BUILD_TIMELESS=1 the resulting binary is identical.

Change-Id: Iec28e3f393c4fe222bfb0d5358f815691ec199ae
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-06-22 13:14:53 +00:00
Arthur Heymans 64c9c6d54c soc/intel/common/cache_as_ram.S: Add macro to find a free MTRR
This adds a macro to find an available MTRR(s) to set up CAR.
This added complexity is not required on bootpaths without bootguard
but with bootguard MTRR's have already been set up by the ACM so
we need to figure out at runtime which ones are available.

Change-Id: I7d5442c75464cfb2b3611c63a472c8ee521c014d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-06-22 13:01:52 +00:00
Alice Sell cebf1e8c46 mb/asus/p8h61-m_pro_cm6630: Add initial support
This motherboard is somewhat similar to the p8h61-m_pro, but also different.
It has two exposed RAM slots with a pinout for four, and it's an OEM
variant used in PCs ASUS sold in stores.

Signed-off-by: Hunter Sell <alicelyralain@gmail.com>
Change-Id: Id08349feb0aeaf21406f814f6d19bbe0d9312a4d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-22 05:08:49 +00:00
Angel Pons 6adbfa79aa nb/intel/haswell/pcie.c: Avoid needless death
Using `config_of(dev)` to access `dev->chip_info` will make coreboot die
if the latter is NULL, which is the case for devices detected at runtime
(i.e. not statically declared in the devicetree). Given that the code is
designed to work when the PEG config is all-zeroes (devicetree default),
dying because `dev->chip_info` is NULL is foolish and unwarranted.

Introduce a helper function that returns a pointer to devicetree config
when available, and otherwise returns a pointer to a zero-filled static
struct. In addition, avoid an out-of-bounds access in the very unlikely
case where the device's function is too large.

Tested on Asrock B85M Pro4, can now boot when `device pci 01.0 on end`
is commented out in its devicetree. Without this commit, it could not.

Change-Id: Ia2d3a03da9eab601fb834b0c51a8a51c9ae14c33
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-06-22 04:47:20 +00:00