Commit Graph

32016 Commits

Author SHA1 Message Date
Dtrain Hsu d14673f0b1 hatch: Create stryke variant
(Auto-Generated by create_coreboot_variant.sh version 1.0.0).

BUG=b:145101696
TEST=util/abuild/abuild -p none -t google/hatch -x -a
make sure the build includes GOOGLE_STRYKE

Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Iea6f8a1c6c24a1e3545c364551cb623debdc4a1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-12-03 11:31:49 +00:00
Elyes HAOUAS 70a03dd960 src: Add missing include <stdlib.h>
Change-Id: I17dc2fed6c6518daf5af286788c98c049088911e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-12-03 11:30:52 +00:00
Subrata Banik 54daaecacb mb/google/drallion: Disable GPIO dynamic PM configuration
BUG=b:144002424
TEST=Ensured no TPM time out issue and system can boot to OS

Change-Id: I7282e6c2d9627846039638bdc0db3ee7ebba5f12
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-12-03 11:26:49 +00:00
Subrata Banik 73b1bd7992 soc/intel/cannonlake: Configure GPIO PM configuration in bootblock
This patch performs below operations:
1. Rename soc_fill_gpio_pm_configuration to soc_gpio_pm_configuration
2. Move soc_gpio_pm_configuration() to gpio_common.c
3. Calling from bootblock and after FSP-S to ensure GPIO PM configuration
is updated with devicetree.cb value even with platform reset.

BUG=b:144002424
TEST=coreboot configures all MISCCFG.bit 0-5 local clock gating based on devicetree.cb

Change-Id: I54061d556d62462d9012bc47bb9f3604a3e5a250
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-12-03 11:26:41 +00:00
Marshall Dawson 91e7fe7b54 soc/amd/stoneyridge: Use USE_AMD_BLOBS to remove default paths
Remove default path/to/file strings when USE_AMD_BLOBS is not enabled.
This will result in a buildable, but not runable image, in the default
configuration.

Drop the check for HAVE_MERLINFALCON_BINARIES in the path default.
A later patch will address the poor use of this symbol

All PSP blobs are still assumed to be in the same directory as the AMD
public key.  Qualify building the amdfw.rom intermediate image and
including it into coreboot.rom on whether the public key remains "".
This change infers it's OK to skip xHCI and GEC firmware too, although
the images normally reside in a separate directory.

This change only determines whether default paths and names exist.
Paths will be updated in a follow-on patch.

Change-Id: Ic21fbd7a58b340a9bcaaea456e1f38b567215b81
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37220
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-03 11:26:17 +00:00
Patrick Georgi a37eef131a soc/nvidia/tegra: Constify variable
Change-Id: Iab0a442e6dbde0f9abdf2d8689f9891b79a2d37a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-12-03 11:24:51 +00:00
Patrick Georgi 08c8cf9586 soc/intel/common/cse: Update comment for post-CAR global world
Change-Id: I4ec9d7d3af1c4d7713ec5dfe516b24d110303ff1
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-12-03 11:24:49 +00:00
Kyösti Mälkki 5cdbce8072 AGESA boards: Drop commented out code
Change-Id: I9db1147c5e112e5e6832eeece2214fece8aa6b83
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-12-03 03:45:46 +00:00
Kyösti Mälkki f824378526 AGESA,binaryPI: Remove unused s3_load/save_nvram
This is access to BIOSRAM region in ACPIMMIO. While we use the
region, we do not use these functions.

Change-Id: I39d1ae811cfe23595587ae0fe51c6549ecbaba6c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-12-03 03:45:23 +00:00
Mathew King c487ac1a9f mb/g/drallion: Enable privacy screen on Drallion variant
Enable ACPI methods to control privacy screen on Drallion devices.
Drallion devices may not have a privacy screen and it is up to the
EC to determine if the privacy screen is present on the system.

BUG=b:142656363
TEST=emerge-drallion coreboot chromeos-bootimage

Change-Id: I79d02bb1b25f0deb49ae4bb852b7ed8c21fd31c7
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36045
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-02 23:28:16 +00:00
Mathew King c650e130ce ec/google/wilco: Add EC ACPI methods for privacy screen
Add ACPI methods to the Wilco EC for controlling a privacy screen
on the device.

BUG=b:142237145, b:142656363
TEST=none

Change-Id: Ic3c136f9d2de90eeb3c9e468e4c7430ccf6dcc42
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36044
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-02 23:28:03 +00:00
Mathew King 6f8f34f1bf soc/intel/cannonlake: Add gfx.asl file
Add gfx.asl file for cannonlake SOCs to allow for graphics-related ACPI
devices and methods on cannonlake devices.

BUG=b:142237145
TEST=gfx.asl added to drallion dsdt.asl

Change-Id: I38a26f3135d571e2f9b63840d38fd4d3476fc142
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-12-02 23:24:08 +00:00
Mathew King f9fa985242 soc/intel: Intel graphics driver scans generic bus
This change allows for Intel graphics devices to use drivers/generic/gfx
driver to populate ACPI SSDT table for common graphics related devices
and methods.

BUG=b:142237145
TEST=On sarien_cml add generic/gfx to the devicetree and device is
     enumerated and correct SSDT ASL is observed.

Change-Id: Ibc86a88687ac860ebef19a4b68af64fd50d12b8e
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-12-02 23:23:52 +00:00
Mathew King c135b829e7 drivers/gfx: Add generic graphics with SSDT generator
Adds a generic graphics driver that can be added to a devicetree which
populates graphics-related ACPI table. It will write the _DOD method
(Enumerate All Devices Attached to the Display Adapter) and a device
object for each device defined. The device may optionally have a
connected privacy screen which can be controlled with a _DSM.

Example:
chip drivers/generic/gfx
  register "device_count" = "1"
  register "device[0].name" = ""LCD""
  register "device[0].addr" = "0x0400"
  register "device[0].privacy.enabled" = "1"
  register "device[0].privacy.detect_function" = ""\\_SB.PCI0.PVSC.GPVD""
  register "device[0].privacy.status_function" = ""\\_SB.PCI0.PVSC.GPVX""
  register "device[0].privacy.enable_function" = ""\\_SB.PCI0.PVSC.EPVX""
  register "device[0].privacy.disable_function" = ""\\_SB.PCI0.PVSC.DPVX""
  device generic 0 on end
end

ASL
Scope (\_SB.PCI0.GFX0)
{
    Method (_DOD, 0, NotSerialized)  // _DOD: Display Output Devices
    {
        Return (Package (0x01)
        {
            0x00000400
        })
    }

    Device (LCD)
    {
        Name (_ADR, 0x0400)  // _ADR: Address
        Name (_STA, 0x0F)  // _STA: Status
        Method (_DSM, 4, Serialized)  // _DSM: Device-Specific Method
        {
            ToBuffer (Arg0, Local0)
            If ((Local0 == ToUUID ("c7033113-8720-4ceb-9090-9d52b3e52d73")))
            {
                ToInteger (Arg2, Local1)
                If ((Local1 == Zero))
                {
                    Local2 = \_SB.PCI0.PVSC.GPVD ()
                    If ((Local2 == One))
                    {
                        Return (Buffer (One)
                        {
                                0x0F
                        })
                    }
                }

                If ((Local1 == One))
                {
                    ToBuffer (\_SB.PCI0.PVSC.GPVX (), Local2)
                    Return (Local2)
                }

                If ((Local1 == 0x02))
                {
                    \_SB.PCI0.PVSC.EPVX ()
                }

                If ((Local1 == 0x03))
                {
                    \_SB.PCI0.PVSC.DPVX ()
                }

                Return (Buffer (One)
                {
                        0x00
                })
            }

            Return (Buffer (One)
            {
                    0x00
            })
        }
    }
}

BUG=b:142237145
TEST=Added gfx to devicetree on sarien_cml and correct ASL in SSDT

Change-Id: Ida520dd7aad81ee7c1e5f2d0d3f5cc1a766d78a0
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36041
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-02 23:23:38 +00:00
Elyes HAOUAS 68ec3eb1f0 src: Move 'static' to the beginning of declaration
Change-Id: I9b2cc1bb58922d9e32202ea4c20b9aacfe308bad
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-12-02 15:56:40 +00:00
Aamir Bohra b9aaa33722 mb/intel/icelake_rvp: Remove unused mainboard ACPI write table
Change-Id: I19040cca064c2ce063aab77391e0577271c6e9dc
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37354
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2019-12-02 13:01:57 +00:00
Yu-Ping Wu 63b9700b2c lib/coreboot_table: Add CBMEM_ID_VBOOT_WORKBUF pointer to coreboot table
Since struct vb2_shared_data already contains workbuf_size and
vboot_workbuf_size is never used in depthcharge, remove it from struct
sysinfo_t. In addition, remove lb_vboot_workbuf() and add
CBMEM_ID_VBOOT_WORKBUF pointer to coreboot table with
add_cbmem_pointers(). Parsing of coreboot table in libpayload is
modified accordingly.

BRANCH=none
BUG=chromium:1021452
TEST=emerge-nami coreboot libpayload depthcharge; Akali booted correctly

Change-Id: I890df3ff93fa44ed6d3f9ad05f9c6e49780a8ecb
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Joel Kitching <kitching@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-12-02 13:00:45 +00:00
Yu-Ping Wu a2962daf6f security/vboot: Remove struct vboot_working_data
After CB:36808, CB:36844 and CB:36845, all fields except buffer_offset
were removed from struct vboot_working_data. Since buffer_offset is used
to record the offset of the workbuf relative to the whole structure, it
is no longer needed.

This patch removes the structure, and renames vboot_get_working_data()
to vboot_get_workbuf().

BRANCH=none
BUG=chromium:1021452
TEST=emerge-nami coreboot

Change-Id: I304a5e4236f13b1aecd64b88ca5c8fbc1526e592
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Joel Kitching <kitching@google.com>
2019-12-02 13:00:36 +00:00
Michał Żygowski 2317b4f114 sb/amd/cimx: replace cimx_util with common ACPIMMIO AMD block
Drop the redundant cimx_util, remove the includes when appropriate and
replace the implementation with amdblocks/acpimmio where needed.

TEST=boot PC Engines apu1 and launch Debian with Linux kernel 4.14.50

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I66b1f82926372b6ebb570893b6eb73c7f2935b9d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-12-02 12:59:45 +00:00
Sakari Ailus 00517b687a mb/google/poppy: Remove useless ifs around voltage and GPIO direction configuration
The methods generally tested OP region settings and only changed them if
they were not in their desired values. Instead, assign them directly
without checking them.

BUG=chromium:959232

Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Tested-by: Jacopo Mondi <jacopo@jmondi.org>
Change-Id: I3ceca4bd51c4410c7020431f4fd682c4ca925110
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36746
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-02 12:59:12 +00:00
Sakari Ailus 68f0eb5269 mb/google/poppy: Remove redundant mutex
The mutex is only used in one method and that method is serialised. Remove
the mutex.

BUG=chromium:959232

Reported-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Tested-by: Jacopo Mondi <jacopo@jmondi.org>
Change-Id: Ic173d557f4b49cc9e860d13b782fc4940fd80869
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36745
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-02 12:59:01 +00:00
Sakari Ailus be0dfef30c mb/google/poppy: Rework OV13858 power on sequence
In particular:

- Set voltage before enabling regulators

- Enable regulators and the clock without any sleeping in between. There's
  no need to wait there.

- Sleep 1 ms in order to wait for regulator voltages settling before
  lifting xshutdown.

BUG=chromium:959232

Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Tested-by: Jacopo Mondi <jacopo@jmondi.org>
Change-Id: I0f8857ae369d5038f293a0e2c48c681df535ad86
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-12-02 12:58:42 +00:00
Sakari Ailus c0b9c8cbc0 mb/google/poppy: Rework OV5670 power on sequence
In particular:

- Enable regulators *after* configuring the voltage

- Allow 1 ms for the voltages to settle

- Enable clock after powering on regulators

- Remove extra delays between enabling things. The sensor requires 8192
  clock cycles after the reset is lifted before I²C access, so 1 ms is
  enough.

- Make the delay after lifting xshutdown 10 ms. This guarantees that
  streaming will only start once the sensor has had enough time to settle
  after lifting the reset.

BUG=chromium:959232

Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Tested-by: Jacopo Mondi <jacopo@jmondi.org>
Change-Id: I4589a7d7ec324f4520572a406cc11ad3feec8b21
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-12-02 12:58:28 +00:00
Sakari Ailus ecfb4b81ae mb/google/poppy: Power on PMIC before accessing its opregion
The PMIC opregion is used to change the direction of two GPIOs for I²C
daisy chain operation. Do this after the PMIC is powered on, not before.

BUG=chromium:959232

Reported-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Tested-by: Jacopo Mondi <jacopo@jmondi.org>
Change-Id: I923987ef21a971df9e32ca03f2da4dccdac07843
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-12-02 12:58:05 +00:00
Sakari Ailus 2d54fc9581 mb/google/poppy: Declare output GPIOs as pull-downs
The pull direction is used to determine the initial state of the pin. If
no pull direction is specified, the pin will remain as input. Fix this.

BUG=chromium:959232

Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Tested-by: Jacopo Mondi <jacopo@jmondi.org>
Change-Id: I1158bc8aaa447b223e8ce25d808348e758de28c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36721
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-02 12:57:49 +00:00
Kyösti Mälkki 1804b15896 soc/amd/common: Inline ACPI MMIO accessors
The overhead of pushing variables to stack exceeded the number
of instructions the actual MMIO operation took and the build of
google/aleena with inlined accessors turned out to be just
slightly (<2 KiB) smaller for the entire romstage or ramstage.
Simple read-modify-write MMIO cycles should optimise better now.

IO cycles with index/data register are borderline, at
first sight assembly looked better by not inlining them.

Change-Id: If2c37c9886a0151183aa6dd80eb068d6c67b3848
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-02 12:08:40 +00:00
Praveen Hodagatta Pranesh ab62d940fe configs: Jenkins buildtest for FSP_CAR
Change-Id: I004fc02bd84b7b8d5c5fb96451e59f143f0fe6d3
Signed-off-by: Praveen Hodagatta Pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-02 12:08:12 +00:00
Praveen Hodagatta Pranesh e58eafc45a soc/intel/cannonlake: Fix compilation
Change MicrocodeRegionLength to MicrocodeRegionSize as per
coffeelake FsptUpd.h.

TEST= Build with CONFIG_USE_CANNONLAKE_FSP_CAR selected and boot test on
      coffeelake RVP.

Change-Id: Iebbf5c34e289870a4d7abdd49fd81e4db236051a
Signed-off-by: Praveen Hodagatta Pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37265
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-02 12:08:04 +00:00
Kane Chen b7f30ad25f mb/google/hatch/variants/helios: DPTF solution update
Modify DPTF parameters.

BUG=b:131272830
BRANCH=firmware-hatch-12672.B
TEST=emerge-hatch coreboot chromeos-bootimage

Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I93930525edf4c5efb6b73bdfc8f16950754f7c9a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37272
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-02 12:07:17 +00:00
Maulik V Vaghela bd36ea9866 soc/intel/tigerlake: Change compilation based on TIGERLAKE_BASE
since we support JSL and TGL soc under tigerlake folder, we need to make
sure all soc related files get compiled based on
CONFIG_SOC_INTEL_TIGERLAKE_BASE and not only for Tigerlake.

We can control soc specific file compilation through Kconfig of
individual soc.

Change-Id: I1a663555d0bdf7588c4e12363375e7c90629f7d9
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2019-12-02 12:07:02 +00:00
Martin Roth 5736846581 superio/aspeed: Remove unused aspeed include path
Working on some other code, I noticed that superio/aspeed was added as
an include path even though I wasn't using it.  I investigated and found
that NOTHING is using it.  The files in the aspeed directory all
reference files in their own directory.

The supermicro x11-lga1151-series boards are the only ones using this
SIO.

TEST=util/abuild/abuild -t supermicro/x11-lga1151-series

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I377066451a50452c17c9bfaa0f815f69e039984e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-02 12:06:28 +00:00
Matt DeVillier 2d086e6971 mb/google/glados: restore device-specific VBTs
When migrating glados (and variants) to FSP 2.0, the older board-
specific VBTs were dropped in favor of the default FSP 2.0 VBT due to
compatibility issues. Now that libgfxinit is available and the default,
restore the board-specific VBTs so that external displays function
properly. Select MAINBOARD_NO_FSP_GOP for all variants except glados
since FSP/GOP init will not function properly with the older VBTs.

Test: build/boot chell and caroline variants w/libgfxinit, verify
external displays now work again.

Change-Id: If55a67e0d3d78e4acf80cee1733ad8e14b8847d4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-02 12:06:18 +00:00
Matt DeVillier d7e92e8958 mb/google/rammus: add libgfxinit support
Add libgfxinit support for rammus. Use panel init values from VBT.

Test: build/boot rammus with libgfxinit and Tianocore payload

Change-Id: I4775a36d83bd67a0064a162effaf96649e9c186d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-02 12:05:38 +00:00
Matt DeVillier 12507ce895 mb/google/poppy: add VBTs for remaining variants
Add VBT files for Atlas, Nocturne, Rammus, and Soraka variants.
Extracted from ChromeOS recovery images for the respective boards.
Select INTEL_GMA_HAVE_VBT for all variants except Poppy, since
it doesn't have a VBT (or a recovery image from which to extract one).

Change-Id: Icba2741e0b7309c22c027f956cd20cec78f34052
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-02 12:05:30 +00:00
Gaggery Tsai cc3e2a031a src/mb/intel/coffeelake_rvp: Rename COMETLAKE_RVP to COMETLAKE_RVPU
This patch renames COMETLAKE_RVP to COMETLAKE_RVPU to avoid confusion.

TEST=build an image with COMETLAKE_RVPU

Change-Id: I93d7b5cc0be475926bb92503b66797dc67e607f5
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36793
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-02 12:04:48 +00:00
Gaggery Tsai fdcc9ab317 src/soc/intel: Add Cometlake-S and CMP-H skus
This patch adds some sku support for CML-S CPU and CMP-H chips.
According to doc #605546:
CML-S (6+2) G0: A0650h
CML-S (6+2) G1: A0653h
CML-S (10+2, 8+2) P0: A0651h
CML-S (6+2, 10+2) Q0/P1: A0654h

CMP-H HM470: 068Dh
CMP-H WM490: 068Eh
CMP-H QM480: 068Ch
CMP-H H470: 0684h
CMP-H Z490: 0685h
CMP-H Q470: 0687h

TEST=Boot with CML-S (6+2) G1 + CMP-H WM490 and IDs are recognized

Change-Id: I6bda09070ec330033eff95329448ace57e87144f
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-02 12:04:38 +00:00
Patrick Georgi c9b13594eb src/: Remove g_ prefixes and _g suffixes from variables
These were often used to distinguish CAR_GLOBAL variables that weren't
directly usable. Since we're getting rid of this special case, also get
rid of the marker.

This change was created using coccinelle and the following script:
	@match@
	type T;
	identifier old =~ "^(g_.*|.*_g)$";
	@@
	old

	@script:python global_marker@
	old << match.old;
	new;
	@@
	new = old
	if old[0:2] == "g_":
	  new = new[2:]

	if new[-2:] == "_g":
	  new = new[:-2]

	coccinelle.new = new

	@@
	identifier match.old, global_marker.new;
	@@
	- old
	+ new

	@@
	type T;
	identifier match.old, global_marker.new;
	@@
	- T old;
	+ T new;

	@@
	type T;
	identifier match.old, global_marker.new;
	@@
	- T old
	+ T new
	 = ...;

There were some manual fixups: Some code still uses the global/local
variable naming scheme, so keep g_* there, and some variable names
weren't completely rewritten.

Change-Id: I4936ff9780a0d3ed9b8b539772bc48887f8d5eed
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-12-02 10:44:38 +00:00
Patrick Rudolph ae64f22e8d drivers/usb/ehci_debug: Add x86_64 support
Use proper int to pointer conversions.

Tested on Lenovo T410 with x86_64 enabled. Still works.

Change-Id: I4ed62297fb47d7d83d4b28e80f3770de99ce70f7
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37393
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-02 07:45:38 +00:00
Patrick Georgi a8582c4c02 lib/cbmem_console: Rename cbmem_console_p to current_console
That way, current_console_set() also isn't necessary anymore and
symmetry is re-established.

Change-Id: I392ed509f490d63b0c016a80fd7ab3ef98ba8019
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-12-01 23:09:34 +00:00
Elyes HAOUAS 92542469e2 src/superio: Remove unused include <stdlib.h>
Change-Id: I941c3d80d6b822b12a2d0c279415ab0c6b7f375b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-12-01 17:59:05 +00:00
Maxim Polyakov eef7c69d49 superio/nct5539d: include the missing acpi.h and ssdt.h
Change-Id: Idd80fae1c39f3c7c4bc66a42e9023fb7a727b024
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-12-01 17:57:56 +00:00
Arthur Heymans a854c9d787 nb/intel/x4x: Factor out hiding PCI devs in pure fn
This increases readability.

Also change the update expression. '--variable' does not make much
sense there.

Change-Id: I64db2460115f5fb35ca197b83440f8ee47470761
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-01 12:39:24 +00:00
Patrick Georgi cd666d992d lib/imd_cbmem: Remove indirection through cbmem_get_imd()
It always returns the same pointer so why not use the pointer directly?

Change-Id: Ib5a13edc7f3ab05c3baf9956ab67031507bdddc1
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37360
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-30 19:25:29 +00:00
Patrick Rudolph bc2204edd2 util/pgtblgen: Fix typo
Change-Id: I638eda3040c7225aa4a8b492c8dc78b0e2effba1
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37369
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-30 19:25:15 +00:00
Arthur Heymans 8601afb679 kill CAR_GLOBAL_MIGRATION leftovers
Change-Id: Ia3b2c10af63cd0cab42dc39f479cb69bc4df9124
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37055
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-30 16:12:04 +00:00
Arthur Heymans fdb8b13e64 arch/x86/car.ld: Drop CAR_GLOBAL region
Change-Id: Id66fd0528987fb3e464d400cf9ccac98752fb8f5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37327
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-30 16:11:42 +00:00
Arthur Heymans 1b8df77ac1 arch/*/*/early_variables.h: drop unused files
Kill off NO_GLOBAL_MIGRATION finally!

Change-Id: Ieb7d9f5590b3a7dd1fd5c0ce2e51337332434dbd
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37054
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-30 16:11:11 +00:00
Arthur Heymans 706251d913 arch/x86/cache.h: Use ENV_CACHE_AS_RAM macro
Change-Id: Ic7b088a04165bb24b9ebcebc1580a96ce0fdfcc8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-30 16:10:27 +00:00
Arthur Heymans 6ea3a13a17 drivers/spi/flashconsole.c: Drop CAR_GLOBAL_MIGRATION support
Change-Id: I81a610a6d119745f2fc637629b8ba7ade76503bc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-30 16:09:57 +00:00
Arthur Heymans c0a4e20887 lib/cbmem_console.c: Drop CAR_GLOBAL_MIGRATION support
Change-Id: I5c970a07c7114bff81f0048cac8eafaec35a2386
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37035
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-30 09:51:02 +00:00