DSDT revision is =1 for ACPI v1 and =2 for greater ACPI version.
This will cause the AML interpreter to use 32-bit integers and math
if the version is 1, and 64-bit if the version is >=2.
Current spec version is 2 for ACPI 6.2-a.
Change-Id: I77372882d5c77b7ed52dcdd88028403df6f6fa7f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29626
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GPP_D6 needs to be inverted to enter S0ix because FPMCU_INT_L is
active low. Keeps device awake otherwise.
BUG=b:119447525, b:115706071
BRANCH=Nami
TEST=Run powerd_dbus_suspend from kernel and make sure see DUT drop into
S0ix in the EC console.
Change-Id: Iad5df124e2439bbdc078d6a33f8d0510d25ecf6f
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/29650
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GPIO's that use GPI_APIC setting with DEEP causes an IRQ storm after
S3 resume. GPIOs that fire IRQs via IOAPIC need to get their logic
reset over PLTRST to prevent IRQ storm after S3 resume and hence
configuring GPP_F10 (HP_IRQ_GPIO) to use PLTRST.
BUG=none
TEST=none
Change-Id: Idc6c42cb4dc6e8eb368d605c83f584f4c69077dc
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/29540
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With this change, coreboot thinks we're running at 1MHz:
DW I2C bus 2 at 0xd1133000 (1000 KHz)
Elan eKT3644 IC Specification (trackpad) requires:
Low Time larger than 500ns (61 * 8.3ns = 506ns).
High Time larger than 260ns (32 * 8.3ns = 265ns),
Data Hold_time larger than 0ns.
Start Condition Hold time larger than 250ns.
Rise/Fall time of less than 120ns.
HCNT controls both High Time and Start Condition Hold time.
LCNT controls Low Time.
SDA_HOLD controls Data Hold Time.
P2 Atlas "Rise time" is 90ns and "Fall time" is 32ns and tuned
using resistors on the board and must be considered when
adjusting any of the parameters since these times are all measured
at 30 or 70% of base and peak voltages (0v/1.8v).
The eKT3644 requirements are met with LCNT=69, HCNT=33, SDA_HOLD=20
which yields the SCL at around 950KHz - suboptimal but compliant.
Lower LCNT or HCNT results in "lost arbitration" errors or not complying
with eKT3644 requirements.
Verified by gaggery.tsai@intel.corp-partner.google.com.
Scope shots posted here:
https://b.corp.google.com/issues/78601949#comment177
BUG=b:78601949
BRANCH=none
TEST=Farzam provided test points on track pad for SCL/SDA/GND.
Waveforms measured with oscilloscope and screen shots attached
to bug (comment #177, #155, #100).
Operate trackpad/touchscreen
Review dmesg (kernel) output for correct speed, parameters, and
no errors (e.g. "lost arbitration" or "host controller timeout")
Change-Id: Iaf42ba7b8818b7cd9c8dcc657823dac705659d38
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Signed-off-by: Grant Grundler <grundler@chromium.org>
Tested-by: gaggery.tsai@intel.corp-partner.google.com
Tested-by: grundler@chromium.org
Reviewed-on: https://review.coreboot.org/29553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Gaggery Tsai <gaggery.tsai@intel.com>
GPP_D0 is NC in 1st SKU board design, so we should control GPP_D0
for only 2nd SKU.
BUG=none
BRANCH=poppy
TEST=emerge-nautilus coreboot
Change-Id: Ifd85693c9155ed960f0c794d4b83fe8863b77134
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/29631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The GPP_E1 gpio was incorrectly being defined as a no-connect.
Configure GPP_E1 for the WLAN_WAKE_L signal as per the schematic.
BUG=b:119508897
TEST=Build and flash nocturne, boot nocturne and
1) Verify nocturne can successfully suspend/resume from S3 and S0ix.
2) Verify wake from wlan wakes device from S3 and S0ix.
To do so,
a) as root, execute "iw phy phy0 wowlan enable disconnect" on DUT
b) connect DUT to mobile hotspot
c) sleep device via "powerd_dbus_suspend"
d) turn off hotspot, verify DUT wakes from S0ix
e) enable hotspot again
f) connect DUT to hotspot
g) sleep DUT via "sudo echo mem > /sys/power/state"
h) turn off hotspot, verify DUT wakes from S3
Change-Id: I4efb4f6d601e172ae4807901e3bd4c9954319f80
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/29630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Rename EC_ENABLE_TABLET_EVENT config as EC_ENABLE_MULTIPLE_DPTF_PROFILES
since it aligns with the use-case.
BUG=b:118149364
BRANCH=None
TEST=Ensured that the expected DPTF table are loaded in different
modes (base attached/detached and clamshell/360-flipped) on Soraka and
Nautilus.
Change-Id: If147f1c79ceaaed00e17ec80ec6c912a8f7a8c2e
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/29261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
GPIO's that use GPI_APIC setting with DEEP causes an IRQ storm after
S3 resume. GPIOs that fire IRQs via IOAPIC need to get their logic
reset over PLTRST to prevent IRQ storm after S3 resume and hence
configuring GPP_D9 and GPP_D10 to use PLTRST.
BUG=b:119202293
TEST=none
Change-Id: I98d71100f28fb9bae05db3fb7d9afcb3f81beb43
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/29538
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GPP_C11 (FPMCU_INT_L) was set to DEEP, causing problems with S3.
Changed GPP_C11 configuration to use PLTRST instead.
BUG=b:114196791
TEST=Build, flash, boot nocturne, log in to kernel and execute
the following two commands and verify it passes :
echo 0 > /var/lib/power_manager/suspend_to_idle && restart powerd
sudo suspend_stress_test -c 2
Change-Id: I008532fce963c51a435378001440ac72b5ebfffc
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/29429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
add the memory parts as ram id 10:
hynix_dimm_H5ANAG6NAFR-UHC
BUG=b:113983573
BRANCH=Nami
TEST=emerge-nami coreboot chromeos-bootimage
Change-Id: I137259b88f39779768a58959a2dcc565645eee6d
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/29524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Some variants of nami will have a fingerprint MCU.
BUG=b:118503113
BRANCH=Nami
TEST=None (build and boot, but no hw yet)
Change-Id: I446dc09cdf7f84a801723cb403d2de80e0997c65
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/29297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
According to syndra thermal table, PL2 need to check cpu id.
Set up syndra PL2 value.
1. KBL_U PL2 is 25w.
2. KBL_R PL2 is 29w.
Refer to b:116836990#comment10.
BUG=b:116836990
TEST=The thermal team verify OK
Change-Id: I766a886121a089683565608252b4c176c70e88a3
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/29269
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Variants of Nami need to accommodate single channel DDR. Will use
GPP_D10 on nami for identification. GPP_D10 will return 1 when device
is using single channel DDR and 0 when using dual channel DDR.
BUG=b:117194353
BRANCH=None
TEST=dmidecode | grep Channel and make sure that the correct number of
channels gets returned.
Change-Id: If86ab2c5404c4e818ce496ea935227ab5e51730a
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/29233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change uses CRFP ACPI name for FP device since user space
utilities expect this name for triggering different actions.
BUG=b:112974410
BRANCH=nocturne
Change-Id: I63309227c916b43917e529c223cf738fc3baa209
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/29231
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On rammus, set GPIO GPP_C22 to 1 for touchscreen power on.
And add touchscreen device "PNP0C50" to I2C0.
According to touchscreen spec, device power on initialization takes
105 ms, so set "generic.enable_delay_ms" to 120.
We found there is i2c error log pop up when we set delay
time to be 110ms or 105ms. If we set delay time to be
120ms. System will not pop up i2c error log.
BUG=b:115944726
BRANCH=master
TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage
Flash FW to DUT, and make sure touchscreen works.
Change-Id: Ibce552d04991e85c99ae3a0a92455fc747d9fced
Signed-off-by: YanRu Chen <kane_chen@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Before entering the OS, the AP relies on the smi handler to shutdown the
system when the lid closes. Without the smi_events setting, the AP will
not receive the smi handler. As a result, the AP won't shutdown and will
always keep in S0.
This problem is caused by the https://review.coreboot.org/c/coreboot/+/28983
and this patch adds the smi_events back to support the smi handler for
the lid close.
BRANCH=master
BUG=b:115572596
TEST=test_that -b ${BOARD} ${IP} firmware_ECLidShutdown
Change-Id: Id82311a8ccd109f9c26516f59a45bdf34da98529
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/29191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Change link frequency of IMX319 from 360Mhz to 482.4 Mhz to match the
changes from kernel driver. IMX319 has two PLLs and it can be configured
either single or dual. Previous driver implemente dual PLL mode, however
image sensor vendor prefer single PLL mode and calculate the pixel rate
became easier. So the kernel driver changed to use single pll, coreboot
change will match that.
Bug=b:116082248
Change-Id: Iac9a72253e0529bf2c0785fb701b7bc251bcbab5
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/28736
Reviewed-by: Tomasz Figa <tfiga@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
While these pins were set to a pull-down 20KOhm, NPCX EC consumes
~2.1mW higher power. Becasue there was leakage current on both GPIO67
and GPIO70 from NPCX EC. With the external pull-up 10KOhm for
USB_OC0#/USB2_OC1#, this wasn't enough to prevent leakage current.
BUG=b:117139495
TEST=Check nxpc EC power to see power improvement
Change-Id: I685d876461c263f07ca4c8f8046635cb7087279c
Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com>
Reviewed-on: https://review.coreboot.org/29007
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Update CPU passive temperature threshold value from 70C to 80C,
to avoid early throttling for spiky workloads. Also, change CPU
throttling interval from 1 sec to 5 sec for CPU temperature.
BUG=b:116400298
BRANCH=None
TEST=Manual performance testing on nocturne.
Change-Id: Ic5031a4aa16f750237565f4e4928e78834b1d686
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/29044
Reviewed-by: Puthikorn Voravootivat <puthik@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since there are two cameras on Nami and only one camera on Syndra.
We need to disable rear camera/DMIC on all Syndra sku.
BUG=b:112876867
Change-Id: I92fb43ec84387c268ffdb6d0d34a5e5b13bcf50a
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/29022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
More platforms are not able to hibernate under certain circumstances,
such as when AC is plugged. This original path was conservatively put in
to prevent potential damage when cr50-update-caused asynchronous resets
occur. Julius' compelling argument that async resets from recovery mode
requests should have enough coverage of the design over the course of
project development. Remove the hibernate path and assume all is well
going forward.
Change-Id: I37121e75ff4e6abcb41d8534a1eccf0788ce2ea2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/29076
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds a variant callback to read google_chromeec_event_info
from variant at runtime to allow override of any events based on
factors like board id.
This callback is used in ramstage and smm to get
google_chromeec_event_info structure for performing various actions
like setting masks and logging wake events from EC.
BUG=b:112366846,b:112112483,b:112111610
Change-Id: If89e904c92372530a0f555952f87702f068e0b03
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Enrico Granata <egranata@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Its spreading copies got out of sync. And as it is not a standard header
but used in commonlib code, it belongs into commonlib. While we are at
it, always include it via GCC's `-include` switch.
Some Windows and BSD quirk handling went into the util copies. We always
guard from redefinitions now to prevent further issues.
Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Wifi wake register is incorrectly set in devicetree.
Set wifi wake to its correct wake source, GPE0_DW2_01.
BUG=b:117330593
TEST='emerge-nocturne coreboot chromeos-bootimage', flash nocture,
connect wifi to a hotspot, suspend device, echo freeze >
/sys/power/state, and then shutdown the hotspot and verify device
wakes.
Change-Id: Iafa865ca79d33541d7f47b69d2fb209e7f9c98af
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/28938
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The WAKE# signal has moved to LAN_WAKE, so WAKE# is now
floating and must be disabled. This change disables WAKE#.
BUG=b:117284700
TEST=none
Change-Id: I1c25e4ba28cd2b8807cd155d47c29c0d3ee9e8a5
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/28926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change uses the generic device driver to provide DMIC properties
in ACPI table to the OS driver.
BUG=b:112888584
Change-Id: I239f571bc29f02793f017a4713b5af03b23cfa3e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28797
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: HARSHAPRIYA N <harshapriya.n@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Nautilus-LTE sku shows abnormal reset symptom at high temperature chamber
test, but the root cause is unclear.
Experimentally, setting SlowSlewRate IA/GT/SA to 1/2 improves this abnormal
reset issue, so we would apply it until find root cause of this issue.
BUG=b:117130599
BRANCH=poppy
TEST=Built and passed on reliability test with modified coreboot
Change-Id: I7fa0041989113097e3b283dbcf4ca2a73629fe54
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/28785
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This adds the ACPI controls for power sequencing the touchscreen.
The initial setting is to keep the touchscreen powered off and in
reset. When linux is ready to talk to the touchscreen, it powers it
on and releases reset via ACPI.
BUG=b:110286344
TEST=verified touchscreen is functional in chromeos
Change-Id: I58c42a8f09342cfe54f82ef0e6cd8ea72a5140dc
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/28869
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GPP_C19 is not being set as the code is incorrectly setting
GPP_C16 instead, causing SAR sensor not to work, so this change
sets GPP_C19 to NF1.
GPP_E3 is not being initialized in the code. Initialize GPP_E3
to a no connect as documented in the board schematic.
BUG=b:117124878
TEST: 'emerge-coreboot chromeos-bootimage', flash nocturne and
verify that i2c transactions work for the left SAR sensor.
Change-Id: I9e972dbe4214cdd15d80d63dfa058e7755f7ecbb
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/28867
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Increase the reset delay for the touchscreen to 10 ms.
BUG=b:116857433
TEST='emerge-nocturne coreboot chromeos-bootimage', flash and boot
nocturne to kernel, log in and execute the following two commands:
echo "i2c-WCOM50C1:00" > /sys/bus/i2c/drivers/i2c_hid/unbind
echo "i2c-WCOM50C1:00" > /sys/bus/i2c/drivers/i2c_hid/bind
and verify the bind command does not echo back a
"-bash: echo: write error: No such device" error.
Change-Id: I102b57ea5a10d22bee6d4f7c6f114b380a5d586b
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/28803
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Caveh Jalali <caveh@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch modifies "oem_table_id" from "RAMMUSMAX" to "RAMMUS"
so that the audio topology file can be loaded properly by the
operating system.
BUG=b:112945714
BRANCH=master
TEST=There is no error message like "failed to load topology firmware" in
kernel v4.4 log.
Change-Id: I66a38ea38791dd3d9606a05b7b696236c350237f
Signed-off-by: Marx Wang <marx.wang@intel.com>
Reviewed-on: https://review.coreboot.org/28870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Use GPIO GPP_D17 pin as the EC sync interrupt and provide this value
to the embedded controller to be exported to the OS.
This interface was tested on a reworked Nocturne board with modified
EC and a modified kernel driver to ensure that the interrupt asserts
as expected and can be used by the kernel driver.
Change-Id: Ie2b33692367b5d9ecc2b128180d8cfe4f6b347b1
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/28759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Increase power limit1 maximum value from 5W to 7W. This value as per
recent measurement on closed system which shows better performance
results.
BUG=None
TEST=Build and tested on Nocturne system. Performance tests
show better results.
Change-Id: I7485b1d2afde46ec28d548c13be35a43e7572918
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/28686
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Puthikorn Voravootivat <puthik@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The previous does not work well enough when testing with
high ambient temperature. Update DPTF settings to make
it work better.
List of tweaks:
1. Raise DRAM Critical temperature from 48C to 55C
Note that there are mechanisms in EC that complement
this because of DPTF limitation that we can't have
multiple passive temperatures.
2. Lower response time for DRAM temp sensor from 60s to 5s.
3. Increase throttle priority to the charger when DRAM hit
passive temperature from 100 to 200.
BUG=b:112550414
BRANCH=None
TEST=Manually tested by thermal team.
Change-Id: Idf7efa76b2c6085cf97aa9f65c6ce066e8cff99a
Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org>
Reviewed-on: https://review.coreboot.org/28738
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch sets the MRC UPD "CmdTriStateDis" to disable TriState for
the rammus boards. Rammus is LPDDR3 design without RTT for CMD/CTRL.
BUG=none
TEST=Run memtester app and also webgl fishtank on the LPDDR3 kabylake
boards and also check the margin data is proper in FSP.
Change-Id: Iee115f49ba5b36dc5b0425e9da02b58cd19b2236
Signed-off-by: Marx Wang <marx.wang@intel.com>
Reviewed-on: https://review.coreboot.org/28568
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change GPP_D17 and GPP_D18 to no connects as DMIC was moved
to DMIC0.
BUG=b:113744731,b:111106010
TEST=none
Change-Id: I8ef42627e542182707c81389af9da33a114bc184
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/28689
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As we don't use the MIPI camera on Rammus, disable SA Imaging Unit and
CIO2 devices to avoid the system failed to enter S0ix.
BUG=b:114502527
BRANCH=master
TEST=On DUT, echo freeze > /sys/power/state
1. check the S0ix status on EC console
2. check the value of /sys/kernel/debug/pmc_core/slp_s0_residency_usec
Change-Id: I91629732db01ee534f0ddb67a2b358d725ef810e
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/28543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch sets the MRC UPD CmdTriStateDis for the atlas boards.
Atlas is a LPDDR3 design without RTT for CMD/CTRL.
The original change for
nocturne is I0f593761dcbd121e7e758421af178931b9d78295
mb/google/poppy: Set UPD CmdTriStateDis for Nocturne
BUG=b:111812662
Change-Id: I45b6dd22412c689c8db64f4650e9fa9e87dec2ec
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/28540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Only for those that are x86 and also have a RW_LEGACY region.
The assumption is that all devices touched have 64k block sizes when
choosing size and alignment of the region.
Change-Id: I12addb137604f003d1296f34f555dae219330b18
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/28532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
