Memory SPD files for each variant are now stored in the variant's
mb/google/volteer/variants/<variant_name>/spd directory instead
of storing them in mb/google/volteer/spd.
This change moves SPDs to where they are needed and changes the
makefile to look for them in their new locations.
BUG=b:156126658
TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot
a proto2 SKU4 to the kernel.
Change-Id: I759c979027477a2a4c5489a6b12278799488d6e7
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41184
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Stefan thinks they don't add value.
Command used:
sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool)
The exceptions are for:
- crossgcc (patch file)
- gcov (imported from gcc)
- elf.h (imported from GNU's libc)
- nvramtool (more complicated header)
The removed lines are:
- fmt.Fprintln(f, "/* This file is part of the coreboot project. */")
-# This file is part of a set of unofficial pre-commit hooks available
-/* This file is part of coreboot */
-# This file is part of msrtool.
-/* This file is part of msrtool. */
- * This file is part of ncurses, designed to be appended after curses.h.in
-/* This file is part of pgtblgen. */
- * This file is part of the coreboot project.
- /* This file is part of the coreboot project. */
-# This file is part of the coreboot project.
-# This file is part of the coreboot project.
-## This file is part of the coreboot project.
--- This file is part of the coreboot project.
-/* This file is part of the coreboot project */
-/* This file is part of the coreboot project. */
-;## This file is part of the coreboot project.
-# This file is part of the coreboot project. It originated in the
- * This file is part of the coreinfo project.
-## This file is part of the coreinfo project.
- * This file is part of the depthcharge project.
-/* This file is part of the depthcharge project. */
-/* This file is part of the ectool project. */
- * This file is part of the GNU C Library.
- * This file is part of the libpayload project.
-## This file is part of the libpayload project.
-/* This file is part of the Linux kernel. */
-## This file is part of the superiotool project.
-/* This file is part of the superiotool project */
-/* This file is part of uio_usbdebug */
Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Kernel pinctrl driver changed for Tiger Lake and went to old scheme.
Kernel patch: https://chromium-review.googlesource.com/c/chromiumos/
third_party/kernel/+/2116670
BUG=b:151683980
BRANCH=none
TEST=Build and boot tgl board. In /sys/kernel/debug/pinctrl
verify INTC34C5:00 listing all the pins.
Cq-Depend:chromium:2116670
Change-Id: I9f1d399ff7380125ad5b935f9590a7d9cc442b04
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39801
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change moves all ACPI table support in coreboot currently living
under arch/x86 into common code to make it architecture
independent. ACPI table generation is not really tied to any
architecture and hence it makes sense to move this to its own
directory.
In order to make it easier to review, this change is being split into
multiple CLs. This is change 3/5 which basically is generated by
running the following command:
$ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g'
BUG=b:155428745
Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
BUG=b:152893285
BRANCH=none
TEST=Build and boot to OS volteer with Intel SATA and reboot
from OS console
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ibed8f8c445bf2ac2290ffb670d8dfb83fc960438
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Create the trondo variant of the volteer reference board by copying the
template files to a new directory named for the variant.
BUG=b:154678884
BRANCH=None
TEST=util/abuild/abuild -p none -t google/volteer -x -a
make sure the build includes GOOGLE_TRONDO
Change-Id: Ie4f9bfe4798e14f91c6cb439f5c5ab2b9ea52b51
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40686
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Setting the default values for GPIO community power management, causes
issues in detecting TPM interrupts. So to avoid that GPIO PM has to be
disabled in devicetree. But for S0ix it is needed. This patch implements
a workaround in ASL code to enable GPIO PM on S0ix entry and disable it
on S0ix exit.
This patch adds the following three platform specific methods.
1. MS0X to enable power management features for GPIO communities on
entry and on exit, it disables them.
2. MPTS to enable power management features for GPIO communities when
preparing to sleep.
3. MWAK to disable power management features for GPIO communities on
waking up.
BUG=b:148892882
BRANCH=none
TEST="Boot with this change on volteer proto1 and check for GPIO
community config with debugger"
Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com>
Change-Id: If522c82c0069a4bf5738beb73a2b4f11ed6f51d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40261
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Venkata Krishna Nimmagadda <Venkata.krishna.nimmagadda@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Implements mainboard_get_dram_part_num() to override dram part number
with a part number read from CBI.
BUG=b:146464098
TEST="emerge-volteer coreboot chromeos-bootimage", flash volteer, boot
and log into kernel, execute "mosys memory spd print id" and verify that
the memory part number from the cbi gets displayed properly.
Change-Id: I3a20691f601cb513ee0936c8d141233c3d06db3d
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40472
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Remove explicit setting of iDisp Link parameters. These settings are
related to configuration for the link between HD-Audio controller and
Display unit for purposes of HDMI/DP Audio playback. During PO,
observed that without setting these params display part was not
binding. With the latest code verified that we dont need to explicitly
set these parameters anymore. HDMI/DP audio playback works fine with
default settings.
BUG=b:151451125
BRANCH:none
TEST= build and boot volteer/ripto and verify HDMI/DP audio playback
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Ie003d119918d363e2ff9172936b70416fd73c7f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40263
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jairaj Arava <jairaj.arava@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update device enable/disable based on PCH EDS#576591 vol1 rev1.2
BRANCH=none
BUG=b:154037185
TEST= boot up OS in volteer and check and check lspci
Unsupported IP should be visable from lspci result
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I61a328da1014ab7584c3ec789971a106c7a0a403
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40394
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
BUG=b:151166040
TEST= build and boot volteer and check LTR and AER value
from FSP log
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ibbf55e6a08ff5e8f358325bb8e9f1487cc982f95
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40268
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to Intel Document #616599,
1) SPD byte offset #5 for Tiger Lake should be "0x21" (16 rows, 10
columns)
2) SPD byte offset #13 for Tiger Lake should be "0x01" (1 channel
x16)
This change fixes those two values in the existing SPD files for
Volteer, and zero's byte 9 (bytes 8-11 should be zero'd out in a
generic SPD).
BUG=b:152827558
TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot
Volteer to kernel.
Change-Id: Ice6a32a2b3827cf99d8e109731ffd9efabf68de1
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Fix GPIO_PCH_WP (GPP_B11) to associate GPP_PCH_WP with community
zero instead of community 1.
BUG=b:152876091
TEST="emerge-volteer coreboot chromeos-bootimage", flash, boot to
and log into Volteer kernel, execute "wp enable" in H1 console,
execute "crossystem" at kernel prompt and verify that "wpsw_cur"
shows as being "1", Execute "wp disable" in H1 console, execute
"crossystem" at kernel prompt and verify "wpsw_cur" is 0.
Change-Id: I082154efd72459ec54999ed7c7bb7420a38f7b6e
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Update memory configuration on Tiger Lake platform to enable Early
Command Training. This feature was not supported before FSP v2527.
BUG=b:150357377
BRANCH=None
TEST= Build and boot volteer
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I674c30f4dfc1af6c0c4a460d66684545a190caf3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40023
Reviewed-by: Dossym Nurmukhanov <dossym@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I8e2aaf681ba3543cfcd400d21f8e94454e9b1c98
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40202
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These two identifiers were always very confusing. We're not filling and
injecting generators. We are filling SSDTs and injecting into the DSDT.
So drop the `_generator` suffix. Hopefully, this also makes ACPI look a
little less scary.
Change-Id: I6f0e79632c9c855f38fe24c0186388a25990c44d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39977
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: David Guckian
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change reorganizes memory initialization code for LPDDR4x on
TGL to allow sharing of code when adding support for other memory
types. In follow-up changes, support for DDR4 will be added.
1. It adds configuration for memory topology which is currently only
MEMORY_DOWN, however DDR4 requires more topologies to be
supported.
2. spd_info structure is organized to allow mixed topologies as well.
3. DQ/DQS maps are organized to reflect hardware configuration.
TEST=Verified that volteer still boots and memory initialization is
successful.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ib625f2ab30a6e1362a310d9abb3f2051f85c3013
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
This commit creates a malefor variant for Volteer. The initial settings
override the baseboard was copied from variant ripto. Fine tune GPIO
and memory DQ based on malefor schematics.
BUG=b:150653745
BRANCH=volteer
TEST=emerge-volteer coreboot
Signed-off-by: William Wei <wenxu.wei@bitland.corp-partner.google.com>
Change-Id: Idbeebb13e537287686344740211143df35b7863a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39857
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In order to create a working baseline all ports are being set to have
retimers. Setting the TcssAuxOri UPD to 0 in order for the SoC to not
misconfigure the ports. Volteer will need some additional changes after
this is implemented to account for ports that do not have a retimer.
This setting is in the process of being documented in the TGL EDS and we
can update once it is fully understood what this setting is changing on
the SOC side.
BUG=b:145943811
BRANCH=none
TEST=Boot to OS and check Type-C port1 Display on Volteer,
Connecting Type-c display should work regardless of Type-c cable
orientation.
Change-Id: I29eb0513299126ad8d1ee11ded2c771f28ad13f3
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39460
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the halvor variant of the volteer reference board by copying the
template files to a new directory named for the variant.
BUG=b:151399850
BRANCH=None
TEST=util/abuild/abuild -p none -t google/volteer -x -a
make sure the build includes GOOGLE_HALVOR
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: If4d3417ba55d56af441c99d949a196328d7a1951
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Add camera ACPI configuration for Ripto/Volteer
BUG=None
BRANCH=None
TEST=Build and boot Ripto or Volteer. Start camera app and able to
capture images.
Signed-off-by: Daniel Kang <daniel.h.kang@intel.com>
Change-Id: I2b47ccd989192273a29f09bf097e12e357929334
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
This is required for PD notifications on the cros_ec driver.
BUG=b:150649744
TEST=Boot volteer with this patch and verify that PD notifier events are
being generated.
Signed-off-by: Prashant Malani <pmalani@chromium.org>
Change-Id: I2e72320b025a3dfa7412181586cb142a4503eda5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
They're listed in AUTHORS and often incorrect anyway, for example:
- What's a "Copyright $year-present"?
- Which incarnation of Google (Inc, LLC, ...) is the current
copyright holder?
- People sometimes have their editor auto-add themselves to files even
though they only deleted stuff
- Or they let the editor automatically update the copyright year,
because why not?
- Who is the copyright holder "The coreboot project Authors"?
- Or "Generated Code"?
Sidestep all these issues by simply not putting these notices in
individual files, let's list all copyright holders in AUTHORS instead
and use the git history to deal with the rest.
Change-Id: I09cc279b1f75952bb397de2c3f2b299255163685
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Volteer uses 4 bits (hardware straps) to indicate what memory
configuration the board is populated with (i.e. which SPD file
to use for the populated memory). This allows for only 16
different SPDs for supporting Volteer and all future variants of
Volteer. Currently, each memory chip needs its own SPD file, so we
can only support 16 different memory chip options for Volteer and
all of its variants.
Generic SPD files are just SPD files that have been stripped down
to contain only fields that are important for the memory controller
(strips out items like vendor info, for example). Using generic SPD
files allows for more than 16 different memory options given it's no
longer a 1-to-1 mapping as similar memory modules from different
vendors can share the same generic SPD file.
BUG=b:147857288
TEST="emerge-volteer coreboot chromeos-bootimage", flash ripto and
verify ripto boots to kernel and "cat /proc/meminfo" reports 8GB
of memory.
Change-Id: I17bd4f4a00b4e3bbaf845d6d321962c11569a186
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39423
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Provide settings for configuring the link between HD-Audio controller
and display unit for purposes of HDMI/DP Audio playback.
BUG=b:144708516, b:148385924
TEST=none
Change-Id: I225faac68729b28be65b4d8f1f83769a874f84ff
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39356
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Limit PcieL1Substate for RP9, RP11 for ES1 NVMe warm reboot workaround.
Reference: #613582 Tiger Lake PCH-LP Sightings Report
issue id #1409566330
BUG=none
BRANCH=none
TEST= boot to OS and check warm reboot with NVMe
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ie85bf71c43427e326ef2ba674da4566f8f51495a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Optane memory module shows up as 2 NVMe devices in x2 config - NVMe
storage device and NVMe Optane memory. Storage device uses rp9 and
optane memory uses rp11. This patch enables rp11. Please note that
these two share clk related pins.
Configuring pciecontroller3 to be set from 2x2. This will by done by
auto detecting optane memory: enabling HybridStorageMode.
BUG=b:148604250
BRANCH=chromeos
TEST='Build, boot and look for two NVMe devices with lspci on Volteer'
Cq-Depend: chrome-internal:2501837
Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com>
Change-Id: I5430829b496ed275e2e3bda3c0bf21c3d2132628
Reviewed-on: https://chrome-internal-review.googlesource.com/c/chromeos/third_party/coreboot-intel-private/jsl-tgl/+/2424428
Tested-by: Wonkyu Kim <wonkyu.kim@intel.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39420
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- declare the FPMCU interrupt to be level-triggered
- change EC_PCH_WAKE_ODL gpio to native function mode
- corrected spelling of a signal name in a comment
BUG=b:144933687, b:148179954
BRANCH=none
TEST=none
Change-Id: I62da900d0b71139e55b52d06ec09ca25106f73cd
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change uses drivers/intel/wifi chip for CNVi device and
adds dynamic SSDT entires for CNVi also export wake gpio for CNVi.
BUG=none
BRANCH=none
TEST=Build and boot volteer
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Ia8baf1c7b770db23f31383bda46ae8d090468560
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
wpsw_boot is deprecated in favour of wpsw_cur. As such,
coreboot no longer needs to share "write protect" GPIO
with depthcharge.
BUG=b:124141368, chromium:950273
TEST=make clean && make test-abuild
BRANCH=none
Change-Id: I2fcb7f82aa063fd72928171af5cbef0356ba620c
Signed-off-by: Joel Kitching <kitching@google.com>
Cq-Depend: chromium:2088434
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39318
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a new ripto variant based off of the volteer baseboard design.
BUG=b:148385924, b:150810535
TEST="emerge-volteer coreboot chromeos-bootimage", flash ripto image
and verify ripto boots to the kernel.
Change-Id: If7606588147500a465f16c7846e2c8429ece93ec
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39301
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Previously, each Intel chipset had its own sleepstates.asl file.
However, this is no longer the case, so drop these comments.
This follows commit 408d1dac9e.
Change-Id: I0c0f4ad8bf743010ebdd2d53fcf297aeab64a662
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
