GNUBoot/coreboot-kgpe-d16
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173 commits

Author SHA1 Message Date
Yinghai Lu
815ced3f7a 1M boundary for _RAMBASE=1M, and CONFIG_LB_TOPK 8M above support 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2152 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-01-04 20:41:05 +00:00
Yinghai Lu
6c02eb2cb5 indirect jmp with * 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2145 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-12-14 23:13:13 +00:00
Yinghai Lu
30576601f6 from issue 53: don't set TOM2 if 4G less mem installed, opt for init_ecc 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2144 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-12-14 20:16:49 +00:00
Yinghai Lu
6f63c0297c support HDT disassembly when cache as ram auto stage 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2143 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-12-14 20:08:23 +00:00
Yinghai Lu
72ee9b0ebe issue 51 and 52: set mtrr for ap before stop it, and _RAMBASE above 1M 
support and pgtbl after 1M support


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2142 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-12-14 02:39:33 +00:00
Yinghai Lu
f42e1770f9 make clear_1m_ram.c to support gcc 3 and gcc4 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2141 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-12-09 01:58:07 +00:00
Yinghai Lu
c3b3600222 use CONFIG_LB_MEM_TOPK instead 1M hardcode from issue 50 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2139 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-12-07 19:02:45 +00:00
Stefan Reinauer
7ce8c54e2b 1201_ht_bus0_dev0_fidvid_core.diff 
https://openbios.org/roundup/linuxbios/issue41
Lord have mercy upon us.




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2118 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-12-02 21:52:30 +00:00
Stefan Reinauer
f5183cfa19 Applying YhLu's patch from issue 37. 
a. apic id liftting to way that kernel like and let bsp
   to stay with 0
b. hw memhole: solve if hole_startk == some node
   basek
                 
This, together with the previous one will break most of 
the tree, but Yinghai Lu is really good
at fixing things, so...

   


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2116 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-12-01 11:01:01 +00:00
Stefan Reinauer
806e146e75 Applying 11_26_car_tyan.diff from Yinghai Lu. 
NOTE: This will break the tree so it can be fixed up later



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2115 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-12-01 10:54:44 +00:00
Stefan Reinauer
f622d598db - Apply 11_24_a_s1_core.diff from 
https://openbios.org/roundup/linuxbios/issue24
- fix up for via epia-m



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2110 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-11-26 16:56:05 +00:00
Stefan Reinauer
af77a61a9c add another Via C3 cpu id reported by grzegorz@el-kom.pl 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2108 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-11-26 11:57:57 +00:00
Ronald G. Minnich
d6bd192f6c remove rev f ifdef 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2097 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-11-23 21:12:47 +00:00
Ronald G. Minnich
fb0a64ba77 CAR patch from YH LU 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2096 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-11-23 21:01:08 +00:00
Ronald G. Minnich
872141a402 Split out microcode updates. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2095 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-11-23 20:52:43 +00:00
Ronald G. Minnich
ed1f9a75b3 missed these. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2093 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-11-23 05:09:42 +00:00
Ronald G. Minnich
9b6b3d22a2 issue 25, various AMD patches 
Signed-off-by: Ronald G. Minnich


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2092 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-11-23 04:56:36 +00:00
Ronald G. Minnich
9442591f42 fixed fsf address 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2091 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-11-22 16:47:40 +00:00
Ronald G. Minnich
43225bc804 EPIA-M fixup 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2090 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-11-22 00:07:02 +00:00
Ronald G. Minnich
86cbd33837 This was posted on issue tracker and approve by ron minnich 
Signed-off-by: Ronald G. Minnich


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2089 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-11-21 23:22:21 +00:00
Stefan Reinauer
2fd467ce3c reverting rev 2082 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2083 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-11-03 08:13:39 +00:00
Eswar Nallusamy
ed00937103 ppc970 initial porting. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2082 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-11-02 17:32:49 +00:00
Jason Schildt
bc6281a8fe - See Issue Tracker id-6 "lnxi-patch-6-replacement" 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2070 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-10-25 21:28:41 +00:00
Jason Schildt
8b26cab08f - See Issue Tracker id-4 "lnxi-patch-4" 
- In addition:
	modified apic_id lifting to always lift all CPUs.  This may cause problems with older kernels.



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2068 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-10-25 21:24:23 +00:00
Jason Schildt
6a2c09a386 - See Issue Tracker ID-3 "lnxi-patch3" 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2067 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-10-25 21:07:34 +00:00
Greg Watson
aa9ef4195a trying to compile... 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2062 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-10-19 21:55:47 +00:00
Greg Watson
5fc3aa73eb get include files right 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2061 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-10-19 20:32:05 +00:00
Greg Watson
58b971e799 start of 970 port 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2056 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-10-19 18:03:08 +00:00
Ronald G. Minnich
20d943d9f9 adding support for dell 1850 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2054 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-10-19 17:02:34 +00:00
Stefan Reinauer
6ab43fcc48 Updating FSF address in the code. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2051 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-10-05 18:17:45 +00:00
Ronald G. Minnich
803719a22d comments mods. THings are working better, so I'm less unhappy with 
this part :-)


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2049 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-09-26 16:48:24 +00:00
Ronald G. Minnich
87888630b2 sc520 support -- ethernet works 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2047 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-09-23 17:08:58 +00:00
Jonathan McDowell
1718c4771b Make EPIA-M use CONFIG_TSC. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2039 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-09-14 16:33:10 +00:00
Steven J. Magnani
059182cc4f Print a failure message if a sibling CPU fails to start. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2031 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-09-14 13:52:06 +00:00
Steven J. Magnani
a7c70bcb3a Fix hang during secondary CPU sibling init caused by nested spinlocks. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2022 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-09-12 18:38:10 +00:00
Ronald G. Minnich
e50570112f sc520 now builds fine. On to testing. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2021 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-09-12 15:20:28 +00:00
Ronald G. Minnich
e118a047b9 moved to include/cpu/amd/sc520.h 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2020 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-09-12 13:43:59 +00:00
Ronald G. Minnich
c06ca3af71 updated to new svn repo 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2018 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-09-12 13:42:12 +00:00
Stefan Reinauer
246ae2129e simplify code 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2012 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-09-08 17:17:25 +00:00
Jonathan McDowell
afa190e046 Add VIA C3 Nehemiah CPUID, as reported by Doug Bell. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2011 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-09-05 09:30:01 +00:00
Hamish Guthrie
e251c42197 Changed udelay in delay_tsc to be more be more considerate of single 
processor environments.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2009 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-08-17 04:48:17 +00:00
Jason Schildt
043b409904 Undoing all HDAMA commits from LNXI from r2005->2003 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2006 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-08-10 15:16:44 +00:00
Jason Schildt
6e44b422b3 - Merge from linuxbios-lnxi (Linux Networx repository) up to public tree. 
- Special version for HDAMA rev G with 33Mhz test and reboot out.
        - Support for CPU rev E, dual core, memory hoisting,
        - corrected an SST flashing problem. Kernel bug work around (NUMA)
        - added a Kernel bug work around for assigning CPU's to memory.

 r2@gog:  svnadmin | 2005-08-03 08:47:54 -0600
 Create local LNXI branch
 r1110@gog:  jschildt | 2005-08-09 10:35:51 -0600
 - Merge from Tom Zimmerman's additions to the hdama code for dual core
   and 33Mhz fix.
 
 
 r1111@gog:  jschildt | 2005-08-09 11:07:11 -0600
 Stable Release tag for HDAMA-1.1.8.10 and HDAMA-1.1.8.10LANL
 r1112@gog:  jschildt | 2005-08-09 15:09:32 -0600
 - temporarily removing hdama tag to update to public repository.  Will
   reset tag after update.
 
 


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2004 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-08-09 21:53:07 +00:00
Greg Watson
78e0b0edf4 Updated ep405pc to latest config system. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1984 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-07-20 18:28:12 +00:00
Yinghai Lu
13f1c2af8b eric patch 
1. x86_setup_mtrr take address bit.
        2. generic ht, pcix, pcie beidge...
        3. scan bus and reset_bus
        4. ht read ctrl to decide if the ht chain
           is ready
        5. Intel e7520 and e7525 support
        6. new ich5r support
        7. intel sb 6300 support.

yhlu patch
	1. split x86_setup_mtrrs to fixed and var
	2. if (resource->flags & IORESOURCE_FIXED ) return; in device.c pick_largest_resource
	3. in_conherent.c K8_SCAN_PCI_BUS


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1982 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-07-08 02:49:49 +00:00
arch import user (historical)
fb07bf4aca Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-62 
Creator:  Yinghai Lu <yhlu@tyan.com>

add eswar code in intel car to disable Hyperthreading


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1980 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-07-06 18:17:43 +00:00
arch import user (historical)
54d6b08f01 Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-54 
Creator:  Ronald G. Minnich <rminnich@lanl.gov>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1970 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-07-06 17:17:41 +00:00
arch import user (historical)
6ca7636c8f Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-51 
Creator:  Yinghai Lu <yhlu@tyan.com>

cache_as_ram for AMD and some intel


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1967 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-07-06 17:17:25 +00:00
arch import user (historical)
b2ed53dd56 Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-50 
Creator:  Ronald G. Minnich <rminnich@lanl.gov>

This now boots to the point of passing the memory test in auto.c. But: we still don't have it working after the "Jumping to LinuxBIOS" step


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1966 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-07-06 17:16:23 +00:00
arch import user (historical)
69c79d232e Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-49 
Creator:  Ronald G. Minnich <rminnich@lanl.gov>

this is a version that  does not fail, but memory is still not up


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1965 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2005-07-06 17:16:21 +00:00