Now that an idt is available in every stage utilize it for exception
processing to help catch and debug issues.
BUG=b:72728953
Change-Id: I69e7f938f36f2e522b787e311fd148bb8fd41247
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25764
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The FU540 is the first RISC-V SoC with the necessary resources to run
Linux (an external memory interface, MMU, etc).
More information is available on SiFive's website:
https://www.sifive.com/products/hifive-unleashed/
Change-Id: Ic2a3c7b1dfa56b67cc0571969cc9cf67a770ae43
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The argument order for smi_write32() is offset, value. Current code had
it backwards.
So, when disable_all_smi_status() was called by sb_slp_typ_handler(),
instead of clearing pending flag SlpTypeEvent65 (0x2) in SMIx88 SmiStatus2
by writing 0x00000002 to 0xfed80288, it would instead write
0x00000088 to 0xfed80202 - clearing the lower 2 bytes of SMIx04
Event_Enable, which disabled the lower 16 GPEs from waking the system from S3.
Thus, the EC events (Keyboard / lid switch) [GPE15] and touchpad [GPE7]
did not work as wake up sources.
BUG=b:78461678
TEST=powerd_dbus_suspend, tapping any key on keyboard wakes from S3.
Change-Id: Ie4fbe6db1bb73f603dcf409117fcce93479a1f46
Fixes:081851a9e4 ("amd/stoneyridge: Add SlpTyp SMI handler")
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/25815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
smi_sources is a file local array of constants.
Change-Id: I431f181449a591ccaf8395f01a84c8e006a29b52
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/25814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
It's going to be necessary to know the i/o hole size as well
the amount of memory configured in the sytsem. Therefore, add
two helper functions:
memory_in_system_in_mib()
iohole_in_mib()
Both return values in units of MiB.
BUG=b:72728953
Change-Id: I481ba517c37f769e76d9e12b3631f5f99b5427a9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25738
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Additional LPC and SPI setup needed to move AGESA out of the bootblock.
Setup the prefetch, sio decode, and a bugfix for SPI.
BUG=b:70558952
TEST=Boots with AGESA moved out of bootblock.
Change-Id: I2c0d8632b25c036ff977c21477feb4778575189c
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/25755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch makes our devicetree in sync with the FSP configuration.
Without this we see in boot logs "PCI: 00:00.2 not found,
disabling it". The reason being in FSP NPK device is disabled by
default. We can enable it by enabling the UPD parameter TraceHubEn.
If we enable it in FSP then the logs complain the NPK pcie device
is not seen.
BUG=b:76115112
TEST=Build for Octopus and check that the logs do not report
"PCI: 00:00.2 not found, disabling it".
Change-Id: I8fe3a36dac2eff2225dacb0e6e16500a5750261e
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/25333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Found-by: Coverity (CID 1387031: Memory - illegal accesses
(BUFFER_SIZE_WARNING)). Calling strncpy with a maximum size argument of
19 bytes on destination array "dimm->module_part_number" of size 19 bytes
might leave the destination string unterminated. Fix the size parameter.
BUG=b:76202696
TEST=Build and boot kahlee, using special debug code to see the output
strings, which was later removed.
Change-Id: I18fa5e9c73401575441b6810f1db80d11666368c
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Julius brought up confusion about the current spi api in [1]. In order
alleviate the confusion stemming from supporting x86 spi flash
controllers:
- Remove spi_xfer_two_vectors() which was fusing transactions to
accomodate the limitations of the spi controllers themselves.
- Add spi_flash_vector_helper() for the x86 spi flash controllers to
utilize in validating driver/controller current assumptions.
- Remove the xfer() callback in the x86 spi flash drivers which
will trigger an error as these controllers can't support the api.
[1] https://mail.coreboot.org/pipermail/coreboot/2018-April/086561.html
Change-Id: Id88adc6ad5234c29a739d43521c5f344bb7d3217
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The EFER and PAT MSRs are x86 architecturally defined. Therefore,
move the macro defintions to msr.h. Add 'paging' prefix to the
PAT and NXE pae/paging functions to namespace things a little better.
BUG=b:72728953
Change-Id: I1ab2c4ff827e19d5ba4e3b6eaedb3fee6aaef14d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
On a second look broadcom/cygnus and imgtec/pistachio appear to
support full duplex. Therefore, remove the use of spi_xfer_two_vectors().
For mediatek/mt8173 and qualcomm/ipq40xx, the driver is written in such
a way that it does not support full duplex. Remove the use of
spi_xfer_two_vectors() and explicitly error out when a full duplex
transaction is requested.
Change-Id: I8689bc9bb2b27563d25e9f165487d38881c0b059
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25742
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move inline function where they belong to. Fixes compilation
on non x86 platforms.
Change-Id: Ia05391c43b8d501bd68df5654bcfb587f8786f71
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25720
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The GPIO definition structure has evolved to a point where it's no longer
specific to stoneyridge, though probably still specific to AMD. Therefore,
rename the GPIO declaration structure removing stoneyridge from it.
BUG=b:72875858
TEST=Build kahlee, grunt, gardenia.
Change-Id: Ib034d3f7840c36ee8f5c5384241d7326d3fe5543
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25726
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Check same IO ranges get programmed first, if so just skip it to avoid double
programming.
BUG=b:77944335
TEST=Boot up with mewoth board, and check serial log, there's no error
message about "LPC: Cannot Open IO Window: ".
Change-Id: I89f9bb70320f91b16c6084384c4a0a53ede3760c
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/25667
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There are sections of code that are almost identical and they can be
converted to auxiliary procedures. For allocating heap, 3 sizes (the
buffer size of currently being examined node, the buffer size of the
current best fit node and the minimum size for a buffer that will need
to be split if selected as the best fit) are used often so they could
be stored in temporary variables. These 2 changes will make code shorter,
with less indentation problems and overall easier to read. The actual
logic of the code is not changed.
BUG=b:77940747
TEST=Build and boot grunt.
Change-Id: Ib4c69981eab7452228ccae9ed9bc288c8baceffe
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25703
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
DRAM Initialization Scratchpad Bit needs to be set after Dram
Initialization finished, according to Cannonlake PCH-LP EDS(#565870)
chapter 5.3.1.
BUG=None
Change-Id: I16dd3787cb743bc5b7492042f3c3757534e1a51c
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/25704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Kin Wai Ng <kin.wai.ng@intel.com>
Force PCH LPC generic IO ranges are identical between PCH LPC pci config
space and DMI PCR registers. Reference documentation from 570374 chapter
2.4.1.
Bug=77944335
TEST=Boot up in OS in meowth board, using iotools to read LPC pci
config space offset 0x84~0x90 and compare with values read from DMI PCR
private register offset 0x2730~0x273c are identical.
Change-Id: I72a40360ba67f443f24468f10504d8cfd0b099ca
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/25668
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With the exception of code that deals directly or indirectly with AGESA,
all other code should be independent of vendor code reference. Therefore,
remove vendor code reference from any GPIO code.
BUG=b:77999987
TEST=Build and boot grunt.
Change-Id: I9ba78767a269ad6b9b06fa11993d8a12350e4bad
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25695
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Creates a common asl include file for PCIe power state methods. This
allows ports to be enabled independently.
BUG=None
BRANCH=None
TEST=None
Change-Id: I7b1cf4e14ebdfe9ecc7131dfe47c70ed7e2c3dc5
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/25532
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Because thermal table is not included the values of DPTF_TSR0_ACTIVE_AC5
and DPTF_TSR0_ACTIVE_AC6 from internal nami/vayne thermal team.
Add conditional compilation in _ACx methods if DPTF_ENABLE_FAN_CONTROL
is defined in the dptf.asl.
BUG=b:72974136
BRANCH=poppy
TEST=emerge-nami coreboot and booted on nami board.
Change-Id: I3e36ce94f714ff13f8ccee65992d7a9c7e0bb5b2
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25614
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The latest public BKDG (3.6) releases some previously undefined (reserved)
bits. Fix these definitions, including the header file where they are
defined.
BUG=b:77940747
TEST=Build and boot grunt.
Change-Id: Icb5334110248d7806421200a161fa3befefcea8a
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25665
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The latest public BKDG (3.6) releases some previously undefined (reserved)
bits, also some bits were wrongly named (possibly copied from previous chip).
Fix these definitions, including the header file where they are defined.
BUG=b:77940747
TEST=Build and boot grunt.
Change-Id: Ie8d3fcccb8443c1a6db828bdc2624778bad6ba9f
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Also base the FSP/GOP related bail-out on the correct Kconfig option
to allow adding a VBT along with libgfxinit.
Most things should work, what doesn't is backlight control because
coreboot misses the settings (moved to FSP and need backporting).
Also, Kaby Lake is still unsupported.
TEST=Booted yet to be upstreamed Skylake-S port (Kontron/bSL6) both with
text and linear framebuffer mode and viewed a FILO menu.
Change-Id: I79fbfed7732cf02d054530ea7ec0d34de32836ba
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This makes FSP use the same baud rate as coreboot so that the user can
more easily change it without having to modify the FSP binary.
Change-Id: I0084aa9a0394ad7eabdd88809b66fc21a25ba316
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/25666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
On glk there's a 4MiB L2 cache all the time. Take advantage of that
by initializing a 1MiB cache-as-ram area.
BUG=b:72728953
Change-Id: Ia4e777a13607d8b70c05534b0a172f0ec6b04c51
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25645
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The pch_smbus_init() function contains code to enable clock gating for
the SMBus controller. Unfortunately this code is buggy and leads to a
hanging system with the latest microcode version.
The hang occurs as follows:
The clock gate register is mapped into RCBA space. After reading the
RCBA address from the LPC device config space no mask is applied to the
value (only bits 31..14 are valid while bit 0 is the enable bit). For
this reason the final address is off by one. The old microcodes at least
allowed this unaligned access to the RCBA space. With the latest
microcode this access leads to CPU hang.
Once this is fixed the next issue occurs: After setting the clock
gating bit for SMBus (bit 5) the SMBus controller disappears from the
PCI bus completely and hence no usage of it is possible anymore.
To fix this issue the clock gating code is completely removed as it was
intentionally meant to enable clock gating on the SMB_CLK line and not
the clock gating on the PCIe interface of the SMBus controller.
This issue is known already and was discussed on the mailinglist:
[coreboot] BDX-DE PCI init fail
https://mail.coreboot.org/pipermail/coreboot/2018-January/085908.html
TEST=Boot mc_bdx1 with microcode version M1050663_07000012.
Change-Id: Icb86f4516f8a6e72552a44618737e682b0fdef33
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/25652
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There wasn't previously a way for Stoney platforms to run mainboard
specific code in romstage. This adds an early call for configuration
and passes along whether the system is currently resuming from S3.
BUG=b:77921345
TEST=Build, verify that weak function implementation gets called.
Change-Id: Id94855e1084814ec37956e603cd093d70f01a559
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/25635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
dimm_info.serial had a strange contract. The SPD spec defines a 4 byte
serial number. dimm_info.serial required a 4 character ascii string with
a null terminator.
This change makes the serial field so it matches the SPD spec.
smbios.c will then translate the byte array into hex and set it on the
smbios table.
There were only two callers that set the serial number:
* haswell/raminit.c: already does a memcpy(serial, spd->serial, 4), so
it already matches the new contract.
* amd_late_init.c: Previously copied the last 4 characters. Requires
decoding the serial number into a byte array.
google/cyan/spd/spd.c: This could be updated to pass the serial number,
but it uses a hard coded spd.bin.
Testing this on grunt, dmidecode now shows the full serial number:
Serial Number: 00000000
BUG=b:65403853
TEST=tested on grunt
Change-Id: Ifc58ad9ea4cdd2abe06a170a39b1f32680e7b299
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/25343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The converter was setting SMBIOS values when dimm_info expects SPD
values.
dmidecode now shows the following:
Memory Device
Array Handle: 0x0000
Error Information Handle: Not Provided
Total Width: 64 bits
Data Width: 64 bits
Size: 8192 MB
Form Factor: SODIMM
Set: None
Locator: Channel-0-DIMM-0
Bank Locator: BANK 0
Type: DDR4
Type Detail: Synchronous
Speed: 933 MT/s
Manufacturer: Hynix/Hyundai
Serial Number: 00000000
Asset Tag: Not Specified
Part Number: HMAA51S6AMR6N-UH
Rank: 1
Configured Clock Speed: 933 MT/s
Minimum Voltage: Unknown
Maximum Voltage: Unknown
Configured Voltage: Unknown
Example debug output:
AGESA TYPE 17 DMI INFO:
Handle: 1
TotalWidth: 64
DataWidth: 64
MemorySize: 8192
DeviceSet: 0
Speed: 1200
ManufacturerIdCode: 44416
Attributes: 1
ExtSize: 0
ConfigSpeed: 933
MemoryType: 0x1a
FormFactor: 0xd
DeviceLocator: DIMM 0
BankLocator: CHANNEL A
SerialNumber(8): ' 00000000'
PartNumber(20): 'HMAA51S6AMR6N-UH '
CBMEM_ID_MEMINFO:
dimm_size: 8192
ddr_type: 0x1a
ddr_frequency: 933
rank_per_dimm: 1
channel_num: 0
dimm_num: 0
bank_locator: 0
mod_id: 44416
mod_type: 0x4
bus_width: 3
serial: 0x00000000
module_part_number(18): 'HMAA51S6AMR6N-UH '
The serial number we get from AGESA (at least on my
board) is always 00000000. I'm assuming this is because the SPD info is
compiled in.
`mosys memory spd print all` is still failing though. I will look into
that next.
BUG=b:65403853
BRANCH=dimm-info
TEST=Test output above
Change-Id: I076bc3f965f81a9374c8976da48c7fdce014dc0c
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/25304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Relocate setting the temp range MTRR, for the SPI flash device, to
after completion of mp_init. The mp_init functionality mirrors the
BSP's exact MTRR settings into the AP cores. The ranges need to be
the correct calculated values and not some temporary setting.
This solves an MTRR sync issue on APUs with more than two cores,
i.e. more than a single compute-unit. MTRRs within a CU are shared
so the AP always stays in sync.
BUG=b:77457944
TEST=run on Kahlee
Change-Id: Idc4cccdf721e252bc87d6cba62a3406a9f19b940
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/25575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
To avoid rounding errors with the current data types, the formula in
this function must be converted.
Change-Id: I75d05165fd9e5a0992330df00f8665a05d2daeb3
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/25584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This is required for clock parameter settings to take effect.
BUG=b:75306520
BRANCH=None
TEST=On Octopus, used a scope to check that spi_clk fed to tpm is
1 MHz
Change-Id: Icdb617aa4aa944d46b3a56dab88d2008b01dea0d
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/25573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The term MTRR has been misspelled in a few places.
Change-Id: I3e3c11f80de331fa45ae89779f2b8a74a0097c74
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Intel internal graphics preallocated memory size should be selected from
below lists as per Intel FSP UPD header:
0x00:0MB, 0x01:32MB, 0x02:64MB, 0x03:96MB, 0x04:128MB, 0x05:160MB,
0xF0:4MB, 0xF1:8MB, 0xF2:12MB, 0xF3:16MB, 0xF4:20MB, 0xF5:24MB,
0xF6:28MB, 0xF7:32MB, 0xF8:36MB, 0xF9:40MB, 0xFA:44MB, 0xFB:48MB,
0xFC:52MB, 0xFD:56MB, 0xFE:60MB
This patch ensures that coreboot can report the same preallocated
memory range for intel grapics during memory layout calculation.
Note: Today all existing SoCs(except Cannonlake) are supported under intel
common code block design may not need to use any other values than 0x0-0x05
for GFX DSM range. DSM memory ranges between 0xF0-0xF6 are majorly for
early SoC samples and validation requirement. This code block to justify
all differnet possible ranges that FSP may support for a platform.
TEST=Set IgdDvmt50PreAlloc UPD with different ranges between 4MB-60MB
and coreboot could able to calculate GFX DSM range accordingly.
Change-Id: I99735e9a2ee57626bd9d7258e700f7f39ef02e58
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/25562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
On APL and GLK the i2c blocks use 133MHz input clock, but the
SPI blocks use a 100MHz input clock. Fix this so that the proper
target frequencies can be hit on the SPI controllers.
BUG=b:75306520
Change-Id: Iec36579894fa4633ac8d1035e6e7afec01af755f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Correct Cannonlake I2C clock frequency to 133Mhz that will match the
silicon, Cannonlake have I2C clock force to 133Mhz.
BUG=b:75306520
Change-Id: Iaab8851bb00cf27876d4068167a283ed79a28b2d
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/25610
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Apparently Intel had decided to use different clock speeds for
some of its IP blocks in some of its designs. The i2c designware driver
has already been moved into common code allowing for its own Kconfig
value. That currently leaves SPI (UART isn't using the clock currently).
Therefore, remove SOC_INTEL_COMMON_LPSS_CLOCK_MHZ and add
SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ to allow for the different clock
speeds present in the system for the various IP blocks.
BUG=b:75306520
Change-Id: I6cb8c2de0ff446b6006bc37645fca64f2b70bf17
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25608
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As part of moving AGESA calls from bootblock to romstage, create
infrastructure to pass a pointer to the AP cores, so they can jump directly
to romstage.
BUG=b:74236170
TEST=Build and boot grunt, actual test will be performed at a later patch.
Change-Id: If716d1c1970746f2ad90ef71ae9062c99f219897
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
As part of moving AGESA calls from bootblock to romstage, callback function
AGESA_HALT_THIS_AP must be available at romstage.
BUG=b:74236170
TEST=Build and boot grunt, actual test will be performed at a later patch.
Change-Id: I0992b2de5856881c19191ec4f637168727686524
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25527
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
MONITOR/MWAIT had an irremediable hardware bug for Apollolake.
This has been fixed for GLK. Therefore, make MONITOR/MWAIT based
C-states the default for GLK and disable IO-Redirection based
C-states used for Apollolake.
Tested on GLK w/kernel 4.14.27 using turbostat to observe C-state
residencies with and without load.
Tested for S0ix entry and exit using:
"echo freeze > /sys/power/state" and "suspend_stress_test -c 500".
BUG=b:77639897
Change-Id: If648c25a9b26c04b278dce4af241d439790288ca
Signed-off-by: Cole Nelson <colex.nelson@intel.com>
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/19718
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
