pmc_prev_sleep_state() isn't handling the case where acpi_sleep_from_pm1()
returns ACPI_S4. Pass that value along so it can get set as a
prev_sleep_state. Without this, consumers see prev_sleep_state as 0
and always treat resume as a cold boot. With this, consumers can
correctly do behavior specific to S4 resume, like skipping the
disconnect IPC command to the PMC on Alderlake systems.
BUG=b:230031158
TEST=Resume from S4 on Primus4es
Signed-off-by: Evan Green <evgreen@chromium.org>
Change-Id: I3fb3dc428a749db80293e51a04a2096514a7b689
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Fix power sequence according to datasheet:GL9750S-OIY04 rev1.24.
BUG=b:229181624
TEST=Build and boot to OS in Skyrim. Ensure that the SD Controller
and SD Card are enumerated fine.
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: Iea729d43d10a3f8353b4fe540146d00975f4d422
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The per-file hash for CBFS_VERIFICATION, stored as a CBFS file
attribute, would increase the total RO metadata size by 75% (3796->6656
for corsola). Therefore, in order to make RO metadata cache fit into
CBFS_MCACHE, enlarge it from 8K to 16K.
Adjust the memlayout by decreasing the DRAM_INIT_CODE from 196K to 184K
(only 160K needed for now), and moving VBOOT2_WORK region to L2C. Also
shuffle the regions in SRAM with better comments.
BUG=b:229670703
TEST=emerge-corsola coreboot
TEST=Enabled CBFS_VERIFICATION and booted kingler into kernel
BRANCH=none
Change-Id: I8e07eb9fae1644a0fbfbdc599ca0a0e11bbe54b5
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
MediaTek's bootROM expects a SHA256 of the bootblock data at the end of
bootblock.bin (see util/mtkheader/gen-bl-img.py). To support CBFS
verification (CONFIG_CBFS_VERIFICATION) on MediaTek platforms, we need
to re-generate the hash whenever a file is added to or removed from
CBFS.
BUG=b:229670703
TEST=sudo emerge coreboot-utils
TEST=emerge-corsola coreboot chromeos-bootimage
TEST=Kingler booted with CONFIG_CBFS_VERIFICATION=y
Change-Id: Iaf5900df605899af699b25266e87b5d557c4e830
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63925
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since we can't rely on the MMIO base address in the PSP_ADDR_MSR MSR to
access the PSP mailbox registers, switch to using the SMN mapping of the
PSP mailbox registers. The PSP SMN base address is taken from the amdgpu
driver in the Linux kernel.
BUG=b:229779018
TEST=Mandolin still boots successfully and there are no errors/warnings
about possibly PSP-related things.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9d17e523e9ae8d8e14ecedc37131a81f82351487
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64034
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Functions that are intended to override weak ones defined in the
baseboard should not also be declared weak, otherwise how would
the linker know which copy to keep.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ia2ceee77d00a5baa915fd1f306d76e79aa609e65
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Based on the schematic bernadino 14 adl-p 20220318.pdf to set
GPP_D16 to enable webcam power
BUG=b:230289857
BRANCH=none
TEST=build and notice log kernel v5.10
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: I01c73006d24b00be348655334232bea5eeb312e4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63955
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add entries to the devicetree override for brya0 and enable the Kconfig
to ensure the Chrome OS EC Mux driver is build tested.
BUG=b:208883648
TEST=None
BRANCH=None
Change-Id: Icf841cd32587f6bd98b15747283b0d331f013532
Signed-off-by: Prashant Malani <pmalani@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64007
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Some platforms have retimers which can be configured via the EC. Add a
handle to these retimer devices to the Type C connector device, using
devicetree references.
BUG=b:208883648
TEST=Verify disassembled SSDT on brya.
BRANCH=None
Signed-off-by: Prashant Malani <pmalani@chromium.org>
Change-Id: Ic0480b08c6d6a7562cca57192e49b8ea2a33b51e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This documents the boards that have been removed from the master branch,
and which branch to check out to build or work on them.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Iee25db13e2c1b0b9131fd2032a26ece45aba4f42
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63797
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
This extends and adds various options to the update_submodules script.
Extensions:
- Add help text
- Add all options, but specifically allow a single repo to be specified,
along with a minimum number of changes instead of being fixed at 10.
- Make it a more formal script with main() and functions
- Show changes in commit message, unless there are > 65 commits.
Options:
-c | --changes <#> Specify the minimum number of changes to update a repo
-h | --help Print usage and exit
-R | --repo <dir> Specify a single repo directory to update
-s | --skipsync Assume that repos are already synced
-V | --version Print the version and exit
This does not fix style issues in the original, which will be fixed in
a follow-on commit.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I222103babff7d5f4f8eb02869c598a4e06748a17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Use common ASL defines for POST code handling.
Change-Id: I5b4c11860a8c33e56edaea0f6de378cbaa63a8c5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63989
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move ASL POST code declarations into a common file to avoid redundancy.
Also, provide a dummy implementation when `POST_IO` is not enabled, as
the value of `CONFIG_POST_IO_PORT` can't be used.
Change-Id: I891bd8754f10f16d618e76e1ab88c26164776a50
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Align POST code ASL elements with existing code in newer southbridges.
The main differences are that `NoLock` is changed to `Lock`, and that
names have been changed. The lock type change should not be a problem
because the field is only used once in the _PTS method.
Change-Id: I8aa362007ff98e5b42add6c7908a8f7beac2222b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
To pave the way for future refactoring commits, drop POST code elements
from the debug.asl file. Only msi/ms7721 includes debug.asl and it does
not use any of it anyway.
Change-Id: Icd73e5c1f700fd7e735bed1668f02da8f9a3adf3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
CORE_2_PSP_MSG_38_OFFSET and CORE_2_PSP_MSG_38_FUSE_SPL are only used in
psp_gen2.c, so move them into this file.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I67cc2ff63d1c0322b514521975f3ce0f9b1cf5b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
This fixes the following issues found by the markdown lint tool, mdl:
MD014 Dollar signs used before commands without showing output
MD026 Trailing punctuation in header
MD030 Spaces after list markers
MD031 Fenced code blocks should be surrounded by blank lines
MD040 Fenced code blocks should have a language specified
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I82317f51c003b2c23d64c3cbbcecbf9a39d5d509
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
ADL-S CPU has maximum 3 PCIe interfaces when the x16 link is bifurcated
into two x8 links. ADL-S PCH has up to 28 PCIe Root Ports, 18 CLKOUT and
CLKREQ signals. ADL-S CPUs do not have Thunderbolt.
Based on the Intel DOC #619501 and #619362.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I408c815d5a43c081beb3f84d795c2b863ce33eb2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Add display on and off notifications which call mainboard hooks if
present. This allows to handle some board specific functions in user
absence or presence (when display goes off from inactivity or on from
activity).
TEST=Use Display on/off notification on Clevo NV41 to tell EC about
laptop inactivity. It is necessary to properly handle S0ix entry (stop
the fans and start blinking the power led).
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Change-Id: Ie80f631ecffa74467ab6d6162e552ba977f7e3f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This patch just adds some comments to the recently merged mem_chip_info
struct for communicating memory type information to the payload/OS, to
clarify the expected format in which values are to be written into the
fields.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I2c28b3bdcdb13b7f270fb87a8f06e2cf448cddec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
As recommended on crrev.com/c/3612466 lz4 code is not supposed
to be modified. Since both gcc and clang complain about
functions without explicit void in argument with Wstrict-prototypes,
just disable it instead instead of enabling.
BUG=b:230345382
TEST=llvm tot test
BRANCH=none
Signed-off-by: Manoj Gupta <manojgupta@google.com>
Change-Id: I9f3ae01821447f43b4082598dd618d9f8325dca2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63936
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Per Microsoft's spec for HID over I2C [1], interrupts must be level
triggered. Switch GPIOs and the devicetree config to conform to this.
Touchpad and multitouch gestures were already working, so no behavior
changes are observed in normal use.
[1]: http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx
Change-Id: I485e616ae00e10bc3620ff3fa1fc1e903653c5cc
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
It's useful to know how many attempts were made at polling the status
bit.
BUG=b:228289365
TEST=Boot guybrush
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ifcc79a339707fbaab33e128807d4c0b26aa90108
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63959
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
The previous code required a bit too much effort to read. It also didn't
print out the actual duration.
BUG=b:228289365
TEST=Boot guybrush
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia620e789c5186f2e1d3cf3c548bda00a294d23bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
I find it difficult to constantly decode the registers when reading
them. Let's print out something that's easier to parse.
BUG=b:228289365
TEST=boot guybrush and see status codes printed
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I6c9d98cf43f340cf50e12c93b4c35187de9bb750
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Silently failing makes it hard to debug when something goes wrong.
BUG=b:228289365
TEST=build guybrush
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7423a7011e7656414155386c014a9a0f2fad4abf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63937
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Based on the datasheet, we can safely increase the SPI frequency of
sc7280 to 50 MHz.
BUG=b:190231148
BRANCH=None
TEST=build and boot BIOS with this config on herobrine boards
Change-Id: I84420d7d8ab0cb979fc606fcf05147197bc51c35
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63948
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The MT8186 platform fails to suspend due to premature wakeup by USB.
In MT8186, we use low level latch to keep USB wakeup signal. However,
hardware could latch a wrong signal if it debounces more than one time.
As a result, it would enable wakeup function too early.
To prevent this issue, we do the following modification:
- Delay about 100 us to enable wakeup function in kernel drivers [1].
- To guarantee 100 us is enough, we need to disable the USB debounce by
default in coreboot.
According to section register 0x404 and 0x420 in
"(CODA) MT8169_PERICFG_REG.xls" which is only for MediaTek internal use:
The current default value of debounce register for MT8186 USB IP0 and
IP1 is incorrect. The reason we add in coreboot is that the default
value should be correct when SoC is booting up.
This modification is only for MT8186. The subsequent SoCs will adjust
the wakeup function to correct register value by default.
[1]: 0d8cfeeef3f5 (usb: xhci-mtk: fix random remote wakeup)
TEST=after stress test, not found premature wakeup by USB
BUG=b:228773975
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I296c4491c5959670a39fa8bd6ef987557bbc459f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63858
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Drop struct pspv2_mbox and access the PSP mailbox via their offsets into
PSP MMIO region.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib665d7ae19deae07d6a69c11ba8cf44e45ea4e70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63966
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Don't use unnamed redefinitions of the pspv2_mbox_command union when the
union definition can be used instead.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3757db45272f11bb47e5106ad9054c0a9ca0cd52
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63964
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
The pspv2_mbox struct contained an unnamed union that covered the 32
bits of the command register of the PSP v2 mailbox. Since the pspv2_mbox
struct is mainly used for hardware register accesses and the union part
is mostly used to access the different bits before/after writing/reading
the command register, split this functionality. For the register access
a command field is added to the pspv2_mbox struct instead of the unnamed
union and for accessing the separate bits of the command register a new
named union is added.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If3f00b6fd73c3f749154b77b940e6d5aa385ec49
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63963
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The cmd_response field in the pspv2_mbox struct is the buffer used to
pass data to the PSP and back to the x86 side, so rename it to buffer.
This also aligns the code a bit more with the reference code. Also
rename the wr_mbox_cmd_resp function to wr_mbox_buffer_ptr.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I22c8971b07b3dedcc2e6e50e93c98d69ec7379e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63962
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The pspv[1,2]_mbox struct is only used in psp_gen[1,2].c, so move those
definitions from the common psp_def.h to the specific psp_gen[1,2].c
files. Also fix the struct name in the comment about pspv1_mbox.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0c95e9a6e292b90e0d147c57f59828a9b41e4b82
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63960
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now the bootblock is not limited to 64K so integrating vboot into the
bootblock reduces the binary size. intel/apl is an exception since the
bootblock size is limited to 32K.
Change-Id: I5e02961183b5bcc37365458a3b10342e5bc2b525
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This patch enforces disabling of the CSE device if CSE stays in
SOFT TEMP DISABLE state. The recommendation is to make CSE function
disable to avoid receiving any CSE commands from the OS layer.
BUG=b:228789015
TEST=None
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I77c254195895a93a5606adee8b6f43d8b7100848
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This patch removes redundant DISABLE_HECI1_AT_PRE_BOOT config check for
heci1_disable(), once by caller (from various SoC) and again inside the
callee (heci1_disable) function.
As all callers of heci1_disable() function are doing
DISABLE_HECI1_AT_PRE_BOOT config enabled check, hence, the second check
inside the callee can be dropped.
BUG=b:228789015
TEST=Able to build and boot google/redrix with this change. CSE PCI
device is getting function disabled upon selecting
DISABLE_HECI1_AT_PRE_BOOT from SoC config.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I47d7a9989e355987618d089f79c3340fcf4953ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63821
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This patch decouples HECI disabling interface a.k.a SMM or PCR or PMC
IPC etc. from DISABLE_HECI1_AT_PRE_BOOT kconfig as Intel ME BWG
recommends to disable the CSE PCI device while CSE is in
software temporary disable state.
BUG=b:228789015
TEST=Able to build google/redrix.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I66abc04d5e195515165a77b0166d004f17d029e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Agah USB-C port 0 is non-retimer port and it connects to TCSS port 2.
Bit[5:4] is for TCSS Port 2, so re-configure "TcssAuxOri" to 0x10 and "typec_aux_bias_pads" to 2 to correct the port.
BUG=b:210970640
BRANCH=NONE
TEST=emerge-draco coreboot chromeos-bootimage
Change-Id: I2d26777e850187aee0b676de13dff915474fed7b
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This allows for the option to persist the serial number and other
device-specific information when switching from stock ChromeOS and
upstream coreboot firmware images.
Change-Id: I12711f678259390fe9e31b7ca728344cc2875b0e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Evan Green