GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
38,215 Commits 1 Branch 29 Tags 224 MiB
Commit Graph

38215 Commits

Author SHA1 Message Date
Michael Niewöhner e4031c558d mb/system76/lemp9: gpio: convert the remaining raw pads to macros 
Convert the EC and touchpad interrupt pads from raw to macros. This
was done with intelp2m.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I79d2cca0f300e6daf1c1923a1882e4cc1ffc3c8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43648
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-09-21 23:52:21 +00:00
Jamie Ryu a45e840309 mb/intel/tglrvp: Enable CSE Firmware Lite SKU 
CSE Lite SKU is CSE FW designed for Chrome and this enables CSE Lite SKU
support for tglrvp.

BUG=None
TEST=Build and boot tglrvp with CSE Lite and Consumer SKU

Change-Id: Ia5f3e8125b5e7760a62f7fb46aeeae85c32e2037
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41132
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Shreesh Chhabbi <shreesh.chhabbi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-09-21 18:58:34 +00:00
Elyes HAOUAS dddd1cc691 src/northbridge: Drop unneeded empty lines 
Change-Id: I5f3118f0f855160ed49adc543b6169fccd7520ee
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44593
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-09-21 16:32:10 +00:00
Elyes HAOUAS 7aa3372ce2 soc/amd: Drop unneeded empty lines 
Change-Id: Ib262955a1d26681c796c4b10d2b336f2715824d0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2020-09-21 16:30:40 +00:00
Elyes HAOUAS 690b6bcb49 treewide/Kconfig: Drop unneeded empty lines 
Change-Id: If8aa28a22625b7b2cf9b58958de87ee752f637f6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2020-09-21 16:30:14 +00:00
Elyes HAOUAS 131d9f5190 src/southbridge: Drop unneeded empty lines 
Change-Id: I02aa1e2a9a9061b34b91f832d96123a8595d61b7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2020-09-21 16:29:35 +00:00
Elyes HAOUAS b69bbfe1ef soc/qualcomm: Drop unneeded empty lines 
Change-Id: If76502ff91896959ef171c192b4fc138dff18fc6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2020-09-21 16:27:16 +00:00
Elyes HAOUAS f91bcb310b src/security: Drop unneeded empty lines 
Change-Id: Icb6057ac73fcc038981ef95a648420ac00b3c106
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2020-09-21 16:26:17 +00:00
Elyes HAOUAS 4b7f3151a8 mb/intel: Drop unneeded empty lines 
Change-Id: I3fdc521d30155c4275c336afe03244311f584e71
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44617
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-09-21 16:24:45 +00:00
Elyes HAOUAS 3ff7bcf10e payloads: Drop unneeded empty lines 
Change-Id: I6faeb7c783052edc4217d2d301dbb905e1fc6a19
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2020-09-21 16:20:57 +00:00
Elyes HAOUAS 99e0c7ddc1 src/cpu: Drop unneeded empty lines 
Change-Id: I116b15c83fcc5d69d3f80a2e6cf0fb085064d9a6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2020-09-21 16:20:30 +00:00
Elyes HAOUAS b6265139c7 soc/rockchip: Drop unneeded empty lines 
Change-Id: I6932580a373608d3d2fa5d844efdc7ffbc577d1f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2020-09-21 16:18:49 +00:00
Elyes HAOUAS 0c2724c844 soc/samsung: Drop unneeded empty lines 
Change-Id: Ib2843c40de8e4607b8b9d665761a689227878bc0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2020-09-21 16:18:07 +00:00
Subrata Banik 0180e43f3d soc/intel/common: Keep common non-IP code block inside basecode 
Expand the scope of 'common/basecode' directory to keep common
non-IP code block (like acpi, power limit).

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I7a2778704016b501eb20382d4603295cec8375d5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45522
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-09-21 16:16:46 +00:00
Elyes HAOUAS 2854f40668 src/soc/intel: Drop unneeded empty lines 
Change-Id: Id93aab5630e928ee4d7e957801e15a4cc8739fae
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44594
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-09-21 16:15:25 +00:00
Elyes HAOUAS ee65079c96 mb/msi: Drop unneeded empty lines 
Change-Id: Id51da519582856b1856479b641599e14f79fd1ad
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2020-09-21 16:06:36 +00:00
Elyes HAOUAS 5548ce5896 mb/protectli: Drop unneeded empty lines 
Change-Id: I051dc318c5f881bc58b1a4460faad6af22049b39
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2020-09-21 16:06:13 +00:00
Elyes HAOUAS 41376c6d1a mb/scaleway: Drop unneeded empty lines 
Change-Id: If56031a7b39d1c1b3ebf6d19376f19ec8c7cef1a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45253
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2020-09-21 16:05:49 +00:00
Elyes HAOUAS d1b2699685 mb/sifive: Drop unneeded empty lines 
Change-Id: I5274bc7206ba333d06f5defc35fdede540a7148f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2020-09-21 16:05:04 +00:00
Elyes HAOUAS fbc36dc4b0 mb/roda/rk886ex: Drop unneeded empty lines 
Change-Id: I229d3995983a05cdd7fef1609a65f31b9f8f2969
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2020-09-21 16:04:18 +00:00
Elyes HAOUAS d0e18ff0cb mb/dell: Drop unneeded empty lines 
Change-Id: I3d0ca401cf5268962bcd9074f94c37724cc0a836
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2020-09-21 16:04:03 +00:00
Elyes HAOUAS 88b9738fa2 mb/supermicro: Drop unneeded empty lines 
Change-Id: I1aae6c0291ad329c8cc125cd18ba22dfd63d979b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2020-09-21 16:03:36 +00:00
Subrata Banik 8f7a2482ae drivers/intel/fsp2_0: Add CONFIG_FSP_STATUS_GLOBAL_RESET 
Add CONFIG_FSP_STATUS_GLOBAL_RESET Kconfig to get correct FSP global
reset type from respective SoC Kconfig.
Supported value:  0x40000003-0x40000008, These are defined in FSP EAS
v2.0 section 11.2.2 - OEM Status Code
Unsupported value: 0xFFFFFFFF

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: Idc04eb3a931d2d353808d02e62bd436b363600d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
 2020-09-21 16:03:28 +00:00
Subrata Banik 77cc3267fc soc/intel: Refactor do_global_reset() function 
List of changes:
1. Rename do_global_reset() to force_global_reset()
2. Make force_global_reset() function static
3. Implement force_global_reset() into common/reset.c to avoid
dedicated SoC implementation
4. Remove redundant force_global_reset() implementation from
dedicated SoC
5. Make direct call to global_reset() from cse_lite.c
7. Drop CONFIG_HAVE_CF9_RESET_PREPARE Kconfig from APL SoC due
to common reset (soc/intel/common/reset.c) code migration
8. Remove unused function send_global_reset() from SKL me.c due
to common reset code migration
9. Delete heci.c from APL SoC as unused

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I1c5dc8d5606ef28ffaed4a64d90f470ae1ffc2a6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
 2020-09-21 16:03:16 +00:00
Elyes HAOUAS e49ce2604f mb/asus/am1i-a: Drop unneeded empty lines 
Change-Id: Ib56b56c05df154522172bff2e6746280286a481f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2020-09-21 16:03:01 +00:00
Elyes HAOUAS 7df9cd5ee2 mb/hp/z220_sff_workstation: Add empty lines after "SPDX" 
Change-Id: Ief8df9ef0d6ecb675680aa5120738f5099034139
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45245
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-09-21 16:02:14 +00:00
Elyes HAOUAS 2fa5c020a4 mb/gizmosphere: Drop unneeded empty lines 
Change-Id: If631055dffa79e7562d6238f6e0b88ad1c7d38b4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45244
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2020-09-21 16:01:47 +00:00
Elyes HAOUAS 4865983a70 mb/jetway: Drop unneeded empty lines 
Change-Id: Id9837eda69d725539a82b3c98f63a57240051c5b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2020-09-21 16:01:23 +00:00
Elyes HAOUAS fc15ca44f4 mb/elmex: Drop unneeded empty lines 
Change-Id: I6dc9f153270fe501d53ab44c902401893aacf1b9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2020-09-21 16:00:57 +00:00
Elyes HAOUAS c2423e498d mb/pcengines: Drop unneeded empty lines 
Change-Id: Ica6a885721b3a88814973d1cf086d2d4bc3d922d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2020-09-21 16:00:15 +00:00
Elyes HAOUAS d32b44645f mb/asrock: Drop unneeded empty lines 
Change-Id: I035b66e749e9a3e1bde13c8ed7ceafeb1edbbfa4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2020-09-21 15:59:53 +00:00
Elyes HAOUAS e2a26a647b mb/lippert: Drop unneeded empty lines 
Change-Id: I82c2527039a9bd278e57cfbd88a009ee5ba03e1d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2020-09-21 15:59:09 +00:00
Elyes HAOUAS a58d7020fd mb/samsung: Drop unneeded empty lines 
Change-Id: I76d5292871c1578f9d27d46b7a2c485a14c3017b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2020-09-21 15:58:29 +00:00
Elyes HAOUAS 5275b60ebd mb/amd: Drop unneeded empty lines 
Change-Id: I2ceeae8dd25663203549a87b4e9524a631fa92f8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2020-09-21 15:58:10 +00:00
Elyes HAOUAS 7c9ad7efdb mb/lenovo: Drop unneeded empty lines 
Change-Id: Icad51da75d99dd541f8f2621a16eae13a596d264
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2020-09-21 15:57:10 +00:00
Elyes HAOUAS f219cd8342 src/device: Drop unneeded empty lines 
Change-Id: Ief990b4174d13b3472ac75a042ae8d878640dda3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2020-09-21 15:56:17 +00:00
Elyes HAOUAS 0dd92f8222 src/commonlib: Drop unneeded empty lines 
Change-Id: Ib3db132aa649b6895f41290df049f87a9f36dc52
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2020-09-21 15:53:25 +00:00
Elyes HAOUAS 0938be9269 src/console: Drop unneeded empty lines 
Change-Id: I94f92ba4385285496ede0c33fc25addd6c4bfeae
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2020-09-21 15:52:42 +00:00
Elyes HAOUAS d161a2fafd src/drivers: Drop unneeded empty lines 
Change-Id: I202e5d285612b9bf237b588ea3c006187623fdc3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2020-09-21 15:51:52 +00:00
Michael Niewöhner 490546f191 soc/intel: rename get_prmrr_size 
get_prmrr_size does not return the actual PRMRR size but a valid PRMRR
size with repect to the users choice in Kconfig. Thus, rename it from
`get_prmrr_size` to `get_valid_prmrr_size` to avoid confusion about what
it does.

Also fix the broken comment in cpulib.h.

Change-Id: Id243be50acb741f2c3118ddde082743d08983a53
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2020-09-21 15:51:01 +00:00
Michael Niewöhner 1dac89633e soc/intel/common/block/sgx: drop no-ops from PRMRR Kconfig 
Since PRMRR size can only be set when SGX is enabled and since SGX
depends on PRMRR size >= 32MB, any lower setting (including "Disabled")
is invalid. Drop these settings.

Change-Id: If7a19c7223a0de2e03b7df9184cddf7c9fc87a68
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2020-09-21 15:50:52 +00:00
Michael Niewöhner 028c0b640f soc/intel/common/block/sgx: make PRMRR size setting depend on SGX 
PRMRR size shall only be set when SGX is enabled. Make PRMRR depend on
SGX enablement in Kconfig.

Change-Id: I551942fd9cb8e7123d00dbd752abffe24788148c
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2020-09-21 15:50:43 +00:00
Karthikeyan Ramasubramanian cc05e311a2 soc/intel/common/cse_lite: Defer cse_fw_sync for JSL 
Defer cse_fw_sync to BS_DEV_RESOURCES boot state so that MRC training
data can be cached before CSE FW Sync and a second MRC training can be
avoided.

BUG=b:168850641
TEST=Build and boot the waddledoo board to OS. Ensure that the memory
training is performed only once.

Change-Id: I0ef5693eaa6ed34dc08c94e5db153f4295578f5f
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
 2020-09-21 15:49:16 +00:00
Edward O'Callaghan be710767fd mb/google/hatch/Kconfig: Make cse override depend on lite sku 
Lets have the Kconfig depend more directly on CSE_LITE_SKU
than indirectly on the PUFF baseboard.

BUG=none
BRANCH=puff
TEST=builds

Change-Id: I8784b506629ceedc2770dc86d8caabbef5eb8a1d
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45523
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-09-21 15:08:34 +00:00
Michael Niewöhner 30c5d21891 soc/intel/skylake: acpi: drop HWP's dependency on EIST 
Enhanced Intel SpeedStep Technology (EIST) and Intel Speed Shift
Technology (ISST) - also know as HWP - are two independent mechanisms
for controlling voltage and frequency based on performance hints.

When HWP is enabled, it overrides the software-based EIST. It does not
depend on EIST, though, but can be enabled on its own.

Break up that currently existing dependency in ACPI generation code.

It was tested that HWP can be enabled and gets used by the Linux pstate
cpufreq driver. With HWP disabled, the frequency does not decrease, even
not in powersave mode. After enabling HWP the frequency changed in
relation to the current workload. (Test device: Acer ES1-572)

Change-Id: I93d888ddce7b54e91b54e5b4fdd4d9cf16630eda
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44137
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-09-21 14:51:00 +00:00
Eric Lai fa0080d187 mb/google/octopus: Clean up LTE power off function 
All octopus board share the same power off sequence.
Move to smihandler.c instead variant.c.

BUG=b:168075958
BRANCH=octopus
TEST=build image and verify on the DUT with LTE DB.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I2be5a656fb42fff99c56d21aaa73ed9140caad37
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45436
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-09-21 12:41:57 +00:00
Angel Pons 3da27ab681 nb/intel/sandybridge: Check ME status only once 
The pre-RAM CBMEM console is tiny. Do not fill it with largely redundant
information, when we could instead store more useful raminit debug logs.

Change-Id: I3a93fdeb67b0557e876f78b12241b70933ad324d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45499
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2020-09-21 08:14:00 +00:00
Angel Pons 035096c6f0 nb/intel/sandybridge: Simplify SPD validity check 
Instead of decoding the entire SPD, just check the memory type directly.

Tested on Asus P8Z77-V LX2, still boots.

Change-Id: I3afa0ca5aae984895e50fe7b3792192fdd2ee6c6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2020-09-21 08:13:48 +00:00
Iru Cai 8c6d1610d1 util/autoport: Always output quoted Kconfig string 
Change-Id: I2076af9c70b626673a83af9abf464d376cda711b
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-09-21 08:13:08 +00:00
Jamie Ryu 5a401ae262 mb/intel/tglrvp: Enable HECI interface 
This is to enable Intel ME communication interface HECI1 by
devicetree for PAVP with CSE Lite.
PAVP feature is enabled with CSE Lite SKU for Chrome and HECI1 interface
is required between kernel and CSE Lite.

BUG=None
TEST=Build and boot tglrvp. Run lspci and check pcie device
     00:16.0 Communication controller: Intel Corporation Device a0e0

Change-Id: I23117fa96503942e6a72765dd3fd1cc762e3f705
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-09-21 08:12:33 +00:00