Commit Graph

33643 Commits

Author SHA1 Message Date
Felix Held 0c70b4ac11 soc/amd/common/psp: add Kconfig description to interface version
BUG=b:153677737

Change-Id: I5b017dfc92563ec4f0a2edb24416d6b65587d9a3
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40361
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-15 12:23:35 +00:00
Felix Held 1ad73926f2 soc/amd/common/block/psp: move psp_load_named_blob to psp_gen1.c
This function is only needed and valid for the 1st generation PSP
interface used on stoneyridge.

BUG=b:153677737

Change-Id: Ia1be09c32271fe9480a0acbe324c4a45d8620882
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-15 12:23:19 +00:00
Edward O'Callaghan 609b7fb303 mb/google/puff: Fix up WLAN_OFF gpio configuration
BUG=b:152927525
BRANCH=none
TEST=builds

Change-Id: I691377624c870eb0fc6f7e84a4b9cd50b7b09654
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
2020-04-15 10:17:26 +00:00
Arthur Heymans b894ad5233 mb/lenovo/x60: Add vboot support
It's relatively slow to boot. It takes 1.5s to get to the payload.
In timestamps there are entries related to TPM, which are somewhat
weird given that the TPM is not enabled on this device (buggy).

TESTED: boot X60, with CONFIG_H8_FN_KEY_AS_VBOOT_RECOVERY_SW=y you
can force the recovery bootpath.

Change-Id: Ia9666194e98b7d23b97eaff08e6177684e35eca7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-15 10:06:58 +00:00
Edward O'Callaghan 4f176913c1 mainboard/puff: Tune ALC5682I rise_fall times on i2c
Tunes the headphone amp i2c with measured signal shape.

BUG=b:147192377
BRANCH=none
TEST=builds and measured i2c frequency below 400khz

Change-Id: I60f73bcf60ed140f595c953be371b982a63f7b95
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38459
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-04-15 02:35:22 +00:00
Julius Werner ef43711aad trogdor: Add third RAM_CODE pin
We decided to add a third RAM_CODE pin to the Trogdor family for devices
after rev1. This patch adds support to read it. Since the newly used pin
was previously unconnected (not pulled down) on rev1, this will change
the RAM_CODE result for previous versions (and actually make it
undetermined until we enable tri-state). But since we're not actually
using RAM_CODE for anything yet, and since those are development
revisions that will eventually be discontinued, this should be fine.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I9b52982f17646a305b1a3e2c7d37606a7c38d0c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philip Chen <philipchen@google.com>
2020-04-14 21:32:57 +00:00
Seunghwan Kim aee0baf069 mb/google/nightfury: Update tdp_pl1_override value
Update tdp_pl1_override value to 15W for CML-U based nightfury platform.

BUG=None
BRANCH=firmware-hatch-12672.B
TEST=Built

Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Change-Id: Ib0155b961b9d304bed2e9456c4964ebd598af4dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-04-14 10:10:04 +00:00
John Zhao 17277ff658 soc/intel/tigerlake: Fix TCSS TBT PCIE root ports scope type
TCSS TBT PCIE root ports scope type was mistakenly set to PCI_ENDPOINT.
Fix the scope type to be PCI_SUB.

BUG=b:141609884
TEST=Booted to kernel and verified no TBT PCIE root ports scope
type mismatch error in kernel log.

Change-Id: I844e7e9583992be496223fb51f24c5aa24fc7d21
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-04-14 10:09:27 +00:00
Eric Lai 72d9366721 mb/google/deltaur: Enable Melfas touch screen for Deltan
Reference Drallion to add device tree for Melfas touch screen.

BUG=b:152924290

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I7b0a42119891c6c2d5978d7f33eefffa2d62df76
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-04-14 10:08:48 +00:00
Julia Tsai 9e0dd9af47 mb/google/octopus/variants/lick: Disable xHCI compliance mode
Since the first LFPS timeout causes xHCI to enter compliance
mode, the SS hub cannot be enumerated. The resolution is to
disable xHCI compliance mode.

BRANCH=octopus
BUG=b:153782196
TEST=Verified usb operation successfully.

Signed-off-by: Julia Tsai <julia.tsai@lcfc.corp-partner.google.com>
Change-Id: If0bf68c8cf0a2a3b857395b6b82e46cc384ba65c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39874
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-14 10:08:37 +00:00
Dtrain Hsu afc593d99c mb/google/dedede: Enable ELAN touchscreen for Waddledoo
Add ELAN EKTH6918 USI touchscreen support.

BUG=b:152936745
TEST="emerge-dedede coreboot chromeos-bootimage", build successful.

Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I030c7d7e76a9705be06fe907c4ac279e247cb163
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-04-14 10:07:58 +00:00
Dtrain Hsu 3fe5f2cfa4 mb/google/dedede: Enable SIS touchscreen for Waddledoo
Add SiS9813 USI touchscreen support.

BUG=b:152936541
TEST="emerge-dedede coreboot chromeos-bootimage", build successful.

Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Id04c46c763fdf68418bf2e97be4c8bb6bb73c749
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40250
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-14 10:07:50 +00:00
Subrata Banik 53e82f67ea mb/intel/{jasperlake_rvp, tglrvp}: Remove unused files
This patch removes unused "spd_util.c" files from mainboard
directory.

Change-Id: Ibd011be578fa256afb61796d5ceeea073e852fe9
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2020-04-14 10:06:19 +00:00
Wonkyu Kim 3ba64ca3d1 soc/intel/tigerlake: Implement CHIPSET_LOCKDOWN
BUG=b:151161585
BRANCH=none
TEST=build and boot ripto/volteer and check FSP logs for lockdown
parameters

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I63cec8a718285f424914e426d0399ed821588dfd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39710
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-14 10:05:50 +00:00
Paul Menzel aecbe7a988 mb/google/hatch: Use tabs for alignment
Change-Id: I38d429245810f64a03253b5076391af843f8d0de
Fixes: e2ac5b7a36 ("mb/google/hatch/variants: Add DPTF based Fan control")
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-14 10:05:14 +00:00
Paul Menzel 71e2b2903a mb/google/poppy/variants/nami: Use tabs for alignment
Change-Id: Ia707295c55ce2e18eb8970506be10b7b0f3fbc39
Fixes: b77cbbe1b0 ("mb/google/poppy/variants/nami: Update DPTF table")
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-14 10:05:02 +00:00
Paul Menzel 0fdd9fd2aa mb/ocp/tiogapass: Add missing spaces around operators
Change-Id: I8930e96e5f2c45b8658dc4dfe1ab57d573e7b26f
Fixes: b75bcc978a ("mb/ocp/tiogapass: Properly configure early serial output")
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
2020-04-14 10:04:35 +00:00
Arthur Heymans 895c77f361 Documentation/vboot: Drop deprecated options from example
4K keys are now default.

Change-Id: I16599d0e8b874f9e8a56100fea06d6e4f94a5c00
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-14 10:04:10 +00:00
Felix Held a6b887e017 src/Kconfig: enable USE_BLOBS by default
To provide sane defaults for most of the user base, this patch switches
on the USE_BLOBS option by default. Since it only changes the default,
this behaviour can still be easily disabled.

With this abuild doesn't have to select USE_BLOBS any more, so what
abuild tests becomes the coreboot default again.

Change-Id: Ia0632b9ae7a1f212a8640b3faec2695d17d238c5
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-14 10:03:55 +00:00
Jonathan A. Kollasch 3e4f7a39f8 mainboard: add Supermicro X9SCL/X9SCM
Boots to Linux.

Works:
 - CPU (Core i3-2120 tested)
 - Memory (one 1GB 1Rx8 PC3-10600E module tested)
 - Slots 4, 6, 7

To fix/improve:
 - SuperIO hardware monitor setup for PECI and fan control
 - SuperIO ASL in DSDT (e.g. UART Devices)
 - PEG PCIe lanes (should show x8 max width instead of x16 on 0:1.0 for Slot 7)

Untested:
 - IPMI where BMC is fully implemented (X9SC[LM](+)-F variants)
 - GbE on X9SCL+-F (where there are two 82574L instead of one)
 - Slot 5 (x4 on 0:06.0) (only applicable to X9SCM variants)

Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Change-Id: I985db89d67de21bbafbdc34d7044496434a6eb17
Depends-On: I5b7599746195cfa996a48320404a8dbe6820483a, I1206746332c9939a78b67e7b48d3098bdef8a2ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38346
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-14 10:02:24 +00:00
Patrick Rudolph dd662870dd nb/intel/sandybridge/raminit: Add ECC support
Add ECC support for native raminit on SandyBridge/IvyBridge.

Change-Id: I1206746332c9939a78b67e7b48d3098bdef8a2ed
Depends-On: I5b7599746195cfa996a48320404a8dbe6820483a
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/22215
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-14 10:02:14 +00:00
Patrick Rudolph 05d4bf7ea7 nb/intel/sandybridge/raminit: Add ECC detection support
Add support for detection ECC capability and forced ECC mode.
Print the ECC mode in verbose debugging mode.

Change-Id: I5b7599746195cfa996a48320404a8dbe6820483a
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/22214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-14 10:02:07 +00:00
Arthur Heymans 48d5b8d463 nb/intel/i945: Add vboot support
Change-Id: I749be0044be04b044ff82e96aff8093f4b0d295e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-14 09:57:14 +00:00
Marx Wang abc17d10d6 soc/intel/apollolake: Disable XHCI LFPS power management
Provide the option to disable XHCI LFPS power management.
If the option is set in the devicetree, the bits[7:4] in
XHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated
from default 9 to 0.

BUG=b:146768983
BRANCH=None
TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash
     the image to the device. Run following command to check if
     bits[7:4] is set 0:
     >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"

Signed-off-by: Marx Wang <marx.wang@intel.com>
Change-Id: Ic603e3b919d8b443c6ede8bb5e46e2de07fcb856
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-14 09:57:03 +00:00
Elyes HAOUAS efc3d04af2 src/mainboard: Use 'const' to set pnp_devfn_t statically
Change-Id: I50ac6914fadc02491df2eccb437eada89fd12b82
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-04-14 09:56:33 +00:00
Marco Chen 4f771fe98b soc/intel/jasperlake: Allow mainboard to override DRAM part number
In order to support mainboards that do not store DRAM part number in
the traditional way i.e. within the CBFS SPD for soldered memory, this
change provides a runtime callback to allow mainboards to provide DRAM
part number from a custom location e.g. external EEPROM on dedede.

For other boards it should be a NOP since the weak implementation of
mainboard_get_dram_part_num does nothing.

BUG=b:152019429

Change-Id: I7ba635f5504ba288308d7d7a4935f405f289aa8d
Signed-off-by: Marco Chen <marcochen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-04-14 09:56:18 +00:00
Marcello Sylvester Bauer dd1a0acc4a mb/lenovo: Add additional FMAPs on 8MiB devices
* Add FMAP for measured boot only, with a single RO partition.
* Add FMAP for measured boot only, with a single RO partition
  but where the ME has been shrunken.

Tested on X220 using VBOOT+measured boot:
* Used patched IFD and ME, boots into OS

Change-Id: I04c1add13198444638c669deec1e05159b1a09c9
Signed-off-by: Marcello Sylvester Bauer <sylv@sylv.io>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
2020-04-14 09:55:58 +00:00
Arthur Heymans 15161d9284 4.12 release notes: Add some explanation behind deprecations
Some features are made mandatory, meaning that some platforms have
been dropped from master. This also explains that further development
on these popular platforms can happen on the 4.11 branch.

TODO is this really the right place or is it too technical for release
notes?

Change-Id: I95e01c301e7db6f81ef88a89d709ebab35c9ccfb
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2020-04-14 09:55:47 +00:00
Krishna Prasad Bhat 26ea43a5c2 soc/intel/icelake: Add function to dump ME firmware status information
Add a function to dump ME Host Firmware Status registers.

BUG=None
BRANCH=None
TEST=Build and boot iclrvp.

Change-Id: I9430189665c94decb2e64680d28a7390ee6e912c
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2020-04-14 09:55:32 +00:00
Krishna Prasad Bhat 633a36af58 soc/intel/tigerlake: Add function to dump ME firmware status information
Add a function to dump ME Host Firmware Status registers.

In tigerlake, Manufacturing mode is “No” if below conditions are satisfied, indicating
end of manufacturing. Otherwise, manufacturing mode is "Yes".
1. Intel fuses are programmed (Indicated by HFSTS6[30] bit set)
2. The SPI flash descriptor region is locked. (Indicated by HFSTS1[4] cleared)

BUG=None
BRANCH=None
TEST=Build and boot tglrvp.

Change-Id: I831a51f9f482425bd3b97ef1d2404b1d06844d07
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2020-04-14 09:55:23 +00:00
Krishna Prasad Bhat d0c0fd736f soc/intel/{icl,tgl}: Make use of print_me_fw_version() from CSE lib
Make use of print_me_fw_version() which is defined in the CSE lib to
print ME firmware version information for icl,tgl.

BUG=None
BRANCH=None
TEST=Build and boot iclrvp, tglrvp boards.

Change-Id: Ief75403c490eee499a84372e54fa38ea3016cc11
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-04-14 09:54:50 +00:00
Wonkyu Kim 53ac68e551 mb/intel/tglrvp : Enable RP LTR
BUG=b:151166040
TEST= build and boot volteer and check LTR and AER value
from FSP log

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I8ab7667d788563ffcb9287a64254590ef9bea5d8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40269
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-14 09:52:33 +00:00
Wonkyu Kim e3bf8ba2d8 mb/google/volteer: Enable RP LTR setting
BUG=b:151166040
TEST= build and boot volteer and check LTR and AER value
from FSP log

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ibbf55e6a08ff5e8f358325bb8e9f1487cc982f95
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40268
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-14 09:52:25 +00:00
Wonkyu Kim 5943117647 soc/intel/tigerlake: Configure RP setting
Add LTR and AER configuration to the root ports config.

BUG=b:151166040
TEST= build and boot volteer and check LTR and AER value
from FSP log

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I668f2e5fea15019a9e5ae06fb4d55fa2aea69e8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40262
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-14 09:52:16 +00:00
Nick Vaccaro ba41ee1f0a mb/google/volteer: fix incorrect fields in SPDs
According to Intel Document #616599,
  1) SPD byte offset #5 for Tiger Lake should be "0x21" (16 rows, 10
     columns)
  2) SPD byte offset #13 for Tiger Lake should be "0x01" (1 channel
     x16)

This change fixes those two values in the existing SPD files for
Volteer, and zero's byte 9 (bytes 8-11 should be zero'd out in a
generic SPD).

BUG=b:152827558
TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot
Volteer to kernel.

Change-Id: Ice6a32a2b3827cf99d8e109731ffd9efabf68de1
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-04-14 09:50:41 +00:00
Nick Vaccaro 5926fb5035 mb/google/volteer: fix CROS_GPIO_WP_AH export
Fix GPIO_PCH_WP (GPP_B11) to associate GPP_PCH_WP with community
zero instead of community 1.

BUG=b:152876091
TEST="emerge-volteer coreboot chromeos-bootimage", flash, boot to
and log into Volteer kernel, execute "wp enable" in H1 console,
execute "crossystem" at kernel prompt and verify that "wpsw_cur"
shows as being "1", Execute "wp disable" in H1 console, execute
"crossystem" at kernel prompt and verify "wpsw_cur" is 0.

Change-Id: I082154efd72459ec54999ed7c7bb7420a38f7b6e
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-04-14 09:50:32 +00:00
dalao 56a25a98db mainboard/lenovo: Use the original hardware ids for keyboard/pointing
Currently coreboot is using the compatible ID PNP0303 for all keyboards
and PNP0F13 for all pointing devices, which causes some problems. On
Windows, the touchpad driver can't be automatically matched and
installed through Windows Update. On Linux, there are some strange
issues. So it's better to use the original hardware IDs for each model.
The hardware IDs for the following models can be found By searching for
dmesg logs on vendor BIOS:

T60: https://mail.gnome.org/archives/networkmanager-list/2012-January/msg00110.html
Keyboard: PNP0303 Pointing: IBM0057

R60: https://openbenchmarking.org/system/1202279-AR-COMPRESS715/Lenovo%20R60/dmesg
Keyboard: PNP0303 Pointing: IBM0057

X60: https://github.com/pavelmachek/missy/blob/master/db/notebook/lenovo/thinkpad/x60/pavel/2018.3648803539788/dmesg.out
Keyboard: PNP0303 Pointing: IBM3780

X200: https://ubuntuforums.org/showthread.php?t=1833248&page=2
Keyboard: LEN0010 Pointing: IBM3780

T400: https://github.com/heradon/libreboot-fork/blob/master/docs/future/dumps/logs-t400-bios2.02-ec1.01/dmesg.log
Keyboard: LEN0010 Pointing: IBM3780

T510: https://bbs.archlinux.org/viewtopic.php?id=120287
Keyboard: PNP0303 Pointing: LEN0015

T410: https://forum.ubuntuusers.de/topic/kein-sound-109/
Keyboard: PNP0303 Pointing: LEN0015

T420: https://linux-hardware.org/index.php?probe=e6a094ade5&log=dmesg
Keyboard: PNP0303 Pointing: LEN0015

T420s: https://bbs.archlinux.org/viewtopic.php?id=191510
Keyboard: PNP0303 Pointing: LEN0015

T520: https://bbs.archlinux.org/viewtopic.php?id=195636
Keyboard: PNP0303 Pointing: LEN0015

W520: https://linux-hardware.org/index.php?probe=9306cac54c&log=dmesg
Keyboard: PNP0303 Pointing: LEN0015

T430: https://github.com/farjump/fwtr/blob/master/lenovo/thinkpad-t430/2347ds2/lenovo/g1et73ww-2.09/fwts/20160218_174223/dmesg.log
Keyboard: PNP0303 Pointing: LEN0015

T430s: https://linux-hardware.org/index.php?probe=01545dc8fb&log=dmesg
Keyboard: PNP0303 Pointing: LEN0015

T530: https://forums.fedoraforum.org/showthread.php?316640-Fedora-27-High-CPU
Keyboard: LEN0071 Pointing: LEN0015

W530: https://bugs.freedesktop.org/attachment.cgi?id=115557
Keyboard: LEN0071 Pointing: LEN0015

L520: https://pastebin.com/U6MaBAY3
Keyboard: PNP0303 Pointing: LEN0017

X201: https://linux-hardware.org/index.php?probe=d7085ee4c8&log=dmesg.1
Keyboard: PNP0303 Pointing: LEN0018

X220: https://bbs.archlinux.org/viewtopic.php?id=237669
Keyboard: PNP0303 Pointing: LEN0020

X230: https://forums.bunsenlabs.org/viewtopic.php?id=2460
Keyboard: PNP0303 Pointing: LEN0020

X131e: https://linux-hardware.org/index.php?probe=d765880811&log=dmesg
Keyboard: MSF0001 Pointing: LEN0026

X1 Carbon Gen 1: https://bugzilla.kernel.org/show_bug.cgi?id=85851
Keyboard: LEN0071 Pointing: LEN0030

s230u: https://launchpadlibrarian.net/147231958/dmesg-reboot.txt
Keyboard: PTL0001 Pointing: LEN0031

T540p: https://linux-hardware.org/index.php?probe=da766a30bc&log=dmesg
Keyboard: LEN0071 Pointing: LEN0034

X240: https://linux-hardware.org/index.php?probe=fa7155b0e4&log=dmesg
Keyboard: LEN0071 Pointing: LEN0035

T440p: https://bugzilla.kernel.org/show_bug.cgi?id=91541
Keyboard: LEN0071 Pointing: LEN0036

T440s: https://bugzilla.kernel.org/show_bug.cgi?id=91541
Keyboard: LEN0071 Pointing: LEN0036

T450: https://gist.github.com/kzar/1c38630eb22e4bf5b976
Keyboard: LEN0071 Pointing: LEN200e

Others:
https://github.com/torvalds/linux/blob/master/drivers/input/mouse/synaptics.c

Test result: This can make Windows automatically install the Lenovo
touchpad driver. It also fixes the T440p touchpad issue.

Change-Id: Ifb635da99c5e05f987aaf4f172108d788dcc2932
Signed-off-by: dalao <dalao@tutanota.com>
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36371
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-14 09:50:10 +00:00
Wim Vervoorn 65535332db mb/facebook/monolith: Add fmd files for 6MB BIOS area
The current flash layout requires changes to the descriptor area to
create the 9MB BIOS region.

Add fmd files that allow switching to coreboot by only replacing the
BIOS region.

BUG=N/A
TEST=tested on facebook monolith

Change-Id: I2b003018e245693934202505d7e3891c2f545e6c
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40040
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-04-14 09:49:10 +00:00
Patrick Rudolph fc8867c3d8 mb/lenovo: Add additional FMAPs for stripped ME
Make it easier to use measured boot with stripped ME by
providing the corresponding FMAPs.

Change-Id: I1763583a42bbc91e6acc06b262deab10d34447a3
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39798
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Marcello Sylvester Bauer <sylv@sylv.io>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-04-14 09:48:55 +00:00
Marcello Sylvester Bauer 45a354fe78 mb/lenovo/*: Add vboot RO FMAPs on 12MiB devices
Tested on W530

Change-Id: I9be0c5e06fcb8287d32171cb72dabb5fcf047e7a
Signed-off-by: Marcello Sylvester Bauer <sylv@sylv.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39450
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-14 09:48:44 +00:00
Duncan Laurie c68902c210 Update vboot submodule pointer
Update the pointer for vboot_reference so it can be used to compile
depthcharge payload on the master branch.

Change-Id: I5fc6e05896d7221a1e48ca86c6b15081488302b5
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-04-14 09:47:56 +00:00
Duncan Laurie 287cf6c7d1 lp/drivers/usb: Work around QEMU XHCI register issue
The QEMU XHCI controller does not support byte/word reads from the
capability register and it expects dword reads only.

In order to make this work move the access of the capability
register fields to use macros instead of a packed struct bitfield.

This issue was filed upstream:
https://bugs.launchpad.net/qemu/+bug/1693050

The original fix attempt in 2012 was not effective:
6ee021d410

With this change the controller is detected properly by the libpayload
USB drivers.

Change-Id: I048ed14921a4c9c0620c10b315b42476b6e5c512
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-14 09:47:22 +00:00
Brandon Breitenstein bc885c194c google/chromeec: Add USB MUX Interrupt
Kernel relies on the USB MUX interrupt to configure USB devices that
are connected on the Type-C ports for TGL. Adding in the Q1C Interrupt
so the Kernel can properly receive and configure USB devices

BUG=b:152902608
TEST=buld_packages for volteer and verified that Proto 1 and Proto 2
are now seeing extcon events

Change-Id: Ie3a2f829a295f090a03e72e12f19ecc5bb724952
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Prashant Malani <pmalani@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-04-13 23:39:29 +00:00
Patrick Rudolph 56a3ef2e74 acpi: Bump MADT to revision 3
Add structs and methods for revision 3.

Change-Id: Ida75f530551ad2b8b20ce7fdeffb3befc51296bc
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2020-04-13 23:32:27 +00:00
Patrick Rudolph c02bda0f06 acpi: Bump FADT to revision 6
Some of the revision 4 FADT fields were already updated to ACPI
spec revision 6, but not all of them. In addition the advertised
FADT revision was 3.

Implement all fields as defined in version 6 and bump the advertised
FADT revision to 6.

Also set all used access_size fields and x_gpe0_blk to sane values
as Windows 10 verifies those fields starting with FADT revision 5.

Fixes: https://ticket.coreboot.org/issues/109

Tested on Windows 10.

Change-Id: Ic649040025cd09ed3e490a521439ca4e681afbbf
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2020-04-13 23:32:15 +00:00
Varun Joshi 2255ebaa23 mb/google/deltaur: Add support to enable GbE on variant
- Configure devicetree for enabling GbE on variant
  and remove from baseboard.
- Configure Kconfig to enable GbE region.
- Configure fmd to incorporate GbE.

BUG=b:151102809
Cq-Depend: chrome-internal:2843183
Signed-off-by: Varun Joshi <varun.joshi@intel.corp-partner.google.com>
Change-Id: I1c36b132546049e3e775585c41164072f4ece73e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2020-04-13 20:28:18 +00:00
Anil Kumar c6f5b05cf3 mb/google/deltaur: Return SKU ID info
For Deltaur and Deltan variants return proper SKU ID based on EC
firmware type and sensor detect GPIO value

BUG=b:152544516
TEST=make build successful for deltan

Change-Id: I20a497739e5062400b093648c3a634203dec6105
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-04-13 20:26:54 +00:00
Varun Joshi 06684979f9 mb/google/deltaur: Update onboard memory config
Update dq, dqs map based on deltan schematics.
Configure memory to read SPD.

BUG=b:151702387

Signed-off-by: Varun Joshi <varun.joshi@intel.corp-partner.google.com>
Change-Id: I29059f09dd08c81b5ca5fe1215f33871835703fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-04-13 20:24:59 +00:00
Rajat Jain 3639f38171 include/input-event-codes.h: Add Linux input key codes header file
Add header file from keycodes from Linux sources. This is needed so
that coreboot can provide scancode to keycode mappings in the ACPI
that the linux kernel expects (https://lkml.org/lkml/2020/3/24/588)

Signed-off-by: Rajat Jain <rajatja@google.com>
Change-Id: I40051cb63a6c154728887ac9b0521bc671b2a518
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40029
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-13 19:54:30 +00:00
Rajat Jain 999001144f util/lint: Accept "GPL-2.0-only WITH Linux-syscall-note" licenses
The Linux kernel UAPI header files are licensed under
/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */

Allows files with this license to be included in coreboot.
For more details about this particular license:

https://www.kernel.org/doc/html/v4.17/process/license-rules.html
https://spdx.org/licenses/Linux-syscall-note.html

Change-Id: I4f0f8d36c637a66a6999a18321fdbc4c42d5751e
Signed-off-by: Rajat Jain <rajatja@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-04-13 19:54:19 +00:00