Commit Graph

33460 Commits

Author SHA1 Message Date
Julius Werner 1645ecc8f6 cbfs: Remove unused functions
cbfs_boot_load_stage_by_name() and cbfs_prog_stage_section() are no
longer used. Remove them to make refactoring the rest of the CBFS API
easier.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ie44a9507c4a03499b06cdf82d9bf9c02a8292d5e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-03-11 12:31:28 +00:00
Kangheui Won 5674bf15f9 mb/google/puff: Enable cros_ec_keyb device
This is required to transmit button information from EC to kernel.

BUG=b:150830342
BRANCH=None
TEST=firmware_ECPowerButton test passes on puff

Change-Id: I10ba9d55e8997ce2412deb0613cfcaa8f24f271d
Signed-off-by: Kangheui Won <khwon@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-03-11 06:29:31 +00:00
Bartek Pastudzki 69a88ddb5d util/scripts/ucode_h_to_bin.sh: Accept microcode in INC format
Intel supplies microcode (at least for MinnowBoard) in Intel Assembly
*.inc format rather than C header. This change allow to pass in
configuration directory with *.inc files rather than list of *.h
files.

Change-Id: I3c716e5ad42e55ab3a3a67de1e9bf10e58855540
Signed-off-by: Bartek Pastudzki <Bartek.Pastudzki@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/25546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-10 20:50:12 +00:00
Nico Huber 47ac6355b3 soc/intel/common: Add more GPIO definition macros
Make i/o-standby state and termination configurable for GPIs.

Change-Id: Id1a3c00aa8a857afa08e745b0b6a578b01fa6d47
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-10 20:47:10 +00:00
Stephen Douthit 56a74bca69 soc/intel/dnv: Set INT_LINE accouting for PIRQ routing & swizzling
This code also sets unused interrupt lines to the recommended safe
value of 0xff instead of ignoring such devices.

Change-Id: I7582b41eb3288c400a949e20402e9820f6b72434
Signed-off-by: Stephen Douthit <stephend@silicom-usa.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34714
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-10 20:45:53 +00:00
Stephen Douthit ecb0e409a4 soc/intel/dnv: Add ACPI _PRT methods for virtual root ports
This eliminates Linux kernel warnings that look like:
    pcieport 0000:00:17.0: can't derive routing for PCI INT B
    ixgbe 0000:07:00.1: PCI INT B: no GSI - using ISA IRQ 10

Change-Id: I2029e7a8252b9e48c1df457d8da5adce7d1ac21d
Signed-off-by: Stephen Douthit <stephend@silicom-usa.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-10 20:45:40 +00:00
Stephen Douthit a51f490870 soc/intel/dnv: Fix ACPI reporting of root port interrupt routing
pcie_port.asl defines an IRQM method that looks up legacy interrupt
swizzling based on incoming interrupt "pin" A-D and root port number.

Unfortunately the 8-bit root port number stored at offset 0x4F in the
config space matches the device number, not the 1-8 scheme used in
the LUT reported to the OS.

Fix the case values to match the hardware.

Change-Id: I103d632a4bc99461f02e05aa0f9a9eb7376770d9
Signed-off-by: Stephen Douthit <stephend@silicom-usa.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34712
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-10 20:45:34 +00:00
Praveen Hodagatta Pranesh aa6a8fb919 mb/intel/{saddlebrook,kunimitsu}: Add macro for SaGv config
Change-Id: Ia31da9997ba46c15cd385bf55e009cf299848b64
Signed-off-by: Praveen Hodagatta Pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36423
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-10 20:42:14 +00:00
Elyes HAOUAS b7731574f4 src: Remove unneeded 'include <arch/cache.h>'
Change-Id: I6374bc2d397800d574c7a0cc44079c09394a0673
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37984
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-10 20:39:50 +00:00
Paul Menzel 2d65608733 winbond/w83667hg-a: Disable mouse controller also during resume
There is no reason to not disable the controller during resume. That
way, no ASL is needed.

Change-Id: I282a03647ee0958abb118fafe306abe5782db71c
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/22286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-10 20:37:25 +00:00
Stephen Douthit 2c18ba5bd7 soc/intel/dnv: Don't clobber SATA_MAP while trying to set mode
SATA Mode Select is bit 16 of the SATA General Configuration
register.  This code currently incorrectly pokes at the Port Clock
Disable bits in the Port Mapping Register, and without clock the
affected ports can't link.

Change-Id: I37104f520a869bd45a32cfd271d0b893aec3c8ed
Signed-off-by: Stephen Douthit <stephend@silicom-usa.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Vanessa Eusebio <vanessa.f.eusebio@intel.com>
Reviewed-by: David Guckian
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-10 20:31:33 +00:00
Matt Delco 54e9894353 soc/intel: fix eist enabling
There was a bug like this for skylake that seems to have been copied to
other SoCs.

Signed-off-by: Matt Delco <delco@chromium.org>
Change-Id: Ib4651eda46a064dfb59797ac8e1cb8c38bb8e38c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-03-10 20:29:10 +00:00
Sebastian 'Swift Geek' Grzywna 49fb39b783 Documentation: Update codenames
austin-3 was a devel board, retracting
t60 comes in variants with discrete gpu and only intel gpu one

Change-Id: Ic1f7397b8676bdcc15f63d59d87518d35bba5b4d
Signed-off-by: Sebastian "Swift Geek" Grzywna <swiftgeek@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-10 20:26:32 +00:00
Evgeny Zinoviev 79f7fcc927 util/nvramtool: fix building on OpenBSD
OpenBSD's gcc 4.2.1 doesn't know about _Noreturn

Change-Id: Ie9e1885c483941d3d0ce8c8948af53f1ef8bb5db
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-10 20:23:39 +00:00
Evgeny Zinoviev b863468533 util/board_status: Add support of CMOS values dump
Change-Id: I89f9a0e9622557b01dda52378f8f1323777bce39
Signed-off-by: Evgeny Zinoviev <me@ch1p.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/28565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-10 20:20:27 +00:00
Nico Huber 549a33091a abuild: Always build the default config
Abuild allows us to add config files below `configs/` for each
mainboard. So far, these were built instead of the default config.
However, that allows to hide errors in the default config. Hence,
we should build that too in any case.

Change-Id: I94075dbaa6fabeb75bdbc92e56f237df80c15cef
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39382
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-10 13:29:38 +00:00
Nico Huber 0266be0d2b soc/intel/xeon-sp,mb/ocp/tiogapass: Don't fake binaries
If we don't pretend to have binaries, there is no need to add fake ones.
This also fixes building the default config.

Change-Id: I8f933f24a734a9ce3d82ef57f7f234ee4dfa86e9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39383
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-10 11:52:45 +00:00
Eric Lai 8fb7cd4123 lib/spd_bin: Correct LPDDR3 SPD information
Follow JEDEC 21-C to correct JEDEC LPDDR3 SPD information. Based on
JEDEC 21-C, LPDDR3 has the same definition with LPDDR4.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I7c9361caf272ea916a3a618ee2b72a6142ffc80c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39366
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-10 10:05:48 +00:00
Michał Żygowski b9f9f6c12b mb/libretrend/lt1000: Add Libretrend LT1000 mainboard
Change-Id: I32fc8a7d3177ba379d04ad8b87adefcfca2b0fab
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-03-10 10:04:05 +00:00
Michał Żygowski 48be6b276a mb/protectli/vault_kbl: Add FW6 support
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I03e8e8db5d827fe113280f2a6376d364edf42870
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-03-10 10:03:17 +00:00
Srinidhi N Kaushik dcd3d072d4 mb/intel/tglrvp: add CNVi ASL entry for dynamic SSDT generation
This change uses drivers/intel/wifi chip for CNVi device and
adds dynamic SSDT entires for CNVi also export wake gpio for CNVi

BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board and check for SSDT entries
for CNVi

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Icdbffa0c29c9e0849a6a99f8592b6f35c0bb3207
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39315
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-10 10:02:19 +00:00
Wonkyu Kim 2b4ded0be8 soc/intel/tigerlake: Enable Hybrid storage mode
To use Optane memory, we need to set 2x2 PCIe lane mode while we need
to set 1x4 PCIe lane mode for NVMe. The mode can be selected using
the FIT tool at build time.

By enabling hybrid storage mode in FSP, FSP will set 2x2 PCIe lane mode
if Optane memory is detected and the mode is not 2x2 and set 1x4 PCIe
lane mode if Optane memory is not detected and the mode is not 1x4
during boot up. The mode is saved in SPI NOR for next boot.

BUG=b:148604250
BRANCH=none
TEST=Build and test booting TGLRVP from NVMe and Optane
Check PCIe lane configuration.

Show all the NVMe devices
lspci -d ::0108
Show all the NVMe devices and be really verbose
lspci -vvvd ::0108
Print PCIe lane capabilities and configurations for all the NVMe devices.
lspci -vvvd ::0108 | grep -e x[124]
Print all the PCIe information of the device ae:00.0
lspci -vvvs ae:

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I25bc380697b0774cc30ad1b31ad785ee18822619
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39232
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-10 09:57:41 +00:00
Brandon Breitenstein 01ec713c26 mb/google/volteer: set TcssXhciEn to 1
BUG=144874778
TEST=Built with Volteer recipe and verified USB functionality

Change-Id: I6cbdbd8a4f65a0fe19e3fb8d7b60b8b849f104e7
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-03-10 09:56:36 +00:00
Nico Huber f6f54dd3fa libpayload/corebootfb: Replace obsolete macros FI and CHARS
These macros serve no purpose anymore, let's do the substitution
manually once and for all. Also update the comment on the macros
and fix whitespace on the touched lines.

TEST=Checked that there are no changes in compiled code.

Change-Id: Ib60f9ab157e2e7d44b551dd4f695a6c25ebeb405
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-03-10 09:00:35 +00:00
Michał Żygowski cd0a5fcafc MAINTAINERS: Add 3mdeb as Protectli mainboards maintainers
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I03301441bb07e64aeb59e659ab1b22442b73ca1c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39418
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-10 06:46:49 +00:00
T Michael Turney 45473dd370 libpayload: Add uart/serial driver support for trogdor
Change-Id: I5be3904298cd88c60dbc6d8d662beeede2abe442
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35960
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-09 22:58:56 +00:00
Elyes HAOUAS 0afd3f41d6 arch/arm: Use 'print("%s...", __func__)'
Change-Id: I83fb453344c31f2cfa97bdaf1b8791a7bef97fd7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-03-09 21:31:07 +00:00
Karthikeyan Ramasubramanian 4ebe6dff1a mb/google/dedede: Add PCIe Root Port Configuration
Add configuration for all the PCIe Root ports and Clock Source.
Configure the Root Ports as disabled and clock sources as not used.

BUG=None
TEST=Build the mainboard.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I0a1ad7e056907e454a93f51c84e1d99f08b7bdef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39166
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-09 21:28:56 +00:00
Karthikeyan Ramasubramanian c83c5af3ae mb/google/dedede: Configure EDP_HPD GPIO
This enables display for use by payload.

TEST=Build and boot the mainboard. Ensure that the screens displayed by
payload are visible.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I5fcd70623b15ae39954242605e75b2c5ce02ff14
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-03-09 21:28:40 +00:00
Karthikeyan Ramasubramanian 2c208bddc9 mb/google/dedede: Configure EC <-> AP GPIOs
BUG=b:150869661
TEST=Build and boot the mainboard. Trigger apreset from EC console.
Trigger reboot from AP console.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I0d6dd0b4264c11f7ee0ef436cc819b0bb92974f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39325
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-09 21:28:23 +00:00
Karthikeyan Ramasubramanian 8499f7fb1b mb/google/dedede: Add GPIO list
Leave all the GPIOs in not connected state so that they can be
configured depending on the use-case. This is done to park the GPIOs in
a known safe state. This will also help to ensure that the required
GPIOs are configured when the concerned use-cases are enabled.

Below GPIOs are configured in Native Function 1 and are required for
boot-up.
* VCCIN_AUX_VID0
* VCCIN_AUX_VID1
* AP_SLP_S0_L
* PLT_RST_L
* CPU_C10_GATE_L
* GPDs

BUG=None
TEST=Build and boot the mainboard.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I5293536f66a6b08c9c2d2a6281684755a0c0b1b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39114
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-09 21:28:08 +00:00
Alex Levin 3bc41cf7b4 mb/google/volteer: Enable FPMCU on volteer
BUG=b:147500717
TEST=none

Change-Id: I32fa27b399127dbf8608e0556c77431d2dad652d
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-03-09 21:26:48 +00:00
Nick Vaccaro fa0bdd9ee0 mb/google/volteer: change two gpio settings
- declare the FPMCU interrupt to be level-triggered
 - change EC_PCH_WAKE_ODL gpio to native function mode
 - corrected spelling of a signal name in a comment

BUG=b:144933687, b:148179954
BRANCH=none
TEST=none

Change-Id: I62da900d0b71139e55b52d06ec09ca25106f73cd
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-03-09 21:26:32 +00:00
Michał Żygowski 83565dea86 mb/protectli/vault: Add FW2B and FW4B Braswell based boards support
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I553fd3a89299314a855f055014ca7645100e12e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-03-09 21:26:20 +00:00
Angel Pons 9d422ef381 mb/asus/p5g41t-m_lx: Do not set BSEL GPIOs in devicetree
This mainboard has the FSB BSEL straps wired to SuperIO GPIOs. They are
set up in romstage, so it makes no sense to clobber the registers with
garbage in ramstage.

Tested, my Asus P5G41T-M LX still boots and it does not need a full
reset on almost every reboot.

Change-Id: I6ea498119df44243ec42e3cb5c2903de32a17373
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39384
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-09 21:25:45 +00:00
Angel Pons d903fffbc9 mb/asus/p5g41t-m_lx: Correct GPIO direction
Not all GPIO4 pins on the SuperIO are configured as outputs.

Change-Id: Idf6350551a91c4c1a25a83e3fb9b1a6722a81c36
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-03-09 21:25:22 +00:00
Angel Pons acabbce229 mb/asus/p5qpl-am: Do not set BSEL GPIOs in devicetree
This mainboard has the FSB BSEL straps wired to SuperIO GPIOs. They are
set up in romstage, so it makes no sense to rewrite their values in
ramstage.

Tested, my Asus P5QPL-AM still boots.

Change-Id: Ic47f96d12420ebcc70ab5cea940c4c09620c03ca
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-03-09 21:23:27 +00:00
Michał Żygowski 915d1eaeae soc/intel/braswell/chip.h: Include smbios.h for Type9 Entries
In order to add the smbios_slot_desc for the SMBIOS Type9 entries into
the devicetree, and not use numbers but strings like
"SlotTypePciExpressGen3X4", smbios.h needs to be included in the
static.c.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Id15fe4101d14479b02e536fdf63748a241c02bd3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-03-09 11:03:41 +00:00
Jacob Garber f8cd291344 drivers/ipmi: Fix buffer double-free
If reading the data for the asset_tag fails, that buffer should be
freed, not the one for serial_number.

Change-Id: I2ecaf7fd0f23f2fb5a6aa0961c7e17fff04847f4
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1419481, 1419485
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-09 08:23:41 +00:00
Nico Huber 4ce52903b0 3rdparty/libgfxinit: Update submodule pointer
Changes allow to use the integrated panel logic (power sequen-
cing and backlight control) for more connectors. The Kconfigs
GFX_GMA_PANEL_1_PORT and GFX_GMA_PANEL_2_PORT can now be set
to any port, e.g.

  config GFX_GMA_PANEL_1_PORT
          default "DP3"

Now that the panel logic is not tied to the `Internal` port
choice anymore, we can properly split it into `LVDS` and `eDP`.

This also adds Comet Lake PCI IDs which should still work the
same as Kaby and Coffee Lake.

Change-Id: I78b1b458ca00714dcbe7753a7beb4fb05d69986b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38921
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-09 08:20:12 +00:00
Patrick Rudolph 9f3e734e5c libpayload: Improve rtc functions
On Lenovo T500 the RTC readings where wrong, as RTC has
different encodings, depending on the statusB register.

Support BCD vs binary RTC format and AM/PM vs 24h RTC format.

Fixes wrong date and time on Lenovo 500.

Change-Id: Id773c33e228973e190a7e14c3d11979678b1a619
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/18498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-03-09 08:14:04 +00:00
Evgeny Zinoviev ef613b97cf Documentation: Add Montevina ThinkPads common page
- Add a common page about Montevina ThinkPads.
- Describe how to disable ME and remove its firmware on these models.
- Describe vendor flash layouts.

Thanks to swiftgeek for his help when writing this, especially the last
paragraph and flash layouts.

Change-Id: I85917821efe63fff4b933b6226e99c17b63eb1b9
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-09 08:10:36 +00:00
Nico Huber de74842049 libpayload/corebootfb: Add option to center a 80x25 console
This makes payloads which are hardcoded to a 80x25 console look much
better, e.g. FILO with its "GRUB" user interface.

Change-Id: I9f4752328d85d148cd40a0c2337c7191e1d6a586
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-09 08:09:44 +00:00
Nico Huber e612418221 libpayload/corebootfb: Keep local copy of framebuffer info
Keeping a local copy of the framebuffer info allows us to make changes,
e.g. add offsets. It also avoids trouble with relocation.

Change-Id: I852c4eb229dd0724114acb302ab2ed7164712b64
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-09 08:09:30 +00:00
Angel Pons c97bf6fdb4 util/superiotool: Drop one SCH5317 entry
The SCH5317 can have either 0x85 or 0x8c as device ID. However, the
former results in false positives on any ITE IT85xx series embedded
controller, which has led some people to think that chip was actually in
their laptops. Moreover, there is no register dump for the SCH5317.

Since nobody has touched this in over a decade, avoid further confusion
by dropping the misleading definition.

Change-Id: I4d1d34d1b88b878461499e52f1a916ee1e33210d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-03-09 08:09:11 +00:00
Srinidhi N Kaushik 9900cf8009 mb/intel/tglrvp: Add memory config for Tiger Lake UP4
Add LPDDR4 memory configuration for Tiger Lake UP4 platform which
includes
1. DQ/DQs Mapping
2. Board id Support
3. SPD indexing

BUG=none
BRANCH=none
TEST= Build TGL UP4 successfully

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Ibbd7036919c1a91ef12049d2af657f0a3597b57e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39365
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-09 08:08:26 +00:00
Wonkyu Kim 7e303581bc mb/intel/tglrvp: Add TGL UP4 RVP
Add initial TGL UP4 RVP build enviorment

BUG=none
BRANCH=none
TEST= Build TGL UP4 successfully

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Iab7ada0746394539586e7cc159112dc8208fdd7c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39363
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-09 08:08:15 +00:00
Srinidhi N Kaushik 7b6a82dc1a vendorcode/intel/fsp/fsp2_0/tgl: Update FSP header for Tiger Lake
Update FSPS header to include HybridStorageMode Upd for Tiger Lake platform
version 2457.

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Ib6ac89163c0f7a11910e56b9804e386f8bcf355d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-03-09 08:07:21 +00:00
Angel Pons b3bfb2a1a7 util/kconfig: Silence warning about _GNU_SOURCE
For some reason, this symbol gets redefined, which causes a warning.
Hide the warning by checking whether it is already defined.

Change-Id: I70ffc9a799e0b536d6aba7d00f828bd6d915d94c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-03-08 14:24:03 +00:00
Srinidhi N Kaushik ac7d6b409e mb/google/volteer: add CNVi ASL entry for dynamic SSDT generation
This change uses drivers/intel/wifi chip for CNVi device and
adds dynamic SSDT entires for CNVi also export wake gpio for CNVi.

BUG=none
BRANCH=none
TEST=Build and boot volteer

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Ia8baf1c7b770db23f31383bda46ae8d090468560
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-03-07 20:56:03 +00:00