Commit Graph

28466 Commits

Author SHA1 Message Date
Julius Werner faa3d4680c vboot: Makefile: Also apply CPPFLAGS include path fixups to ccopts
In some cases (e.g. Arm architecture variants), include paths are stuck
into <stage>-generic-ccopts rather than CPPFLAGS_<stage> (in fact, the
whole redundancy between these two is kinda stupid and we should
probably eliminate the latter, but I don't want to get into that right
now). This patch makes sure those paths are also correctly translated
when invoking $(MAKE) for vboot.

Change-Id: I37f09b88e555567590664e0e6fac23c34fd887df
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-28 13:38:16 +00:00
devmaster64 3f888ef845 mb/asus/h61m-cs: Add ASUS H61M-CS
Working:
 - USB (Partially. Check "Not working")
 - PCIe
 - PCIe graphics
 - All SATA ports
 - Native memory init
 - On-board audio (back and front)
 - S3 (Sleep and wake)

Not working:
 - Fan control
 - USB (If the keyboard has a USB Hub or if the keyboard
        is connected through 2 or more hubs then it doesn't
        initialize in time. A simple reboot allows the
        keyboard to be used in SeaBIOS and the bootloader)

Untested:
 - PS/2
 - On board graphics

Change-Id: I4ed2077248a8d7123c728c790d9b81fe37956ed2
Signed-off-by: Abhinav Hardikar <realdevmaster64@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30767
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-28 13:37:50 +00:00
Shamile Khan 6afeef829f mb/google/octopus: Fix termination for unused dual voltage pins
These pins should not have pull downs configured in standby state as that
can cause contention on the termination circuitry and lead to incorrect
behavior as per Doc# 572688 Gemini Lake Processor GPIOTermination
Configuration.

BUG=b:79982669
TEST=Checked that code compiles with changes.

Change-Id: If3cadc000ec6fc56019ee3f57e556dc819d5e0a5
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/c/30823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-01-28 13:37:18 +00:00
Seunghwan Kim 6dda1e0556 mainboard/google/octopus/variants/casta: Decrease touchpad I2C CLK frequency
ELAN touchpad supports up to 400KHz, so we need to limit its CLK
frequency to 400HKz.

BUG=b:123376618
BRANCH=octopus
TEST=built and verified touchpad I2C clk frequency gets be lower than 400KHz

Change-Id: If7a43fe20c7e5abdf23c8c36e34c072c371563bf
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/c/31085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-01-28 13:36:49 +00:00
Arthur Heymans 36ced10364 mb/lenovo/thinkcentre_a58: Extend mb name
While branded as thinkcentre a58 this board can also be found as
"L-IG41M".

Change-Id: I06ed424138c46c6b2f29f15c7ea5c3648b26a8d3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/31109
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-28 13:36:29 +00:00
Chris Zhou daeaa772a2 mb/google/sarien: Using HID over I2C to enable Melf TouchScreen
Current Melfas touchscreen driver cannot unregister ifself when
connecting without Melfas touchscreen or connecting with other devices.
And Melfas touchscreen FW can use I2C and HID over I2C driver, so
switch to using HID over I2C driver.

BUG=b:122710830
BRANCH=master
TEST=Verify touchscreen on sarien works with this change.

Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com>
Change-Id: If04a2904a0f72a6c8363ab2c9865926c71cb5186
Reviewed-on: https://review.coreboot.org/c/31062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-01-28 13:36:07 +00:00
Raul E Rangel df3064227f amd/stoneyridge: Disable GPIO MASK STATUS
MASK_STATUS disables interrupt status generation for the entire GPIO
controller when any debounce register is configured. This causes
problems when the kernel is loading drivers because we could lose
interrupts for previously loaded devices.

sb_program_gpios is also not setup to wait when configuring
PAD_DEBOUNCE, so there is a potential that we could lose the interrupt
status enable bit for other registers. By disabling MASK_STATUS we avoid
that problem.

BUG=b:113880780
BRANCH=none
TEST=Ran a reboot stress test that concluded that we are no longer
losing TPM interrupts while booting.

Change-Id: Ife1db3b1449f205092509595cbc3eca511bff57a
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
2019-01-28 13:35:44 +00:00
Julien Viard de Galbert 595202c304 soc/intel/denverton_ns: Add ACPI T-States and P-States
Also make soc_get_tss_table public and weak instead of static
in intelblock so it can be overridden in denverton.

Change-Id: Id9c7da474a81417a5cebd875023f7cd3d5a77796
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/c/25430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Vanny E <vanessa.f.eusebio@intel.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: David Guckian
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
2019-01-28 13:33:30 +00:00
Nico Huber 3b0667dd2a soc/intel/{apl,skl}: Drop redundant `select RTC`
RTC is now implicitly selected through SOC_INTEL_COMMON_BLOCK_RTC
and SOC_INTEL_COMMON_PCH_BASE.

Change-Id: I1885c419cfe318b75f3bda6220d4a6f6a8e26575
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/31113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-01-28 10:45:46 +00:00
Lijian Zhao 7060b5d7fe soc/intel/common/rtc: Enable RTC in common code RTC
Intel RTC common code driver need to turn on RTC itself.After the
change, cannonlake and icelake platform will have RTC enabled.

BUG=b:123372643
TEST=build and boot up on sarien platform, check .config to see
CONFIG_RTC is set.

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I0c8c5cf9e6f7f338b1f2f784c04254649d257536
Reviewed-on: https://review.coreboot.org/c/31112
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-28 10:45:30 +00:00
Angel Pons acb6e138b2 src/soc/intel/cnl/chip.h: Fix preprocessor condition
Commit dc666f5 (soc/intel/cannonlake: Change in SaGv options) added a
conditional preprocessor directive, but its condition was incorrect
because SOC_INTEL_CANNONLAKE is selected for CNL, CFL and WHL. Thus, an
explicit check for !SOC_INTEL_COFFEELAKE is required.

While we are at it, clean up the comment above a bit.

BUG=b:123184474
Change-Id: I8a6959bb615fb5668cbfe54339747d135bd5a005
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31095
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-28 06:36:14 +00:00
Elyes HAOUAS d731a24ff1 src/cpu/intel: Set get_ia32_fsb function common
Add get_ia32_fsb returns FSB values in MHz of intel's CPUs.
Also add get_ia32_fsb_x3 function. It returns round up 3 * get_ia32_fsb.

Change-Id: I232bf88de7ebba6ac5865db046ce79e9b2f3ed28
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30103
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-27 12:13:09 +00:00
Elyes HAOUAS b58e99dfa5 src: Fix the warning "type 'hex' are always defined"
This is spotted using "./util/lint/kconfig_lint"
While at it, do the check in C and not the preprocessor.

Change-Id: Icfda267936a23d9d14832116d67571f42f685906
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-27 11:14:26 +00:00
Elyes HAOUAS d3fa7fa5d8 nb/intel/i945: Fix typo on DMIBAR32(0x334)
Change-Id: Ib894c24bc787c6c211da26dca78bcd330ded6681
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-27 10:40:35 +00:00
Elyes HAOUAS 3452eca26d nb/intel/i945: Remove initialization already done at bootblock
Upper 128bytes of CMOS and RCBA are already enabled at bootblock.
Tested on 945g-MA. Resuming from suspend is working fine

Change-Id: I3f34380b0e700cf60688ad58465f9cb0aeda0928
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31107
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-27 10:39:54 +00:00
Philipp Hug 2ef569a405 mb/qemu-riscv: update to match current qemu version
Boots again to payload not found on qemu.

Change-Id: Ie107eb882cbaac5a5a06c1ff990e7b9364377640
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/c/30554
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-26 13:40:51 +00:00
Angel Pons 175778f059 Revert "util/bincfg: code cleanup: convert sym_table to a local variable"
This reverts commit 48c24ce5ee.

Reason for revert: Commit broke bincfg, and sym_table as a global
variable is less bad than passing it around in function calls.

Change-Id: Ib8d64a1dc201d17a4e278ab0114958b6807a45ac
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31105
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-26 13:35:43 +00:00
Elyes HAOUAS 3f7fd58823 crossgcc: Update CMake to version 3.13.3
Change-Id: If3bd670e2273715b6996e2ca78a0b9c412bfd220
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-26 13:33:55 +00:00
Patrick Georgi b8c107c7b8 util/crossgcc: Update to binutils 2.31.1 and gcc 8.2
Change-Id: Icf7c6bdd4021bf84cc295c819f93838248e0f4c7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/31089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-01-26 13:33:32 +00:00
Felix Held dacf083c2f superio/common/conf_mode: use pnp_write_config instead of outb calls
Change-Id: Ibab8e798bd6bee14ef4141373e48100504d6cb46
Signed-off-by: Felix Held <felix-github@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/31061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-25 17:53:59 +00:00
James Ye a6450d7b76 mb/lenovo/x131e: remove PMH7
This board does not have PMH7.

Change-Id: I382958f012e5f4445efc76c7f36bbdf460c29be4
Signed-off-by: James Ye <jye836@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31065
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-25 12:44:43 +00:00
Kyle Stevenson 769c309e3d util/superiotool: detect Fintek F81866, F8196*
F81866 detection tested with the iBASE SI-613:

    superiotool r4.9-420-g034e5e6
    Found Fintek F81866 (vid=0x3419, id=0x1010) at 0x4e

F8196* detection is based on chip IDs provided by iBASE, but untested.

Change-Id: I7210e1523a188a8593cd03547bb0c95cd3e7aa39
Signed-off-by: Kyle Stevenson <kstevenson@comqi.com>
Reviewed-on: https://review.coreboot.org/c/31052
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-25 11:24:59 +00:00
Julien Viard de Galbert cf2b72f951 soc/intel/denverton_ns: Enable ACPI using intelblock
- Port the existing denverton tables to intelblock
- Add C-States table for denverton

Note: Removed code is functionally identical to corresponding
common code.

Tested-on: scaleway/tagada

Change-Id: Iee061a258a7b1cbf0a69bcfbf36ec2c623e84399
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/c/25428
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-25 11:24:30 +00:00
Kane Chen b933495229 mb/google/octopus: Override emmc DLL values for Ampton
New emmc DLL values for Ampton

BUG=b:122307153
TEST=Boot to OS on 5 systems

Change-Id: Iadd58d254f4bb384f483c2c3e5615f7569d5211c
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/31048
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
2019-01-25 11:24:02 +00:00
Duncan Laurie 5e96399789 mb/google/sarien: Force power on after cr50 update
By default this board is configured to not power up after an
EC reset.  However in the case of a cr50 firmware update that
will reset the EC it will end up powered off.  In order to have
it stay powered up configure the board to power up.  This will
get reset to the configured default when it boots again.

BUG=b:121380403
TEST=update cr50 firmware and reboot to ensure system boots and
does not end up powered off.

Change-Id: I85beae24b1bc56bb0813f1fd1305218f04b0c1c8
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31058
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-25 11:22:52 +00:00
Duncan Laurie f131fc7f37 vendorcode/google/chromeos: Add mainboard hook before cr50 update
In order to allow the mainboard to configure the system before a
cr50 initiated update reset add a weak function that the mainboard
can override if necessary.

This will allow a board that would otherwise be configured to
stay off after an EC reset to instead power up after the reset and
not end up in a shut down state after a cr50 update.

BUG=b:121380403
TEST=update cr50 firmware on sarien and reboot

Change-Id: I11f9e8c9bfe810f69b4eaa2c633252c25004cbd0
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31057
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-25 11:22:35 +00:00
Duncan Laurie 26bc3282f6 soc/intel/cannonlake: Export function to set After G3 state
Export the SOC level function to set the After G3 state so it
can be changed by the mainboard.  The setting will be restored
by a normal boot but in some circumstances coreboot wants to
ensure that it will be powered up again after a reset.

BUG=b:121380403
TEST=update cr50 firmware on sarien and reboot and ensure the
host does not power off after the cr50 initiated reset.

Change-Id: I6cd572ac91229584b9907f87bb4b340963203c32
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31056
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-25 11:22:22 +00:00
Duncan Laurie 52b5b587f1 soc/intel/cannonlake: Disable CpuRatio and SaGv in recovery
Disabling CpuRatio UPD for FSP will ensure it does not force a
hard reset to set the CPU Flex Ratio at boot.  This is important
in a recovery mode boot where the SOC will lose power and need
to set the flex ratio again.

Disabling SaGv makes recovery mode training faster and mirrors
the setting that was done on Skylake.

BUG=b:123305400
TEST=reliably enter recovery mode on sarien

Change-Id: Ie9664493a980af9acce82faff81f4c4b1355be73
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-01-25 11:22:06 +00:00
Lijian Zhao 38e40414d2 mb/google/sarien: Increse BIOS region size to 28MB
Increase BIOS region(SI_BIOS) from 16MB to 28MB to make more spaces for
upcoming payloads.

BUG=b:121169122
TEST=Build and boot up fine into OS on sarien and arcada platform.

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I4b03e20a485cb819b468c00e68f1539e92731237
Reviewed-on: https://review.coreboot.org/c/31054
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-01-25 11:21:39 +00:00
John Zhao 57aa8b6a2b soc/intel/apollolake: Override GLK usb clock gating register
It was observed system suspend/resume failure while running
RunInDozingStress. Apply correct GLK usb clock gating register
value to mitigate the failure.

BRANCH=octopus
BUG=b:120526309
TEST=Verified GLK clock gating register value after booting
to kernel.

Change-Id: I50fb16f5ab0e28e79f71c7f0f8e75ac8791c0747
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/30918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-01-25 11:21:20 +00:00
Lucas Chen 49c0e6416a mb/google/kahlee/variants/aleena: Add support Synaptics touch pad
Add support Synaptics touch pad for Aleena/Kasumi.

BUG=b:122549449
BRANCH=master
TEST= Check if synaptics touch pad working in ChromeOS.

Change-Id: Icab1b312f1943b27037ef458044ce9e7172919ee
Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/31064
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-25 11:20:18 +00:00
Jan Tatje 83a127a189 sb/intel/common: Show "Add gigabit ethernet firmware" only for boards that need it
Hide "Add gigabit ethernet firmware" option for boards that do not
use GbE firmware in GbE section.

The option is now hidden by default and can be reenabled on a
per-board basis by selecting MAINBOARD_USES_IFD_GBE_REGION in the
mainboards Kconfig.

The following boards seem to use this:
mb/roda/rv11
mb/ocp/wedge100s
mb/ocp/monolake
mb/lenovo/x230
mb/lenovo/x220
mb/lenovo/x201
mb/lenovo/x200
mb/lenovo/t530
mb/lenovo/t520
mb/lenovo/t430s
mb/lenovo/t430
mb/lenovo/t420s
mb/lenovo/t420
mb/lenovo/t400
mb/kontron/ktqm77
mb/intel/saddlebrook
mb/intel/kblrvp
mb/intel/dg43gt
mb/intel/dcp847ske
mb/intel/coffeelake_rvp
mb/intel/camelbackmountain_fsp
mb/hp/revolve_810_g1
mb/hp/folio_9470m
mb/hp/compaq_8200_elite_sff
mb/hp/8770w
mb/hp/8470p
mb/hp/8460p
mb/hp/2760p
mb/hp/2570p
mb/google/sarien
mb/facebook/watson
mb/compulab/intense_pc
mb/asus/maximus_iv_gene-z

The boards were identified by looking at devicetree.cb, but this
list is possibly still incomplete.

Change-Id: Ibfb07902ad93fe5ff2bd4f869abcf6579f7b5a79
Signed-off-by: Jan Tatje <jan@jnt.io>
Reviewed-on: https://review.coreboot.org/c/30790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-25 11:19:51 +00:00
Elyes HAOUAS d2abe9314e mb/{kontron,supermicro}: Use pcidev_on_root()
Change-Id: I61b3e5c92830f02d61a108dadde25ff261099e57
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31051
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2019-01-25 11:18:45 +00:00
Nico Huber b32347415d nb/intel/sandybridge/acpi: Add RMRR entry for iGPU
The iGPU always needs access to its stolen memory. For proper IOMMU
support, we have to make the OS aware of that.

Directly below TOLUD lies the data stolen memory (BDSM) followed by
the GTT stolen memory (BGSM), the iGPU needs access to both.

Change-Id: I391d0a5f1ea14bc90fbacabce41dddfa12b5bb0d
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/29668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-01-25 09:45:46 +00:00
Angel Pons e583dd3d51 src/mb/asrock/../g41m-s3: Remove spurious devices
This fixes errors regarding "PCI: Leftover static devices"

Change-Id: Ie45fe6934df4a9dad4c8f6b1af665034853c4c5a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-24 22:25:05 +00:00
Lijian Zhao a31872c615 ec/google/wilco: Turn on wake up from lid
Send required EC command to enable ACPI S3 wake up from lid switch.

BUG=b:120748824
TEST=Put Sarien system into S3 and then wake up from lid switch
successful.

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I13f3469847b0886147b8b624311a1ece796f847b
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/30824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-01-24 22:03:32 +00:00
Arthur Heymans 2bbffc0442 mb/*/*/devicetree.cb: Move the ioapic device under the LPC bridge
This fixes spurious lines "child IOAPIC: 02 not a PCI device" and
IOAPIC as leftover device.

Change-Id: Id8010c84c45f0859508e7564c0eaa501904b7043
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/31041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-24 21:46:51 +00:00
Patrick Georgi ff28371521 Revert "soc/intel/denverton_ns: Rewrite pmutil using pmclib"
This reverts commit ab1227226e.

There were significant changes around soc_reset_tco_status() that this
code needs to be adapted to.

Change-Id: I563c9ddb3c7931c2b02f5c97a3be5e44fa873889
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/31071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-24 15:23:47 +00:00
Sumeet Pawnikar 062fdf13b8 mb/google/sarien/variants: Set tcc offset value
Set tcc offset value to 5 degree celsius for Sarien system.

BRANCH=None
BUG=b:122636962
TEST=Built and tested on Sarien system

Change-Id: I06fbf6a0810028458bdd28d0d8a4e3b645f279ca
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/31037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
2019-01-24 14:21:37 +00:00
Ronald G. Minnich d19f4e50aa riscv: ARCH_RISCV_RV{32,64} selects ARCH_RISCV
ARCH_RISCV_RV{32,64} will now select ARCH_RISCV.

Change-Id: Ia7a1a8f0bfab20e91b8429dd6dd3e9a4180a0a5b
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>
2019-01-24 14:21:01 +00:00
Julien Viard de Galbert 053ea60682 soc/intel/denverton_ns: Configure MCA
Change-Id: I101eb4f008a13af92bac5ed738a8d1f1f8c65eba
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/c/25433
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-24 14:05:10 +00:00
Julien Viard de Galbert 15b570b716 soc/intel/denverton_ns: Use cpulib in cpu.c
Also remove duplicate code

Change-Id: I45da6363a35cf6f5855906bb97ed023681d36df7
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/c/25432
Reviewed-by: Vanny E <vanessa.f.eusebio@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Guckian
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-24 14:04:13 +00:00
Julien Viard de Galbert 2f66c709f4 soc/intel/denverton_ns: Enable Fast Strings
Change-Id: I7cee3c40299abf14a24128b1ac14f1823f87a0e1
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/c/25431
Reviewed-by: Vanny E <vanessa.f.eusebio@intel.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: David Guckian
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-24 14:03:47 +00:00
Julien Viard de Galbert ab1227226e soc/intel/denverton_ns: Rewrite pmutil using pmclib
Change-Id: If31e7102bf1b47c7ae94b86d981b762eda0a19e5
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/c/25427
Reviewed-by: David Guckian
Reviewed-by: King Sumo <kingsumos@gmail.com>
Reviewed-by: Vanny E <vanessa.f.eusebio@intel.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-24 13:59:14 +00:00
Julien Viard de Galbert c2540a958b soc/intel/common/block/acpi: fix P-States extra entry
The ratio_max step is appearing twice when (ratio_max - ratio_min)
is evenly divisible by the ratio step.

This is because in this case there are no rounding down of ratio_max in
the for loop.

Thanks Jay Talbott for the step calculation algorithm.

Change-Id: I91090b4d87eb82b57055c24271d679d1cbb3b7a7
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/c/25429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-24 13:58:24 +00:00
Nico Huber 016ef9e9bc ec/kontron: Add support for Kontron kempld
A programmable logic device used by Kontron as EC on their COM express
modules. The name `kempld` is taken from Linux kernel sources, as is the
I2C driver. The meaning of the acronym is unclear, probably: Kontron
Embedded Module PLD.

Change-Id: If9a0826c4a8f5c8cd573610c2d10561334258b36
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/29476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-01-24 13:56:25 +00:00
Duncan Laurie b2e610011c mb/google/sarien: Fix recovery mode detection
In order to support the physical recovery GPIO on sarien it needs
to enable the option VBOOT_PHYSICAL_REC_SWITCH and set the GPIO
number in the coreboot table appropriately so that depthcharge can
correctly determine the GPIO number.  The same is done for the
write protect GPIO in this table.

Additionally since we are reading a recovery request from H1 it
needs to cache the result since H1 will only return true on the
first request.  All subsequent queries to H1 will not indicate
recovery.  Add a CAR global here to keep track of the state and
only read it from H1 the first time.

BUG=b:121380403
TEST=test_that DUT firmware_DevMode

Change-Id: Ia816a2e285d3c2c3769b25fc5d20147abbc71421
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31043
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-24 13:55:21 +00:00
Karthikeyan Ramasubramanian 2b27e236b5 mb/google/octopus/bobba: Add support to handle PEN_EJECT event
Enable gpio_keys driver for bobba and add required configuration in the
device tree to handle the pen eject event.

BRANCH=octopus
BUG=b:117953118
TEST=Ensure that the system boots to ChromeOS. Ensure that the stylus tools
open on pen eject. Ensure that the system wakes on Pen Eject. Ensure that
the system enters S0ix and S3 states after the pen is ejected. Ensure that
the system enters S0ix and S3 states when the pen remains inserted in its
holder. Ensured that the system does not wake when the pen is inserted.
Ensure that the suspend_stress_test runs successfully for 25 iterations
with the pen placed in its holder.

Change-Id: I768b89d2b45f4dcab6d235b11ce00544a827f22d
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/30108
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-01-24 13:55:02 +00:00
Karthikeyan Ramasubramanian c4427393c5 drivers/generic/gpio_keys: Add trigger for wakeup event action
Currently without any trigger the wakeup event is generated on both the
rising and falling edges of the GPIO input. Add support to specify the
trigger explicitly so that the configuration can be passed to the
kernel.

BRANCH=octopus
BUG=b:117953118
TEST=Ensure that the system boots to ChromeOS. Ensure that the stylus tools
open on pen eject. Ensure that the system wakes on Pen Eject. Ensure that
the system enters S0ix and S3 states after the pen is ejected. Ensure that
the system enters S0ix and S3 states when the pen remains inserted in its
holder. Ensured that the system does not wake when the pen is inserted.
Ensure that the suspend_stress_test runs successfully for 25 iterations
with the pen placed in its holder and ejected from its holder.

Change-Id: Ifb08ba01106031aa2655c1ae2faab284926f1ceb
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@chromium.org>
Reviewed-on: https://review.coreboot.org/c/30451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-01-24 13:54:51 +00:00
Karthikeyan Ramasubramanian cff4507289 soc/intel/gpio: Enable configuring GPIO debounce duration
Add new helper macros to enable configuring debounce duration for a
GPIO input. Also ensure that the debounce configuration is not masked
out.

BRANCH=octopus
BUG=b:117953118
TEST=Ensure that the system boots to ChromeOS. Ensure that the debounce
duration is configured as expected.

Change-Id: I4e3cd7744867bcfbaed7d3d96fed4e561afb2cec
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@chromium.org>
Reviewed-on: https://review.coreboot.org/c/30450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-01-24 13:54:45 +00:00