Commit Graph

29029 Commits

Author SHA1 Message Date
Keith Short 00dbf449c9 coreboot: Run mainboard specific code before Cr50 reset
When coreboot checks the TPM and key-ladder state it issues a reboot of
the Cr50 with a delay parameter.  Older Cr50 code doesn't support the
delay parameter and reboots immediately, which prevented coreboot from
running the mainboard specific code needed for the AP to come back up.

This change calls mainboard_prepare_cr50_reset() prior to sending the
VENDOR_CC_IMMEDIATE_RESET command.

This change also fixes a false error message from the coreboot log that
indicated "Unexpected Cr50 TPM mode 3" when the Cr50 key ladder is
disabled.

BUG=b:130830178
BRANCH=none
TEST=build coreboot on sarien and grunt platforms.
TEST=Load Cr50 v3.15, run 'gsctool -a -m disable; reboot'.  Verify
corebot send the
VENDOR_CC_IMMEDIATE_RESET command and that the AP boots normally.
Verify event log shows "cr50 Reset Required"
TEST=Force Cr50 automatic update.  Verify event log shows "cr50 Update
Reset".

Change-Id: Ib05c9cfde8e87daffd4233114263de5b30822872
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-23 10:21:24 +00:00
Lijian Zhao c5d734b3f9 soc/intel/common/acpi: Add dynamic method around sleep
Declare plaform level hook method before and after system sleep for
possible power management related usage.

BUG=N/A
TEST=pass with make what-jenkins-does

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: Ie63711748b6dbb99d34910824f2059464543e162
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32366
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-23 10:20:29 +00:00
Elyes HAOUAS 31438f73c0 cpu/intel/speedstep/acpi: Use get_ia32_fsb_x3() function
Change-Id: Ie8c5d5f7dd5b43becc144fd5e62d7de2f1ed3b80
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31432
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-23 10:19:37 +00:00
Arthur Heymans c58525ee46 configs: Add a target to buildtest the ivybridge mrc.bin bootpath
Change-Id: Iff15e9586cd3e39850d986582b5943cbb8a184a7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32384
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-04-23 10:18:44 +00:00
Arthur Heymans 3c61304a9f arch/x86/car.ld: Make the vboot tpm log symbols conditional
Without VBOOT_MEASURED_BOOT there is no need for these symbols.

Change-Id: I96391b7817c79f760713c67bc469164b5514879e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-23 10:18:09 +00:00
Elyes HAOUAS 01912201a4 nb/intel/i945: Check if interleaved even if rank #4 size is zero
Tested config:
Interleaved (config; status before, after):
 DIMM{0 + 2}: ok, ok
 DIMM{0 + 3}: Nok, ok
 DIMM{1 + 2}: ok, ok
 DIMM{1 + 3}: Nok, ok
 DIMM{1 + 2 + 3}: ok, ok
 DIMM{0 + 2 + 3}: ok, ok
 DIMM{0 + 1 + 2}: ok, ok
 DIMM{0 + 1 + 3}: Nok, ok

Not Interleaved:
 DIMM{0 + 1 + 3}: Nok, Nok
 DIMM{0 + 1 + 2}: ok, ok (with single ranked)
 DIMM{0 + 1 + 2}: Nok, Nok (with only dual ranked)
 DIMM{0 + 2 + 3}: Nok, ok
 DIMM{1 + 2 + 3}: ok, ok

Change-Id: Ibf130a3d4b6f8fa816f7a5f06822a9b8807be3d4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31007
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-04-23 10:13:34 +00:00
Matt DeVillier d6d6771b97 sb/intel/bd82x6x: fix linking for non-native raminit case
Commit 45d4b17 [nb/intel/sandybridge: Move southbridge code to bd82x6x]
moved early_pch_init() to the southbridge, but failed to include
early_pch.c for the non-native raminit case, which now fails to link.
As all boards default to native raminit, this was missed by the autobuilder.

Adjust early_pch.c to be compiled regardles of ram init type used

Test: build/boot google/stout with MRC ram init selected

Change-Id: I50db30fda9a1099fb434c04ea97bcc38f8455233
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-04-23 10:13:14 +00:00
Elyes HAOUAS 420d7e009d ich7/i945: Use full_reset()
For full reset, use already defined full_reset() function.

Change-Id: Iec7dcf285f3cb1cdc8f48d348ff8496879625db5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-04-23 10:12:24 +00:00
Arthur Heymans d893a2635f sb/intel/lynxpoint: Enable LPC/SIO setup in bootblock
This allows for serial console during the bootblock and enables
console in general for the bootblock.

Change-Id: I5c6e107c267a7acb5bf9cbeb54eb5361af3b6db4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30315
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-23 10:12:02 +00:00
Kyösti Mälkki 63bc18e328 soc/amd/common: Remove AmdReadEventLog()
Parameter passing is incorrect here, it should pass
complete StdHeader instead of attempting to fill
in HeapStatus that should be treated as a field private
to AGESA, based on where it is defined in the header
files.

Furthermore the while() loop did not evaluate the
return value. Feature can be brought back at a later
date after someone verifies it actually works correctly
across different stages.

Change-Id: Ib243b275f8700ecaeb330772c795d305c61899c5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31484
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-23 10:10:45 +00:00
Kyösti Mälkki 6e512c4d7a soc/amd/common: Introduce agesa_execute_state()
Each entrypoint to AGESA goes through the same sequence
and have same the function signature.

To avoid introducing bunch of preprocessor magic, rename
all the agesawrapper_amdXXX() functions that are actual
entrypoints to AGESA API, make them static, and provide
a single exposed entry function agesa_execute_state().

Change-Id: I96ae1874132da3843aa42c2f4e8a59ec771d3893
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31483
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-23 10:10:34 +00:00
Roy Mingi Park ba851170fb mb/google/sarein: Add power control for Arcada touchscreen
This change will save touchscreen power leakage 2-3mW in S0iX and
increase T2 display time delay to meet display panel requirement.

BUG=b:129899315
TEST= Measure touchscreen power from Arcada during S0iX

Change-Id: I4b8f3fdc0d107b080c5febe6fa5d29ea5d1ed0fc
Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-04-23 10:10:19 +00:00
Lijian Zhao e98a751823 smbios: Add memory type 9 system slot support
Add SMBIOS type 9 system slots into coreboot, the definiation is up to
date with SMBIOS spec 3.2

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: Ibcfa377c260083203c1daf5562e103001f76b257
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-04-23 10:09:35 +00:00
Kane Chen 3717256d5a soc/intel/cannonlake: Enable PlatformDebugConsent by Kconfig
This change is mainly to control PlatformDebugConsent FSP UPD.
PlatformDebugConsent is enabled if SOC_INTEL_CANNONLAKE_DEBUG_CONSENT != 0.
PlatformDebugConsent in FspmUpd.h has the details.

BUG=b:130203864
TEST=boot ok and PlatformDebugConsent can be controlled by Kconfig

Change-Id: Ib845b5e42bc78fb352a0c97c6301f2aeca522f29
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32297
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-23 10:08:57 +00:00
Kane Chen f5e8b29be6 soc/intel/common: Add SOC_INTEL_DEBUG_CONSENT to control debug interface
SOC_INTEL_DEBUG_CONSENT config is generally to enable default debug
interface of SoC.

Ex: USB DBC, DCI debug interface on cnl, whl, cml.

Change-Id: I313d80d6c63fd37164c63f78e9e69d3cb4a5566b
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32337
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-23 10:08:45 +00:00
Frans Hendriks 0556f6132b soc/intel/braswell/acpi/lpss.asl: Remove SPI1 and PWM asl code
Linux remains using SPI1 and PWM ASL even if these devices are disabled.
SPI1 and PWM are disabled by Intel FSP.
Remove ASL code.

BUG=N/A
TEST=Boot Ubuntu on Intel CherryHill CRB

Change-Id: Iec2ca7520081d00bf7a53d58ee054aa6f23e5606
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29417
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2019-04-23 10:07:38 +00:00
Elyes HAOUAS 34564ed154 ACPI: Clarify serial bus revision and specific revision
Serial bus revision [Byte 3] and serial bus specific revision [Byte 9]
are not the same.

Change-Id: I366f62e6aa0e9c0dfbc1ec17adeebc42a0e777eb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-04-23 10:06:35 +00:00
Patrick Rudolph da9302a2c4 nb/intel/sandybridge: Drop pch.h from sandybridge.h
Include pch.h in the source files instead in sandybridge.h.

Tested on Lenovo T520 (Intel Sandy Bridge).
Still boots to OS, no errors visible in dmesg.

Change-Id: I9e5b678e979a8d136d8d00b49486d0a882f77d81
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-04-23 10:06:01 +00:00
Aamir Bohra 78fbe3d831 soc/intel/cannonlake: Add null reference check for Cnvi and Xdci
Change-Id: I2e1011d9ac93ed764b6c2aa425928a972ec2aa43
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32322
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-23 10:04:42 +00:00
Elyes HAOUAS 5f28639a93 crossgcc: Update acpica to version 20190215
Support for ACPI specification version 6.3:

Add PCC operation region support for the AML interpreter. This adds PCC
operation region support in the AML interpreter and a default handler for
acpiexec. The change also renames the PCC region address space keyword to
PlatformCommChannel.

Support for new predefined methods _NBS, _NCH, _NIC, _NIH, and _NIG.
These methods provide OSPM with health information and device boot
status.

PDTT: Add TriggerOrder to the PCC Identifier structure. The field value
defines if the trigger needs to be invoked by OSPM before or at the end
of kernel crash dump processing/handling operation.

SRAT: Add Generic Affinity Structure subtable. This subtable in the SRAT
is used for describing devices such as heterogeneous processors,
accelerators, GPUs, and IO devices with integrated compute or DMA
engines.

MADT: Add support for statistical profiling in GICC. Statistical
profiling extension (SPE) is an architecture-specific feature for ARM.

MADT: Add online capable flag. If this bit is set, system hardware
supports enabling this processor during OS runtime.

New Error Disconnect Recover Notification value. There are a number of
scenarios where system Firmware in collaboration with hardware may
disconnect one or more devices from the rest of the system for purposes
of error containment. Firmware can use this new notification value to
alert OSPM of such a removal.

PPTT: New additional fields in Processor Structure Flags. These flags
provide more information about processor topology.

NFIT/Disassembler: Change a field name from "Address Range" to "Region
Type".

HMAT updates: make several existing fields to be reserved as well as
rename subtable 0 to "memory proximity domain attributes".

GTDT: Add support for new GTDT Revision 3. This revision adds information
for the EL2 timer.

iASL: Update the HMAT example template for new fields.

iASL: Add support for the new revision of the GTDT (Rev 3).

More changes in this version at https://acpica.org/node/166

Change-Id: I3a825f568423c3a703ad1c13da976af322ed9de2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-04-23 10:03:12 +00:00
Elyes HAOUAS b1f4d52580 crossgcc: Update CMake to version 3.14.2
Release Note :
https://cmake.org/cmake/help/v3.14/release/3.14.html
"The FindFontconfig module added by 3.14.0 accidentally used uppercase
FONTCONFIG_* variable names that do not match our conventions.
3.14.1 revises the module to use Fontconfig_* variable names.
This is incompatible with 3.14.0 but since the module is new in the 3.14
series usage should not yet be widespread"

Change-Id: Ief7f5e8309597093f061789926bd3bd2ed3aec2d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-04-23 10:03:06 +00:00
Elyes HAOUAS 095c2617a3 crossgcc: Upgrade GCC to version 8.3.0
Change-Id: I135fd62619fc33bbc3fd29e93eeafcf695700c9a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-04-23 10:03:01 +00:00
Elyes HAOUAS cd4fe0f718 src: include <assert.h> when appropriate
Change-Id: Ib843eb7144b7dc2932931b9e8f3f1d816bcc1e1a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/26796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: David Guckian
2019-04-23 10:01:36 +00:00
Elyes HAOUAS 351e3e520b src: Use include <console/console.h> when appropriate
Change-Id: Iddba5b03fc554a6edc4b26458d834e47958a6b08
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: David Guckian
2019-04-23 10:01:21 +00:00
Elyes HAOUAS 20eaef024c src: Add missing include 'console.h'
Change-Id: Ie21c390ab04adb5b05d5f9760d227d2a175ccb56
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-04-23 10:00:39 +00:00
Elyes HAOUAS 7118701e96 sb/intel/i82801gx/lpc: Use {read,write}_pmbase32 and lpc_get_pmbase
Also use macros instead of magic numbers.

Change-Id: I00bd687c487894c72d4e4363774dbcdfaf62dd54
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-04-23 09:59:34 +00:00
Arthur Heymans 7a50554e29 src/mainboard/{foxconn/d41s,intel/d510mo}: Use pci_or_config
The pci_or_configx function makes the code shorter and more readable.

Change-Id: Ic1ba250f8ac9fb75cf3252aec18af80842bda7dd
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-04-23 09:57:39 +00:00
Thejaswani Putta 6f5225c7e0 Klocwork: Fix the Null pointer derefernce found by klocwork
Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.com>
Change-Id: I15973ac28e9645826986cf63d2160eedb83024e4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32290
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-23 09:56:37 +00:00
Robin Broda 21f9b3ecd7 util/intelmetool: Add Intel Cannon Lake PCH HECI Controller to supported PCI devices
Signed-off-by: Robin Broda <robin@broda.me>
Change-Id: I0f9e83b3bdf35e3e3e119ffcb93b092121a67666
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32285
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-04-23 09:55:31 +00:00
Arthur Heymans b524dfca40 payloads/U-Boot: Update to the latest stable 2019.4
Change-Id: I4740aa80e3c0faf9b18730390af778abcc92aac3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-04-23 09:54:40 +00:00
Arthur Heymans 89d4a601f5 payload/U-Boot: Fix generating a default config on the master branch
The name of the default configuration file for x86 coreboot changed.

Change-Id: I6544142a70bd3e1e13ee52eccbd5335f8375a4f6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-04-23 09:54:34 +00:00
Arthur Heymans f4af723fd8 payloads/U-Boot: Use a phony target for checking out a revision
Change-Id: I5ea4df33545f69c06e4ae2158a1a6c14ead784a7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-04-23 09:54:27 +00:00
Arthur Heymans 52cb8a7fec payloads/U-Boot: Unexport the coreboot_exports
Without this U-Boot ends up overwriting the coreboot .config when
generating a configfile.

Change-Id: I62fc0aa3ede0287ffc96915182a2ed5a4877f29d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-04-23 09:54:15 +00:00
Sheng-Liang Pan 8b784004d3 mb/google/octopus: Add keyboard backlight support for Droid/Blorb
Droid/Blorb supports keyboard backlight feature, so enable the ASL code.

BUG=b:130330141
BRANCH=octopus
TEST=Build and boot to OS, verify that the string 'KBLT' is in the DSDT.

Change-Id: I74684e3905d34b61fa4b851798dbca018f986e5a
Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-23 09:53:58 +00:00
Philipp Hug 6b6dc6eddd hifive-unleashed: update documentation to match current state
Signed-off-by: Philipp Hug <philipp@hug.cx>
Change-Id: I3f1b7dd4ef52a64c9a222f2d5cffe2b73806fe4e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-04-23 09:34:09 +00:00
Lijian Zhao 7f1a0e6b4c Revert "soc/intel/cannonlake: Enable coreboot MP PPI service for WHL/CML"
This reverts commit 41dad286d8. The change will make s0ix fail on Sarien/Arcada Platform.

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I169bc6f41fba82fcf515267e8e1d08aa5ee2dce4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32391
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-22 21:35:45 +00:00
Hung-Te Lin 69eae2762f board/kukui: Support ADC value for NC
When the components like LCM ID are not installed (i.e., NC), ADC will
return some value with much larger variation from standard value (out of
the tolerance we set). To support that, we should check tolerance only
on non-NC voltages.

Also improve the error messages so we can see the ADC raw values
instead of simple assertion error (which makes debugging more difficult
since we have to build another firmware image just to print the values).

BUG=None
TEST=Booted on Kukui and got correct SKU ID for NC LCMID.
BRANCH=None

Change-Id: I8d00956e0e3b48ddbcaa505dd3ade24720c3b4ad
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32353
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-22 19:56:23 +00:00
Roy Mingi Park e3f5f2155a mb/google/sarien: Configure both GPP_H12 and GPP_H13 for SSD on Arcada
Currently, Arcada only supports D3hot during S0iX and there is leakage
power around 5~10mW depending on SSD vendors.
To support D3cold for SSD during S0iX, one MOSFET will be added on DVT2
and two GPIOs are required to be configured.
GPP_H13 is to control SSD_SCP_PWR_EN(power enable) and GPP_H12 is to
control SSD reset.

BUG=b:130741066
TEST=Measure SSD power during S0iX from Arcada(DVT2)

Change-Id: I868590e9e85d5df07930a3681884e3fc3a5c4d50
Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32361
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-22 18:00:13 +00:00
Arthur Heymans c94ba798d6 arch/x86/car.ld: Also check mrc.bin heap for Ivybridge
Sandy- and ivybridge use the same mrc.bin that has the heap in an
awkward location.

Change-Id: If985a48c6703c8a86d8051e67595cf0fd409d99a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-04-22 13:40:14 +00:00
Felix Singer 1db39a4466 drivers/intel/fsp2_0: Set basename for FSP binaries
Since there is no standardized naming scheme for the
FSP binaries, the option USE_FSP_REPO can't be used
on some platforms, because some of the filenames differ
and the build process awaits "Fsp_*.fd" as filename.

As a workaround, add the option -n to SplitFspBin.py,
which defines the basename.

Change-Id: Idc684ad00033ffafd1090fc32b23549ce9603b4f
Signed-off-by: Felix Singer <migy@darmstadt.ccc.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30930
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-21 23:35:45 +00:00
Arthur Heymans 77d5e7481b nb/intel/haswell: Add an option for where verstage starts
Previously Haswell used a romcc bootblock and starting verstage in
romstage was madatory but with C_ENVIRONMENT_BOOTBLOCK it is also
possible to have a separate verstage.

This selects using a separate verstage by default but still keeps the
option around to use verstage in romstage.

Also make sure mrc.bin is only added to the COREBOOT fmap region as it
requires to be run at a specific offset. This means that coreboot will
have to jump from a RW region to the RO region for that binary and
back to that RW region after that binary is done initializing the
memory.

Change-Id: I3b7b29f4a24c0fb830ff76fe31a35b6afcae4e67
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/26926
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-21 23:32:37 +00:00
Arthur Heymans 8e646e74b3 cpu/intel/haswell: Use C_ENVIRONMENT_BOOTBLOCK
This puts the cache-as-ram init in the bootblock.
Before setting up cache as ram the microcode updates are applied.

This removes the possibility for a normal/fallback setup although
implementing this should be quite easy.

Tested on Google peppy (Acer C720).

Setting up LPC in the bootblock to output console on SuperIOs is not
done in this patch, hence BOOTBLOCK_CONSOLE is not yet enabled by
default.

Change-Id: Ia96499a9d478127f6b9d880883ac41397b58dbea
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/26859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-04-21 23:31:26 +00:00
Arthur Heymans c4772b9fd7 cpu/x86: Move checking for MTRR's as a proxy for proper CPU reset
Checking for empty MTRR_DEF_TYPE_MSR as a proxy for proper CPU reset
is common across multiple platforms. Therefore place it in a common
location.

Change-Id: I81d82fb9fe27cd9de6085251fe1a5685cdd651fc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-21 23:29:29 +00:00
Martin Roth 0800194f95 ipxe: Update stable version from 2017.3 to to 2019.3
Updating iPXE stable from commit id fd6d1f4660:
Fri Mar 31 09:08:13 2017 +0300
[thunderx] Use ThunderxConfigProtocol to obtain board configuration

to commit id ebf2eaf515:
Mar 18 10:24:08 2019 +0000
[intel] Add PCI ID for I219-V and -LM 6 to 9

This brings in 176 new commits

Change-Id: Id35fee38e0e61897a623dae35f42fc580e32d3ee
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-04-21 23:15:42 +00:00
Marshall Dawson 6d3b7e6f62 soc/amd/stoneyridge: Fix gnvs aoac initialization
Correct the SD and SATA assignments.

TEST=Boot Grunt
BUG=b:130788333

Change-Id: Ib75e1dbb0cd7f90a8d297d11d3a7c3bad47a8d21
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2019-04-21 23:14:45 +00:00
Arthur Heymans b328209330 nb/intel/nehalem: Hide some raminit output messages
Hide some debug output behind CONFIG_DEBUG_RAM_SETUP. That way the
pre-ram console does not overflow.

Change-Id: Idc425f4d10443f6ee7f9b4da67eb6542069cc40c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-04-20 04:27:01 +00:00
Elyes HAOUAS 4c15ea5bab mb/facebook/watson: Don't use deprecated IS_ENABLED
Change-Id: Ia4b7311f30f8ec951d02d3c31c30cf8895ed0eb2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-04-20 04:22:46 +00:00
Tony Huang 6cd9e631b0 mb/google/octopus/variants/baseboard: Disable unused I2C 1
I2C 1 is not being used in any of the octopus variants, so disable it.

BUG=none
BRANCH=octopus
TEST=Verify on meep and bloog
     reboot and s0ix suspend successfully

Change-Id: I7ed5065cfd0b9780d13feb27cc78b8090d7a03a6
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
2019-04-20 00:55:54 +00:00
Nathan_chen 5397f194cc mb/google/arcada: Set psys_pmax to 140W
arcada is designed to operate at max power of 140 Watt. Hence set psys_max to 140W.

BUG=b:124792558
TEST=Build and boot arcada.

Change-Id: I280dfb81b3e25c7619a68db487e2b18867f52fda
Signed-off-by: nathan chen <nathan_chen@wistron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32335
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-04-20 00:55:07 +00:00
Elyes HAOUAS 75380d3a16 src/mb/Kconfig: Fix PCI subsystem IDs
References to MAINBOARD_PCI_SUBSYSTEM_{DEVICE_ID,VENDOR_ID} were removed
in commits

 dbd3132 sb/intel/{i82801g/i/j,bd82x6x}: Make use of generic set_subsystem()
 00bb441 sb/intel/lynxpoint: Remove PCI bridge function

Change-Id: I72bba8406eea4a264e36cc9bcf467cf5cfbed379
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32107
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-19 17:48:15 +00:00