Update definition to be more intuitive and extensible.
Port descriptors will be defined as individual entities and added
to the descriptor list as such.
BUG=b:281059446
TEST=builds
Change-Id: Ic5a06a7d1bdb9123a0a242a571f094ac3233d7b2
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79627
Reviewed-by: Tim Van Patten <timvp@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Eric Lai <ericllai@google.com>
When an if block has curly braces, the corresponding else block should
also have curly braces.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie1979873142469b1482097f9b4db487541a1b7a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Since we have chipset devicetrees for all SoCs that include this code in
the build, we can use the DEV_PTR macro instead of using
pcidev_path_on_root to get the device struct pointer. We can also use
the is_dev_enabled function instead of checking the value of the enabled
element of the device struct directly.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5dcd92399e2d3f304352f2170dd3ef8761e86541
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79672
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since we have chipset devicetrees for both SoCs supported by the
Stoneyridge code, we can use the DEV_PTR macro instead of using
pcidev_path_on_root to get the device struct pointer. We can also use
the is_dev_enabled function instead of checking the value of the enabled
element of the device struct directly.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifb787750ebc6aa2fef9d3be0e84e6afcffdc2ac1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79671
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Make it possible to enable C1e from the devicetree by adding
`c1e_enable`. C1e was disabled by ea2a38be32
for all RPL SOCs to reduce noise.
This will ensure that boards that disabled it based on CPUID are unchanged.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I758621393cb39345c2ba7b19a32872e84e1c5a19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77088
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Identify PCH type by LPC device ID. This allows to identify
the PCH without including northbridge headers.
Tested: Lenovo X220 still boots.
Change-Id: Ic3e15c1d8d4b1d1012d6204cc65de92d91431fbe
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79145
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This is a preparation to make the next patch result in identical images
for timeless builds and also aligns Zork's DSDT more with Guybrush's
DSDT.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I46835b404be13f150c68680afb3fcc78639e08f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79652
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
For RMT build, add kconfig option to enforce Plan Of Record
restriction on DDR5 frequency & voltage settings.
Change-Id: Ibfcaaf47fec3bd5d8a858309918b3af2f8d976e9
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Add and use defines for 6 series and 7 series PCH PCH IDs.
Change-Id: I4de37d5817766b9bc4f5c2d4d472d3c456b14b29
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79546
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use same indent levels for switch/case in order to comply with the
linter.
Change-Id: I64361262e5b16419351fa139c8fdf04c5c07662d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The master is deprecated in favor of the main.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I58001819079bc880e8cde1c3a6756ff6c8a1c016
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This southbridge can route POST codes written to port 0x80 to either
LPC or PCI, but currently always route them to LPC. Change it so that
POST codes are routed to PCI if CONFIG(POST_DEVICE_PCI_PCIE) is
selected, LPC otherwise.
Rename the static function because POST codes no longer always go to
LPC.
Change-Id: I455d7aff27154d6821e262a21248e8c7306e2d61
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
update DTT settings for thermal control,the values before
Sensor1 and Sensor2 were set too high. Modify the protection
temperature to better meet DUT requirements.
BUG=b:291217859
BRANCH=none
TEST=emerge-rex coreboot
Change-Id: I8abc866c0d05a2437c34198e6b8fb4a58c1cb829
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79683
Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This patch follows the BWG recommendation (doc 729123) by clearing
the SPI SYNC_SS bit before disabling the WPD bit in
SPI_BIOS_CONTROL. This prevents boot hangs due to a 3-strike error.
Unable to follow this guideline would result into boot hang
(3-strike error).
BRANCH=firmware-rex-15709.B
TEST=Able to build and boot google/rex.
Change-Id: I18dbbc92554d803eea38ceb0b936a9da9191cb11
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Previous sleep state showing in serial log is a magic number.
In order to let users understand its meanings directly, add
the strings to describe the modes.
TEST=build, boot the device and check the logs:
without this change, the log is like:
[DEBUG] prev_sleep_state 0
with this change:
[DEBUG] prev_sleep_state 0 (S0)
Change-Id: Iabe63610d3416b3b6e823746e3ccc5116fabb17d
Signed-off-by: Marx Wang <marx.wang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78999
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
According to datasheet, EN_TCHSCR_PWR high --> SOC_TCHSCR_RST_R_L high
should over 5ms. And current measure result is 200us.
Set EN_TCHSCR_PWR to output high in bootblock to make it meet datasheet
requirment.
Measurement result of EN_TCHSCR_PWR high --> SOC_TCHSCR_RST_R_L high:
Power on --> 31.7 ms
Resume --> 38.7 ms
BUG=b:314245238
TEST=Measure the sequence
Change-Id: I56e455a980b465f27794b30df058ec0944befc2e
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79571
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Meteor Lake CPUs physical address size is 46 if TME is disabled, 42 if
TME is enabled but Meteor Lake SoC physical address size is always
42.
BUG=b:314886709
TEST=MTRR are aligned between coreboot and FSP
Change-Id: Ic63c93cb15d2998e13d49a872f32d425237f528a
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79666
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The physical address size of the System-on-Chip (SoC) can be different
from the CPU physical address size. These two different physical
address sizes should be used for settings of their respective field.
For instance, the physical address size related to the CPU should be
used for MTRR programming while the physical address size of the SoC
should be used for MMIO resource allocation.
Typically, on Meteor Lake, the CPUs physical address size is 46 if TME
is disabled and 42 if TME is enabled but Meteor Lake SoC physical
address size is always 42. As a result, MTRRs should reflect the TME
status while coreboot MMIO resource allocator should always use
42 bits.
This commit introduces `SOC_PHYSICAL_ADDRESS_WIDTH' Kconfig to set the
physical address size of the SoC for those SoCs.
BUG=b:314886709
TEST=MTRR are aligned between coreboot and FSP
Change-Id: Icb76242718581357e5c62c2465690cf489cb1375
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79665
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add probe DB_C_A_LTE/DB_C_A for Type-C Port C1 (daughter board).
DB_A is only used for skus without Type-C Port C1.
BUG=b:316048649
TEST=emerge-nissa coreboot
Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Change-Id: Ifb702c497740953144b43c56653da16fade1053f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79629
Reviewed-by: Kyle Lin <kylelinck@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Some GPIOs were not configured correctly according to the HW
spreadsheet provided by the HW team.
* GPP_B5/GPP_B6 use NF1, not NF2
* GPP_B23 should use NF2, no GPI
* GPP_D11 should be set to NC
* GPP_E21/22 should be using NF (previous NC)
* GPP_F17 is a GPO
* GPP_F18 should be an interrupt, not a NF
BUG=b:300690448,b:316180020
BRANCH=NONE
TEST=emerge-brox coreboot
Change-Id: I9e1e62adb79bd7fdab935afdbf2d23f9061b88aa
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Did a pass through HW team's brox speadsheet and aligned the gpio.c
file with it. The changes in this CL are to fix the pad's reset field
as needed. See "Intel SoCs" section in
https://doc.coreboot.org/getting_started/gpio.html for reset
definitions.
BUG=b:300690448,b:316180020
BRANCH=NONE
TEST=emerge-brox coreboot
Change-Id: I4285136184c648adb9dc97748bd6b01cba3f8ddd
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Did a pass through HW team's brox speadsheet and aligned the gpio.c
file with it. The changes in this CL include fixing the pulls for
GPIOs as necessary, making sure that it matches what is in the HW
team's spreadsheet.
BUG=b:300690448
BRANCH=NONE
TEST=emerge-brox coreboot
Change-Id: Ie50cb3c6fc85f1633c1afd1330c0e040e04b0ec1
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79704
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Did a pass through HW team's brox speadsheet and aligned the gpio.c
file with it. The changes here include changing the pad config to NC
because it is not being used in ChromeOS.
BUG=b:300690448
BRANCH=NONE
TEST=emerge-brox coreboot
Change-Id: I15471e4d7ff25c858b05ef024f15ca7c0b9e598e
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79703
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
datasheet: https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20221129/DS-00562-GD25LQ255E-Rev1.1.pdf
BUG=b:311336475
BRANCH=firmware-rex-15709.B
TEST=Build AP-firmware and test on karis, system can boot to OS.
Change-Id: Id952ba3a4a45a51571d3735cf6b5764cece2c5e4
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79087
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Add HDMI GPIO configuration to early GPIO list to support
VGA text o/p in Pre-RAM stage on HDMI.
BUG=b:316982707
TEST=Erase MRC cache and reboot, SOL text display on HDMI/eDP
Change-Id: Idb2af56baeb4d0ef9db5fc1c5dbcebecee6515e6
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79572
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Since the camera sensor and camera eeprom share GPP_A12, remove
the off timing to avoid issue of camera sensor loss, but this
will increase system power by 5mW.
(Before root cause, this is a short term workaround to unblock
function test.)
BUG=b:298126852
TEST=1. Run coldreboot/warmreboot check see if the camera sensor lost.
2. Run S0ix check to see if the camera function abnormal.
Change-Id: I49b6ecbfbf3dddd6575bdaaf9c8fd0ee6c09af25
Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79647
Reviewed-by: Jason Z Chen <jason.z.chen@intel.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
set slew rate to 1/8 for GT domain.
BUG=b:312405633
BRANCH=none
TEST=Able to build and boot google/screebo
Change-Id: Ib5cb07b7effc4a51c2119183010a03e026f639f8
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Some of the boards use the EC_SYNC pin to wake the AP but do not
advertise the pin as wake capable in the CREC _CRS resource. Relevant
boards were determined through empirical testing and inspection of gpio
configuration.
Update the ACPI tables for rex, brya, and brox based boards to advertise
their EC_SYNC pin as wake capable.
BUG=b:243700486
TEST=-Dump ACPI and verify ExclusiveAndWake share type is set when
EC_SYNC_IRQ_WAKE_CAPABLE is defined
-Wake Aviko via keypress and verify chromeos-ec as wake source
-Wake Screebo via lid open and verify chromeos-ec as wake source
Change-Id: I5828be7c9420cab6ae838272c8301c302a3e078c
Signed-off-by: Mark Hasemeyer <markhas@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79374
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This adds a default style for shell scripts. fmtsh now looks for this
when reformatting shell scripts.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I348f23badf302a48c851231a08c1ce4be94738a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78830
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
UART0 is routed to a USB-serial converter chip on the Onyx board, so
also enable this UART in the devicetree, so that the OS will be able to
use this UART.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7b2577d799fd82a0aa0c9b01324930237e204aa0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
FSP default value for LpDdrDqDqsReTraining is 1. For boards
that didn't set LpDdrDqDqsReTraining to any value, 0 was being
assigned and it caused black screen issue.
BUG=b:311450057
BRANCH=NONE
TEST=emerge-brox coreboot
Change-Id: I4a009076e50408a4f7ff16ddc96a0f2e47b09470
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79646
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
SATA_IDE_DEVID, AHCI_DEVID_MS and AHCI_DEVID_AMD are still kept even
though they're unused at the moment, but those might still be useful to
keep around, since the SATA controller can have different PCI device IDs
depending on in which mode it is in.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia05683b732d9748d9198225acaecbd4dc196733a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79577
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
GPP_B02 and GPP_B03 were set incorrectly previously.
This CL corrects these settings according to schematics.
BUG=b:305793886
TEST=Built FW image correctly.
Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: Id62f15f7a77ac43c72cc6b2645816d6c87133a0e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Only EC will use field "PANEL_PWRSEQ_EC_CONTROL".
Add this field in coreboot for align fw_config settings.
BUG=b:314245238
TEST=emerge coreboot pass
Change-Id: Icecb44a338ddc28027e362332c6a69cc9fd268d5
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79570
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
After confirm with thermal, only EC will reference FAN field in
fw_config.
Update the settings for align fw_config.
BUG=b:307822225
TEST=emerge coreboot pass
Change-Id: Id7c4cdba29c5500c06d0f2293495650bb14b9e9c
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79573
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Eran Mitrani <mitrani@google.com>
UART1 is selected for debug uart in Kconfig, it also needs to enabled
in devicetree. With this serial output doesn't stop during the device
enable step.
TEST:Build onyx_poc board
Change-Id: I7c910301c6eca5d3057785607139ac03b344bc15
Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Use same indent levels for switch/case in order to comply with the
linter.
Change-Id: I2dd0c2ccc4f4ae7af7dd815723adf757244d2005
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Eric Lai <ericllai@google.com>
Use same indent levels for switch/case in order to comply with the
linter.
Change-Id: I602cf024ec84b15b783d36014c725826f9d6595e
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79418
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use same indent levels for switch/case in order to comply with the
linter.
Change-Id: Icf41e823c42ffea7b73bdd9112081af4d1f94bc9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79417
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Eric Lai <ericllai@google.com>
These IDs are not used as crashlog data is not stored in CBMEM now.
(Ref CL: I43bb61485b77d786647900ca284b7f492f412aee
Title: soc/intel/common,mtl: Refactor BERT generation flow for crashlog)
BUG=b:298234592
TEST=Able to build REX.
Change-Id: Ie38571dece89a995d582099d34f0a1dd57cb936f
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
With earlier flow, a chunk of CBMEM region was allocated for each SRAM
e.g., PUNIT SRAM, SOC PMC SRAM and IOE PMC SRAM. Then entire SRAM
content was copied to dedicated CBMEM region. Later in acpi_bert.c, the
BERT table was getting created for each chunk of CBMEM. This flow was
not considering creating separate entries for each region of crashlog
records. It resulted in only the first entry getting decoded from each
SRAM.
New flow aims to fix this issue. With new flow, a simple singly linked
list is created to store each region of crashlog records from all
SRAMs. The crashlog data is not copied to CBMEM. The nodes are
allocated dynamically and then copied to ACPI BERT table and then
freed. This flow also makes the overall crashlog code much simpler.
BUG=b:298234592
TEST=With this change decoding crashlog show comprehensive details,
tested on REX.
Change-Id: I43bb61485b77d786647900ca284b7f492f412aee
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78257
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The optimization of sleep time in acpi code includes reducing the sleep
duration and increasing the polling frequency within the acpi _ON/_OFF
method. StorageD3Enable is activated in Google/Rex, and this
optimization results in a saving of approximately 25ms in D3cold resume
time, reducing it from around 160ms to 135ms.
BUG=b:296206467
BRANCH=firmware-rex-15709.B
TEST=boot test verified on google/rex
verified _ON/_OFF Method in SSDT.
verifid kernel log in s0ix test -
0000:00:06.0: PM: pci_pm_resume_noirq
Change-Id: I7ba960cb78b42ff0108a48f00206b6df0c78ce7a
Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Enable Acoustic noise mitigation for google/screebo and set slew rate
to 1/8 for IA domain and ignore the slew rate for SA domain.
BUG=b:312405633,
TEST=Able to build and boot google/screebo.
Before:
[SPEW ] AcousticNoiseMitigation : 0x0
[SPEW ] FastPkgCRampDisable for Index = 0 : 0x0
[SPEW ] SlowSlewRate for Index = 0 : 0x0
After:
[SPEW ] AcousticNoiseMitigation : 0x1
[SPEW ] FastPkgCRampDisable for Index = 0 : 0x1
[SPEW ] SlowSlewRate for Index = 0 : 0x2
Change-Id: Ib86939ab48c2c6e7d0491d7c1cb4a2c7c6a1b568
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79323
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Jon Murphy