Commit Graph

55505 Commits

Author SHA1 Message Date
Arthur Heymans b2ea2f29b8 soc/amd/genoa: Hook up BERT
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ie21bf8d436de19c23ae2176bf8d061564cd5b9cb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-12-15 09:30:51 +00:00
Felix Held b499c1f014 soc/amd/genoa: Hook up IVRS generation
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I0a6eaf43ab6da4bb4a0cc0bbefb5b75c206348f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2023-12-15 09:30:20 +00:00
Felix Held 80434a6984 soc/amd/genoa: configure FCH IRQ mapping
Add the code to configure the FCH IRQ mapping registers and provide the
IRQ name strings for each FCH IRQ mapping configuration register.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I282ae35ebc4d7754121ce4544b782e3cbe7e2256
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-12-15 09:30:05 +00:00
Morris Hsu 6a57210686 mb/google/brya/var/dochi: Enable LpDdrDqDqsReTraining
FSP default value for LpDdrDqDqsReTraining is 1. For boards
that didn't set LpDdrDqDqsReTraining to any value, 0 was being
assigned and it caused black screen issue.

BUG=b:302465393,b:315739133
TEST=Boot to OS with debug FSP, check LpDdrDqDqsReTraining = 1

Change-Id: I5d61301fddac6630bb1c48e992dd76e5cf02a272
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79533
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-12-15 01:59:55 +00:00
Naresh Solanki 933d2b0f13 lib: ramdetect: Add Kconfig PROBE_RAM
Previously ramdetect.c was compiled only for VENDOR_EMULATION.
Hence add Kconfig option PROBE_RAM which allows board outside
the scope of VENDOR_EMULATION to select and utilize  probe_ram
function to runtime detect usable RAM in emulation environment.

PROBE_RAM is default selected if VENDOR_EMULATION is set so
that existing boards under VENDOR_EMULATION scope are not
affected.

Other boards can explicitly select PROBE_RAM to use probe_ram.

TEST=Build mb/arm/rdn2 with PROBE_RAM selected & make sure
there is no any error.
Also checked qemu-aarch64 build to make sure build is success.

Change-Id: Id909ddaee6958cfa8a6c263a11f9a90d94710aa7
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-12-14 14:21:33 +00:00
Felix Held 18c83e1a94 mb/amd/onyx/mainboard: add FCH IRQ mapping table
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iab640551d6dd246884802ced948ff8c359d922a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79470
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-14 13:10:08 +00:00
Kun Liu d3ff66d1fb mb/google/rex/var/screebo: Change GPP_B14 from UP_20K to NONE
Change GPP_B14 from UP_20K to NONE for compatible
with DVT1 and DVT2 board

BUG=b:272447747
TEST=enable usb OC2 function to ensure USBA work normal

Change-Id: Ib7720980335660f423b3a74199ceedc113ec70df
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79431
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-14 13:08:59 +00:00
Jakub Czapiga 2d1b5c21f6 MAINTAINERS: Update Jakub's email address
jacz@semihalf.com is no longer available, czapiga@google.com should be
used instead.

Change-Id: I228b34c961ccf1546103f105276a75409825a432
Signed-off-by: Jakub Czapiga <czapiga@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79438
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-14 13:08:18 +00:00
Weimin Wu 5ba045c715 mb/google/nissa/var/anraggar: Update DTT settings for thermal control
Update DTT settings based on the suggestion of the thermal.

BUG=b:313833488
TEST=emerge-nissa coreboot

Change-Id: I2296990062cadc05202e3d1ab90af04234bda885
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-14 13:07:55 +00:00
Weimin Wu 6215ef47cd mb/google/nissa/var/anraggar: Enable USB3 Port3 for WWAN (LTE)
1. Ref to SCH, LTE use USB3 Port3, enable it.
2. Explicitly define the use of USB3 Port1 & USB3 Port2.

BUG=b:315061146
TEST=can pass PCIe Hardware Compliance Test

Change-Id: I03d6925020012fa740bbd0168a2f5b02ea6763b4
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-14 13:07:13 +00:00
Weimin Wu 133e3ee661 mb/google/nissa/var/anraggar: Change code style for register usb2_ports
Change code style to be compatible with Nissa's format:

register "option" = "{
    [0] = value /* comment */
    ...
}"

to

register "option[0]" = "value" /* comment */

BUG=none
TEST=abuild -v -a -x -c max -p none -t google/brya -b anraggar

Change-Id: I60659bd44813173f9b984216473a0919c5f331b8
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-14 13:06:13 +00:00
Felix Held 020d4b605e soc/amd/genoa/domain: generate SSDT entries for domains
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iadc37f2724a9be43cad1f1934403ebabd5cca245
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-12-14 13:05:41 +00:00
Felix Held d1065a3e64 soc/amd/genoa: Add basic ACPI support
- DSDT
- MADT
- SSDT CPUs

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0c86694ae83e9e6aa06a50a8a35bf2b24bc8ab65
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76530
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-14 13:04:28 +00:00
Felix Held 3d3e1cf060 vendorcode/amd/opensil/genoa_poc: add opensil_fill_fadt_io_ports
Add the opensil_fill_fadt_io_ports function to fill in the ACPI I/O
ports in FADT that openSIL configured.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I154a162cc8e048cadab693c0755e96c71a62983c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76529
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-14 13:03:17 +00:00
Yi Chou 27f888cda1 Update vboot submodule to upstream main
Updating from commit id db533497:
2023-12-05 20:09:44 +0000 - (host/lib/pkcs11: Remove superfluous 'nss' directory from include paths)

to commit id c0cb4bfa:
2023-12-08 09:14:32 +0000 - (signer: sign_android_image.sh should die when image repacking fails)

This brings in 3 new commits:
c0cb4bfa signer: sign_android_image.sh should die when image repacking fails
30e37712 tlcl: Add `TlclCreatePrimary()` support
12fa13e3 2api: Add firmware & kernel PCR support

Change-Id: I354c1d07c3b506069d5b64bc2fc476dadc36e0e2
Signed-off-by: Yi Chou <yich@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79484
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-14 08:29:08 +00:00
Kulkarni, Srinivas 7c6f1d570c vc/intel/raptorlake: Updating the FSP v4301.01 headers to Standard path
Move the existing FSP 4301.01 headers for Raptor Lake out of
subdirectory called 43101.01 to follow standard process.

Change-Id: I710f373acd37e9e0f8b50084a1a7e9fbda816e8c
Signed-off-by: Kulkarni, Srinivas <srinivas.kulkarni@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79475
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-12-14 03:23:31 +00:00
Felix Held fa3f1171ef soc/amd/genoa/acpi: update soc.asl
Add the missing parts in soc.asl. Compared to earlier versions of this,
the includes related to S0i3 and DPTC were removed.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I89ecf469e44ca2a3b35c9fcf57c008ff29e7b9bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79468
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-13 20:39:24 +00:00
Felix Held c8dfd6d935 soc/amd/genoa/acpi/soc: add root bridges to DSDT
Add the 4 root bridge devices using the ROOT_BRIDGE macro.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If405a90981e5c1fea51935c520800a245473317e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79467
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-13 20:32:11 +00:00
Felix Held 7949a1b73b mb/amd/onyx/dsdt: include acpi/dsdt_top.asl
acpi/dsdt_top.asl provides some common functionality and needs to be
included at the beginning of the DSDT.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia7b5ddce110b35ed65c6df6cc42995abe93a3ffc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79466
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-12-13 20:31:27 +00:00
Felix Held bff9823700 soc/amd/genoa/acpi: include globalnvs.asl in SoC code
Instead of including globalnvs.asl in the mainboard's dsdt.asl, include
it in Genoa's soc.asl. This aligns Genoa with Cezanne and newer and also
moves more SoC-common code to the SoC folder.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie0e3299a95e007188a4d9de824cfff8d25a778be
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79465
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-13 20:30:32 +00:00
Felix Held dd032e0c41 soc/amd/genoa: set up the non-FCH IOAPICs
Apart from the IOAPIC in the FCH which is handled by amd_lpc_ops,
there's one IOAPIC per PCI root which also needs to be initialized.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I38af5a194062e714827852e95f4e29b45311e517
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-12-13 20:29:17 +00:00
Felix Held 0fe8643465 soc/amd/genoa/domain: fix indentation in genoa_pci_domain_ops
There's no need for the two additional spaces between the tabs and the
'='.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic6824e8c7ee870fc44c5efd70cc05677e9948a9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79464
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-12-13 20:28:10 +00:00
Felix Held d01826843e soc/amd/genoa/chip: add init & final functions and chip name
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I00a567f417b1e22167923fc3193583138718dbbd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79463
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-13 20:26:51 +00:00
Felix Held 4e4938bcb9 soc/amd/genoa/include/amd_pci_int_defs: rename PIRQ index 0x60 and 0x61
PIRQ_SCI is already defined as 0x10 and this also brings the definitions
more in line with Phoenix.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib2ab954b379d2edd0167d7fb229557600cbc4e48
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-12-13 20:25:43 +00:00
Patrick Georgi 1d029b40c9 lib/jpeg: Replace decoder with Wuffs' implementation
To quote its repo[0]: Wuffs is a memory-safe programming language (and
a standard library written in that language) for Wrangling Untrusted
File Formats Safely. Wrangling includes parsing, decoding and encoding.

It compiles its library, written in its own language, to a C/C++ source
file that can then be used independently without needing support for
the language. That library is now imported to src/vendorcode/wuffs/.

This change modifies our linters to ignore that directory because
it's supposed to contain the wuffs compiler's result verbatim.

Nigel Tao provided an initial wrapper around wuffs' jpeg decoder
that implements our JPEG API. I further changed it a bit regarding
data placement, dropped stuff from our API that wasn't ever used,
or isn't used anymore, and generally made it fit coreboot a bit
better. Features are Nigel's, bugs are mine.

This commit also adapts our jpeg fuzz test to work with the modified
API. After limiting it to deal only with approximately screen sized
inputs, it fuzzed for 25 hours CPU time without a single hang or
crash. This is a notable improvement over running the test with our
old decoder which crashes within a minute.

Finally, I tried the new parser with a pretty-much-random JPEG file
I got from the internet, and it just showed it (once the resolution
matched), which is also a notable improvement over the old decoder
which is very particular about the subset of JPEG it supports.

In terms of code size, a QEmu build's ramstage increases
from 128060 bytes decompressed (64121 bytes after LZMA)
  to 172304 bytes decompressed (82734 bytes after LZMA).

[0] https://github.com/google/wuffs

Change-Id: If8fa7da69da1ad412f27c2c5e882393c7739bc82
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Based-on-work-by: Nigel Tao <nigeltao@golang.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78271
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-13 16:17:34 +00:00
Naresh Solanki 5466261019 drivers/uart/pl011.c Perform basic UART init
Configure UART baud rate, Line Control register as 8n1 with FIFO
enable and enable UART TX and RX.

Change-Id: I090344a20430dc370a0b93ff7fbbae54111fae24
Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79406
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-12-13 14:27:09 +00:00
Martin Roth 3e25f85d68 drivers/ipmi to lib: Fix misspellings & capitalization issues
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I926ec4c1c00339209ef656995031026935e52558
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77637
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-13 10:42:30 +00:00
Ivy Jian 3933ed5e5a mb/google/brox: Generate RAM ID for supported memory part
Add the MICRON MT62F1G32D2DS-023 WT:B RAM part for brox:

DRAM Part Name                 ID to assign
MT62F512M32D2DR-031 WT:B       0 (0000)
H9JCNNNBK3MLYR-N6E             0 (0000)
MT62F1G32D4DR-031 WT:B         1 (0001)
MT62F1G32D2DS-023 WT:B         2 (0010)

BUG=b:311450057,b:315913909
BRANCH=None
TEST=Run part_id_gen tool without any errors
Change-Id: Id120a5eb311d8299a8e59d2c1658fe0742e93934
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79459
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-12-13 00:24:42 +00:00
Felix Held 919801e5dc soc/amd/genoa/chipset.cb: add missing non-transparent PCI bridges
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2d5efa948e8bd993ca4b5af80f664db687b8a766
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-12-12 18:32:56 +00:00
Felix Held c3d909dbb7 mb/amd/onyx/devicetree: enable more PCI devices
Early versions of CB:76519 had more devices enabled in the chipset
devicetree which shouldn't necessarily be enabled in the chipset
devicetree. Enable most of those in the Onyx mainboard's devicetree.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ieeb96755a007a5ca70e4c31df09325835bb8ef47
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-12-12 18:32:01 +00:00
Felix Held 5aaaee3486 soc/amd/genoa/chipset.cb: disable IOMMU devices by default
Disable the IOMMU PCI devices in the chipset devicetree. In order for
the IOMMU devices on the Onyx mainboard still be enabled, enable them in
the mainboard devicetree.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8c1bbbf370a3b5566a8484bcfa88dc4efa31222b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79409
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-12 18:30:55 +00:00
Felix Held 2f58bbd686 soc/amd/genoa: Parse APOB for DRAM layout
Use the xPRF call to report holes in memory and report those regions as
reserved.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5605499e39931e1a1592318310112666f8a0f144
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-12-12 18:26:34 +00:00
Arthur Heymans 5f6cf6105c vendorcode/amd/genoa: Parse APOB for DRAM layout
Use the xPRF call to report holes in memory to report those regions as
reserved.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: If89b08a31a9b9f8e7d2959d1bc45e91763fe565b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78922
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-12 18:26:09 +00:00
Martin Roth a31b28cb23 mb/amd/onyx: Add MPIO config
Add the device and chip entries for the various PCIe ports and MPIO
lane configuration. Below each PCIe bridge device with an external PCIe
port on the mainboard, an MPIO chip is added that provides the
corresponding MPIO configuration for this external PCIe port.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I8563c5a07eb8fd8ff9dd4e7b63fc9a7d485b1316
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78921
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-12 18:25:35 +00:00
Arthur Heymans f1b1412068 soc/amd/genoa: Add opensil MPIO chip files
Add the openSIL MPIO chip driver that allows specifying the MPIO lane
configuration in the mainboard's devicetree instead of having this
configuration in a separate port descriptor C file.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I1d408a7eff22423612bc5eb9bfebaf0d86642829
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76520
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-12 18:25:09 +00:00
Arthur Heymans 62389ab04a vendorcode/amd/opensil: Add SATA configuration
For now, we'll use a hard-coded SATA controller configuration that
should work in most cases instead of making everything configurable via
devicetree settings.

In the process of scrubbing opensil for public release SATA became non
functional.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ib37a081c0be4fdd2785e1dca70f376b967ce4462
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76518
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-12 16:58:08 +00:00
Martin Roth 21be665c9a mb/amd/onyx: Add USB configuration
Drive board specific USB configuration from the coreboot devicetree into
the opensil input block.

In the process of scrubbing opensil for public release USB became non
functional.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I62eefe1061446612168dd27e673a2742903456c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78920
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-12-12 12:30:24 +00:00
Martin Roth f643a4d77e vendorcode/amd/opensil: Add USB configuration
Drive board specific USB configuration from the coreboot devicetree into
the opensil input block.

In the process of scrubbing opensil for public release USB became non
functional.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ic41f57f3208aebb3a8b42f70cf558de50fa4de24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78919
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-12 12:29:51 +00:00
Felix Held ddc8e5d7bf soc/amd/genoa/chip.h: drop unneeded xhci2_enable
Genoa has no XHCI2 controller, so drop this devicetree option.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5b995bb1c0cf0032be25ab215333bc966427f7ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79454
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-12 12:29:19 +00:00
Arthur Heymans 10e60ab49e arch/arm64/armv8/Makefile.inc: Add clang -target for .ld CPP
When preprocessing the linker script the target arch needs to be
specified.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Id18af3da93d2d06a2ebb83eddd03377c9026c8fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-12-12 12:23:53 +00:00
Kun Liu 3914561ef5 mb/google/rex/var/screebo: Increase PL1 max value from 15W to 25W
Adjust PL1 max value from 15W to 25W

BUG=b:314263021
TEST=emerge-rex coreboot

Change-Id: I4122a13d7e33c736299c1a759ec51f7a3b29340f
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79377
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-12 12:21:15 +00:00
Martin Roth b94fb02178 util/abuild: Better identify config string in log
When using the --skip_set and --skip_unset arguments, the config line
looked like a statement that the build was being skipped instead of
abuild just printing the configuration.

This updates those config statements to better show that it's the
config and not stating that this particular build is being skipped.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I6cc59f9b33dcda51aeb3640d449037a0aa054e36
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76936
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-12 00:43:13 +00:00
Mark Hasemeyer 431ca5eab5 ec/google/chromeec: Provide ec_sync wake option
The ACPI spec defines keywords for the GpioInt and Interrupt resources
to specify whether a given pin is wake capable. Some boards are using
the ec sync interrupt pin to wake the system so the CREC _CRS needs to
be updated accordingly.

Provide a new macro that allows a board to specify whether its ec sync
pin is wake capable.

BUG=b:243700486
TEST=Dump ACPI and verify ExclusiveAndWake share type is set when
     EC_SYNC_IRQ_WAKE_CAPABLE is defined

Change-Id: I483c801ff0fee4d3ce0a3b2fc220e0bd9356a612
Signed-off-by: Mark Hasemeyer <markhas@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Forest Mittelberg <bmbm@google.com>
2023-12-11 14:33:23 +00:00
Felix Held f3523b4f0d soc/amd/genoa/chipset.cb: add missing '_' in gpp_bridge_3_b
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I22b9b6781f516b96724b67d1321dd71b98e0e0e3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79410
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-12-11 11:57:02 +00:00
Arthur Heymans 663c577311 soc/amd/genoa: Add USB configuration
Drive board specific USB configuration from the coreboot devicetree into
the opensil input block.

Add USB OC pins to chipset.cb

In the process of scrubbing opensil for public release USB became non
functional.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I506547a7abbb643d3e982e44a92f33b45cd739e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-12-11 11:04:36 +00:00
Felix Held 543c1ee314 soc/amd/genoa/chipset.cb: enable dummy functions
Enable the dummy function 0 that don't have an alias in the chipset
devicetree.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I607245c587a544007fd714f64901cbb50014612f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-12-11 11:02:31 +00:00
Yidi Lin e78ea98bb2 libpayload/arm64: Round fb_size up to a multiple of GRANULE_SIZE
If a framebuffer is already configured by coreboot, we need to ensure
that the framebuffer size is a multiple of GRANULE_SIZE before passing
to `mmu_add_memrange`. Otherwise, we would fail to allocate memory
region due to `sanity_check`.

Change-Id: Ia6a6400733ca10a61220087e87022f68c28e4789
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79451
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-11 11:00:22 +00:00
Robert Chen 933e50702e mb/google/nissa/var/quandiso: Tune P-sensor
Update proximity sensor tuning value from dedede/kracko tuning.
Remove GPIO override to use the configuration from nissa baseboard:
- GPP_B5  ==>   SOC_I2C_SUB_SDA
- GPP_B6  ==>	SOC_I2C_SUB_SCL

BUG=b:310050220
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot

Change-Id: I7c687677a797415d80be4c420484d3346a8455f6
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79247
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-11 10:46:32 +00:00
Felix Held 6c00a6afc2 soc/amd/common/data_fabric: pass PCI segment group to domain code
Return the PCI segment group number from data_fabric_get_pci_bus_numbers
via pointer argument so that amd_pci_domain_scan_bus can handle the PCI
segment group numbers once coreboot supports more than one PCI segment
group. For now, just print an error and return if the buses are on a PCI
segment group other than 0.

TEST=Mandolin still boots

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia53cda0ba656201c2197d05bc0d4a8fbbe8ad5d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-12-11 10:42:50 +00:00
Subrata Banik 7ae510093c soc/intel/meteorlake: Add entries to eventLog on invocation of early SOL
This patch records early signs of user activity during CSE firmware
synchronization or MRC (re)training events in the event
log (ELOG_TYPE_FW_EARLY_SOL).

These can be used to ensure persistence across global reset (e.g. after
CSE sync) so that they can be later retrieved in order to build things
such as test automation ensuring that we went through the SOL
path/display initialized.

BUG=b:279173035
TEST=Verified on google/rex, event shows in eventlog after CSE sync
and/or MRC.

Scenario #1: While performing MRC update

1 | 2023-11-08 | Early Sign of Life | MRC Early SOL Screen Shown
2 | 2023-11-08 | Memory Cache Update | Normal | Success
3 | 2023-11-08 | System boot | 9
4 | 2023-11-08 | ACPI Wake | S5

Scenario #2: While performing CSE update/downgrade

11 | 2023-11-08 | Early Sign of Life | CSE Sync Early SOL Screen Shown
12 | 2023-11-08 | System boot | 13

Scenario #2: While performing both MRC and CSE upgrade

16 | 2023-11-08 | Early Sign of Life | MRC Early SOL Screen Shown
17 | 2023-11-08 | Early Sign of Life | CSE Sync Early SOL Screen Shown
18 | 2023-11-08 | Memory Cache Update | Normal | Success
19 | 2023-11-08 | System boot | 16
20 | 2023-11-08 | ACPI Wake | S5

Change-Id: Idfa6f216194fd311bb1a57dd7c86fe7446a3597c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78983
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-12-11 05:09:38 +00:00