Disable the PM ACPI timer during PMC init, when `USE_PM_ACPI_TIMER` is
disabled. This is done to bring SKL, CNL, DNV in line with the other
platforms, in order to transition handling of the PM timer from FSP to
coreboot in the follow-up changes.
Disabling is done in `finalize` since FSP makes use of the PMtimer.
Without PM Timer emulation disabling it too early would block.
Change-Id: If85c64ba578991a1b112ceac7dd10276b58b0900
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
Allow devicetree override to leave ac_loadline, dc_loadline and icc_max as default.
Test=Boot to OS
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I715345d5ea83aed9ee929b2a4e13921c9d8895b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add DDR5 and LPDDR5 memory type checks while calculating bus width
extension (in bits).
Additionally, update all caller functions of
smbios_bus_width_to_spd_width() to pass `MemoryType` as argument.
Update `test_smbios_bus_width_to_spd_width()` to accommodate
different memory types.
Create new macro to fix incorrect bus width reporting
on platform with DDR5 and LPDDR5 memory.
With this code changes, on DDR5 system with 2 Ch per DIMM, 32 bit
primary bus width per Ch showed the Total width as:
Handle 0x000F, DMI type 17, 40 bytes
Memory Device
Array Handle: 0x0009
Error Information Handle: Not Provided
Total Width: 80 bits
Data Width: 64 bits
Size: 16 GB
...
BUG=b:194659789
Tested=On Alder Lake DDR5 RVP, SMBIOS type 17 shows expected `Total Width`.
Change-Id: I79ec64c9d522a34cb44b3f575725571823048380
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
CSE EOP will fail if the CSE is disabled (CB:52800)
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ic00fdb0d97fefac977c0878d1d5893d07d4481ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Modify print_me_fw_version to get ME firmware version by
calling it.
Tested=On a not yet to be public platform, verified the function
can get ME FW version successfully.
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Change-Id: I50d472a413bcaaaa085955657bde6a0e6ec2c1db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Make use of `smbios_bus_width_to_spd_width()` for filling DIMM info.
Additionally, ensures dimm_info_util.c file is getting compiled for
romstage.
TEST=dmidecode -t 17 output Total Width and Data Width as expected.
Change-Id: I7fdc19fadc576dec43e12f182fe088707e6654d9
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The PCI-SIG engineering change requirement provides the ACPI additions
for firmware latency optimization. This change adds additional ACPI DSM
function with both of FW_RESET_TIME and FW_D3HOT_TO_D0_TIME to the
USB4/TBT topology which has the same implementation on Tiger Lake in
commit I5a19118b75ed0a78b7436f2f90295c03928300d7.
BUG=b:199757442
TEST= It was validated that the first connected device waits only 50ms
instead of 100ms and all functions work on Alder Lake platform boards.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I0c8977c96de27ab0e554469eba658660975b8493
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The current check for XDCI enabled uses a static device path to an
internal PCI device at a very late point in the boot flow. At this
time the devicetree has been processed and disabled devices have been
already removed. If this device (00:15.1, XDCI) is disabled in
devicetree this will trigger the message
'BUG: check_xdci_enable requests hidden 00:15.1' in the log.
This looks weird and is wrong since it is not a bug to disable this
device when it is not needed.
To avoid this look up the devicetree by a tree walk instead of using
a static value for the devicetree.
Change-Id: If193be724299c4017e7e10142fac8db9fac44383
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The Intel icelake rvp boards actually rely on this but this failure
was hidden in a runtime error instead of a compile time error, due to
weakly linked functions.
Change-Id: Idbbe774efa1515ce1d34ce2ce8f87953300a3312
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58662
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Modify IPC sub command to 2 from 0 for reading LPM requirement from PMC.
Reference:
https://github.com/otcshare/CCG-ADL-Generic-Full
ClientOneSiliconPkg\Include\Register\PmcRegs.h
#define V_PMC_PWRM_IPC_SUBCMD_GEN_COMM_READ 2
It is consumed in below.
ClientOneSiliconPkg\IpBlock\Pmc\Library\PeiDxeSmmPmcLib\PmcLib.c
Change-Id: I58509f14f1e67472adda78e65c3a2e3ee9210765
Signed-off-by: Ethan Tsao <ethan.tsao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Since all x86 CPUs in tree have MTRR support, there is no need to guard
the DISPLAY_MTRRS option with HAVE_DISPLAY_MTRRS. Also all x86 CPUs/SoCs
have a display_mtrrs call at least somewhere in their code, so selecting
the DISPLAY_MTRRS option will always have an effect. All SoCs that don't
select RESET_VECTOR_IN_RAM have the postcar stage where it gets called.
The two AMD SoCs that select RESET_VECTOR_IN_RAM use the FSP2 driver
which contains plenty of display_mtrrs calls.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2894689ce58e7404d9d5a894f3c288bc4016ea19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The Intel Quark SoC does have a LAPIC on its x86 CPU core, so we should
select CPU_X86_LAPIC. This will additionally include the Makefile from
cpu/x86/lapic. Since none of AP_IN_SIPI_WAIT, LEGACY_SMP_INIT and
UDELAY_LAPIC gets selected, only the boot_cpu.c and lapic.c targets will
be added to the build. Since SMP isn't set, adding the boot_cpu.c target
won't change the resulting binary of a timeless build, since the only
function inside will be removed by the compiler's pre-processor in the
!SMP case. So the only thing that will change the resulting binary is
the addition of the lapic.c target. From this target only the function
cpu_get_lapic_addr will be used which overrides the weak implementation
in acpi/acpi.c. The call in arch/x86/mpspec.c can be ignored, since
GENERATE_MP_TABLE isn't selected. So this change will result in the
LAPIC address in the MADT being changed from 0 to to LAPIC_DEFAULT_BASE.
Since the documentation of the Quark SoC mentions that it has a LAPIC on
its one x86 core, this should work.
TEST=None
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2f163bd608f0548abb0e8de90843d2a796b8ef6c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58550
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Initialize the pad_cfg_lock_offset field for the various gpio
pad_community structures in the adl_communities.
BUG=b:201430600
TEST='emerge-brya coreboot' and verify it compiles successfully.
Change-Id: I2cd3e43a84b0140bb2aeae5de1e299db714d419b
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Update api name and comments to be more generic as spi destination
id is not DMI specific.
Update api name as soc_get_spi_psf_destination_id and comments.
And move PSF definition from pcr_ids.h as it's not pcr id.
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ie338d05649d23bddae5355dc6ce8440dfb183073
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
With using a Kconfig option to add the x86 LAPIC support code to the
build, there's no need for adding the corresponding directory to subdirs
in the CPU/SoC Makefile. Comparing which CPU/SoC Makefiles added
(cpu/)x86/mtrr and (cpu/)x86/lapic before this and the corresponding
MTRR code selection patch and having verified that all platforms
added the MTRR code on that patch shows that soc/example/min86 and
soc/intel/quark are the only platforms that don't end up selecting the
LAPIC code. So for now the default value of CPU_X86_LAPIC is chosen as y
which gets overridden to n in the Kconfig of the two SoCs mentioned
above.
Change-Id: I6f683ea7ba92c91117017ebc6ad063ec54902b0a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
No SoC uses the ramstage-only x86_enable_cache helper function to call
enable_cache with some added port 0x80 and console output.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Angel Pons <th3fanbus@gmail.com>
Change-Id: I7c5039e1341fd4089078ad7ffb2fe6584a94045c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This change is required as part of HECI Interface initialization in order
to put the host and CSE into a known good state for communication. Please
refer ME BIOS specification for more details. The change adds HECI
interface reset flow in the CSE driver. It enables coreboot to send HECI
commands before DRAM Init.
BUG=b:175516533
TEST=Run 50 cold reset cycles on Brya
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ie078beaa33c6a35ae8f5f460d4354766aa710fba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
MBP Hob is being generated by FSP after getting data from ME.
coreboot does not consume this HOB and FSP provides an option
for bootloader to skip generation of MBP HOB. This will help in
saving ~14 ms of boot time.
Here is the data from Brya P1 Board:
Before: 955 returning from FspSiliconInit 879,432 (99,156)
After: 955 returning from FspSiliconInit 1,177,513 (84,506)
BUG=b:188577893
BRANCH=None
TEST=No functional impact on Brya system and boot time is reduced
with this patch.
Change-Id: Ibb64e4d0f4ae7212defb6704b05a78e754f75cd7
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58289
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
All x86-based CPUs and SoCs in the coreboot tree end up including the
Makefile in cpu/x86/mtrr, so include this directly in the Makefile in
cpu/x86 to add it for all x86 CPUs/SoCs. In the unlikely case that a new
x86 CPU/SoC will be added, a CPU_X86_MTRR Kconfig option that is
selected be default could be added and the new CPU/SoC without MTRR
support can override this option that then will be used in the Makefile
to guard adding the Makefile from the cpu/x86/mtrr sub-directory.
In cpu/intel all models except model 2065X and 206AX are selcted by a
socket and rely on the socket's Makefile.inc to add x86/mtrr to the
subdirs, so those models don't add x86/mtrr themselves. The Intel
Broadwell SoC selects CPU_INTEL_HASWELL and which added x86/mtrr to the
subdirs. The Intel Xeon SP SoC directory contains two sub-folders for
different versions or generations which both add x86/mtrr to the subdirs
in their Makefiles.
Change-Id: I743eaac99a85a5c712241ba48a320243c5a51f76
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This patch fixes regression introduced by commit bee4bb5f0
(soc/intel/common/cse: Late sending EOP msg if !HECI_DISABLE_USING_SMM)
FAFT test case fail when doing `firmware_DevMode` test.
If CSE is already hidden then accessing CSE registers would be wrong
and will receive junk, hence, return as CSE is already disabled.
BUG=b:203061531
TEST=Brya system can boot to OS with recovery mode.
Change-Id: I2046eb19716c397a066c2c41e1b027a256bd6cf9
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58513
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
After adding the functionality to add a bus/link on the CPU cluster
device in mp_cpu_bus_init if it is missing due to no LAPIC device being
present in the devicetree below the CPU cluster device, we can use
mp_cpu_bus_init as init function in cpu_bus_ops and implement
mp_init_cpus.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I76aebeca1b3227cfd310b6c45f506c042b35ae04
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58509
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Since PSE devices could be initialized as either host owned
(PCI devices) or PSE owned (will be hidden from coreboot and
only visible to PSE interface), add all PSE devices in PCI
list header file for future usage.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: Iaa40cdcb021d05e50504dd85f94e9c021e284d00
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58466
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For coreboot proper, I/O APIC programming is not really required,
except for the APIC ID field. We generally do not guard the related
set_ioapic_id() or setup_ioapic() calls with CONFIG(IOAPIC).
In practice it's something one cannot leave unselected, but maintain
the Kconfig for the time being.
Change-Id: I6e83efafcf6e81d1dfd433fab1e89024d984cc1f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This adds delivery of PIC/i8259 interrupts via ExtNMI on the
affected platfoms.
Change-Id: If99e321fd9b153101d71e1b995b43dba48d8763f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The number of redirection table entries (aka interrupt vectors) inside
an I/O APIC may depend of the SKU, with the related register being of
type read/write-once. Provide support utilities to either lock or set
this registers value.
Change-Id: I8da869ba390dd821b43032e4ccbc9291c39e6bab
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Implement mp_init_cpus and use mp_cpu_bus_init as init function in
cpu_bus_ops.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2adcb1e1d79ced804925c81095cc5c0c2e6f9948
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Implement mp_init_cpus and use mp_cpu_bus_init as init function in
cpu_bus_ops.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I057ae8d95bdc510e9e7afb144b692531107fa45d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Each CPU/SoC checks the return value of the mp_init_with_smm and prints
the same error message if it wasn't successful, so move this check and
printk to mp_init_with_smm. For this the original mp_init_with_smm
function gets renamed to do_mp_init_with_smm and a new mp_init_with_smm
function is created which then calls do_mp_init_with_smm, prints the
error if it didn't return CB_SUCCESS and passes the return value of
do_mp_init_with_smm to its caller.
Since no CPU/SoC code handles a mp_init_with_smm failure apart from
printing a message, also add a comment at the mp_init_with_smm call
sites that the code might want to handle a failure.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I181602723c204f3e43eb43302921adf7a88c81ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Using cb_err as return type of mp_run_on_aps, mp_run_on_all_aps,
mp_run_on_all_cpus and mp_park_aps clarifies the meaning of the
different return values. This patch also adds the types.h include that
provides the definition of the cb_err enum and checks the return value
of all 4 functions listed above against the enum values instead of
either checking if it's non-zero or less than zero to handle the error
case.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4b3f03415a041d3ec9cd0e102980e53868b004b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Use a boolean type to store the information if any mp_run_on_all_cpus
call failed. This is a preparation to change the return type of
mp_run_on_all_cpus from int to enum cb_err which will be done in a
follow-up patch.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic04ad3e4a781a00ee6edcd7dbd24bc7601be1384
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Using cb_err as return type clarifies the meaning of the different
return values. This patch also adds the types.h include that provides
the definition of the cb_err enum and checks the return value of
mp_init_with_smm against the enum values instead of either checking if
it's non-zero or less than zero to handle the error case.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ibcd4a9a63cc87fe176ba885ced0f00832587d492
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
For PchFivrExtVnnRailSxEnabledStates, vnn_enable_bitmap config is used
by mistake, instead of the expected vnn_sx_enable_bitmap
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Idf100be3ac4d6d97335c627e790c1870558d1210
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Do not run or include any code in case the user did not explicitly
enable SGX through `SOC_INTEL_COMMON_BLOCK_SGX_ENABLE`.
Also move the ifdef inside the ASL file.
Change-Id: Iec4d3d3eb2811ec14d29aff9601ba325724bc28c
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
This is a follow-up to commit e9f10ff38b which changed the base
signature and all other occurrences.
To make gcc11 happy (which is pickier about these things), let skylake
follow.
Change-Id: I42a629d865baa53640213a03e54e85623a386e35
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58458
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change updates the STITCH_ME_BIN path to enable support for
including CSE RW update in CBFS. CSE_RW_FILE is set to either
CONFIG_SOC_INTEL_CSE_RW_FILE or CSE_BP2_BIN depending upon the
selection of STITCH_ME_BIN config.
BUG=b:189177580
Change-Id: I0478f6b2a3342ed29c7ca21aa8e26655c58265f4
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This change adds support for allowing mainboards to stitch CSE
components during build time instead of adding a pre-built CSE
binary. Several Kconfig options are added to allow mainboard to
provide the file names for different CSE region components. This makes
use of the newly added cse_serger and cse_fpt tools to create
following partitions:
1. BP1 - RO
2. BP2 - RW
3. Layout
In addition to this, it accepts CSE data partition as an input using
Kconfig CSE_DATA_FILE. All these partitions are then assembled
together as per the following mainboard FMAP regions:
1. BP1(RO) : CSE_RO
2. BP2(RW) : CSE_RW
3. Layout : CSE_LAYOUT
4. Data : CSE_DATA
Finally, it generates the target $(OBJ_ME_BIN) which is used to put
together the binary in final coreboot.rom image.
Several helper functions are added to soc/intel/Makefile.inc to allow
SoCs to define which components use:
1. Decomposed files: Files decomposed from Intel release CSE binary in
FPT format.
2. Input files: Mainboard provided input files using corresponding
Kconfigs.
3. Dummy: Components that are required to have dummy entries in
BPDT header.
These helpers are added to soc/intel/Makefile.inc to ensure that the
functions are defined by the time the invocations are encountered in
SoC Makefile.inc.
BUG=b:189177580
Change-Id: I8359cd49ad256703285e55bc4319c6e9c9fccb67
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Return a read-only pointer from the `soc_get_cstate_map()` function.
Also, constify the actual data where applicable.
Change-Id: I7d46f1e373971c789eaf1eb582e9aa2d3f661785
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The `acpigen_write_CST_package` and `acpigen_write_CST_package_entry`
functions don't modify the provided C-state information. So, make the
pointer parameters read-only to enforce this. Also constify arguments
where possible.
Change-Id: I9e18d82ee6c16e4435b8fad6d467e58c33194cf4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
A regular assignment works just as well and also allows type-checking.
Change-Id: Id772771f000ba3bad5d4af05f5651c0f0ee43d6d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
As long as there is only one PCI segment we do not need
more complicated MCFG generation.
Change-Id: Ic2a8e84383883039bb7f994227e2e425366f9e13
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Add CNVi (14.3) to IRQ Table to stop dmesg error:
iwlwifi 0000:00:14.3: can't derive routing for PCI INT F
iwlwifi 0000:00:14.3: PCI INT F: not connected
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I5b793997f9ea954217871eb4656dacf6abe77e74
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58342
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Use the common ACPI code to reduce code duplication.
After this change, `PSS_MAX_ENTRIES` is honored correctly in P-state
table generation (as of commit c2540a9) and the number reduces from 10
to 7 entries.
Also, remnants of P_BLK support missed in CB:58096 will vanish.
Tested on google/fizz: no errors in dmesg, ACPI tables remain the same
(except PSS, as mentioned above).
Change-Id: I1ec804ae4006a2d9b69c0d93a658eb3b84d60b40
Tested-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44138
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
