Commit Graph

39466 Commits

Author SHA1 Message Date
Matt DeVillier 8bdb006db5 drivers/vpd: Add support to read device serial from VPD
Add functions to read the system and mainboard serial numbers
from VPD tables stored in flash.

Remove board-specific implementations for google/drallion and
google/sarien and select the new Kconfig instead.

Test: build/boot google/akemi with RO_VPD region persisted from
stock Google firmware, verify system/mainboard serial numbers
present via dmidecode.

Change-Id: I14ae07cd8b764e1e22d58577c7cc697ca1496bd5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49050
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-04 23:12:58 +00:00
Matt DeVillier 1717231b74 drivers/vpd: Add VPD region to default FMAP when selected
Currently, use of the VPD driver to read VPD tables from flash
requires the use of a custom FMAP with one or more VPD regions.
Extend this funtionality to boards using the default FMAP by
creating a dedicated VPD region when the driver is selected.

Test: build qemu target with CONFIG_VPD selected, verify entry
added to build/fmap.fmd.

Change-Id: Ie9e3c7cf11a6337a43223a6037632a4d9c84d988
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-04 23:12:35 +00:00
Matt DeVillier 21a9bf81d8 soc/intel/baytrail/southcluster.asl: Use consistent comment formatting
Change-Id: I479e1eb5819c42621e8b17367b964124d5433378
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-04 23:11:35 +00:00
Matt DeVillier 6a7b707d11 soc/intel/baytrail: add LPEA resources to southcluster.asl
The LPEA device memory resources, required by Windows drivers,
were not being set.  Allocate required resources using
soc/intel/braswell/acpi/southcluster.asl as a reference.

This patch alone is not sufficient for working audio under Windows
on Baytrail ChromeOS devices, but it is a necessary component.

Test: boot Windows 10 on google/swanky, observe LPEA device working properly.

Change-Id: I7994d9b2c6e134c01b05cd7c61d309b6ba6e88e5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48745
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-04 23:11:26 +00:00
Kyösti Mälkki 33a68e4676 arch/x86: Move .id section higher
The (now removed) ID_SECTION_OFFSET=0x80 was actually the
secondary address flashrom and FILO are looking for. The
primary was 0x10, just below .reset.

If .id does not collide with .fit_pointer, use the higher
of the two locations.

Change-Id: I0d3a58c82efd3bbf94f4bc80ec5bbc97d5b1c109
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48499
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-04 23:10:55 +00:00
Arthur Heymans bccb6916fe security/intel/txt/ramstage.c: Fix clearing secrets on CBNT
intel_txt_memory_has_secret() checks for ESTS.TXT_ESTS_WAKE_ERROR_STS
|| E2STS.TXT_E2STS_SECRET_STS and it looks like with CBNT the E2STS
bit can be set without the ESTS bit.

Change-Id: Iff4436501b84f5c209add845b3cd3a62782d17e6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47934
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-04 23:09:22 +00:00
Martin Roth b513c53f31 util: Make sure all util dirs have description files at top level
New util directories have been added with no description.md file.
The description file for supermicro was added at a secondary level,
which doesn't help a user find the util since no path was added. Move
it up to the top level.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I40b4c25dd7706513e96c6b8078a34160f8bb901e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tom Hiller <thrilleratplay@gmail.com>
2021-01-04 23:08:16 +00:00
Angel Pons 86e3d748f8 nb/intel/sandybridge: Replace memset with initializer
There's no need to use `memset` here.

Change-Id: I0478bc3ff25b75bf0b554aa83ead6a63fcbd975c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-04 23:07:59 +00:00
Kevin Chiu 30b12e905f mb/google/zork: update DRAM table for morphius
Remove index0 DRAM assignment since it doesn't use in any build.

Add Hynix DDR4 DRAM H5ANAG6NCJR-XNC, index was generated by gen_part_id

BUG=b:175911098
BRANCH=zork
TEST=emerge-zork coreboot

Change-Id: I853a316c266afafeecff67b263005a77be316e2b
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48723
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-04 23:07:48 +00:00
Matt DeVillier 6da4de1e7a mb/google/hatch: set Tianocore boot timeout to 5s for PUFF-based boards
PUFF-based Chromeboxes need more than the 2s default in order to init
an external display and show the boot splash/menu prompt.

Test: build/boot WYVERN variant, ensure boot splash/menu prompt visible
regardless of display init type used.

Change-Id: Ie6d2151d28058501498a4c501bb221919b4e1b39
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-04 01:15:12 +00:00
Matt DeVillier 0139a15c4b mb/google/{beltino,fizz,jecht}: Set Tianocore boot timeout to 5s
These Chromeboxes need more than the 2s default in order to init
an external display and show the boot splash/menu prompt.

Test: build/boot one of each variant, ensure boot splash/menu
prompt visible regardless of display init type used.

Change-Id: Ib90136b7e564451aff638af4d42abd97e42b3c19
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48978
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-04 01:15:04 +00:00
Michael Niewöhner d990455c0a mb/clevo/cml-u: Configure IRQ as level triggered for HID over I2C
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4,
the interrupt line used by the device is required to be level triggered.
Hence, this change updates the configuration of the HID over I2C devices
to be level triggered.

References:
[1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx
[2] https://review.coreboot.org/c/coreboot/+/47417/2/src/mainboard/google/hatch/variants/baseboard/gpio.c#b182

Tested successfully on Clevo L141CU.

Change-Id: Ia232c0a11546aa6d17614f4cab07c255e58f2fed
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-04 00:36:34 +00:00
Matt DeVillier 2c6a725e2b mb/google/octopus: Add ACPI backlight controls
Enables backlight control under Windows 10.

Test: build/boot Windows 10 20H2 on google/ampton, verify
display backlight controls functional.

Change-Id: I779f7f3f5a111018fc7b5c50c5750a9eb815d670
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-04 00:35:27 +00:00
Matt DeVillier d7ef450d88 soc/intel/apollolake: Hook up GMA ACPI brightness controls
Add struct i915_gpu_controller_info for boards to supply info needed
to generate ACPI backlight control SSDT.

Hook into soc/common framework by implementing intel_igd_get_controller_info().

Add Kconfig entries to set the correct register offsets for backlight
frequency and duty cycle.

Change-Id: Ia62a88b58e7efd90f550000fc5b2cef0cb5fade7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40593
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-04 00:31:42 +00:00
Michael Niewöhner 95a181e432 mb/clevo/l140cu: add libgfxinit support
Change-Id: Id58bb2ce5fdaeaf158d02d8c812ab2c331db352d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48751
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-03 11:52:38 +00:00
Michael Niewöhner 6efff741c2 mb/clevo/l140cu: add panel settings to the dt and hook up GMA ACPI
Add the panel settings dumped from vendor firmware and hook up
drivers/intel/gma, which will be required for brightness control.

Keyboard brightness control still requires ACPI code. This will be done
in a separate change later.

Test: Panel gets enabled when the payload starts on Clevo L141CU.

Change-Id: I7977a2271da72c142b025b4631318d1a39adfb13
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-03 11:52:22 +00:00
Michael Niewöhner d585564fd0 drivers/intel/gma: add macro for one internal panel in gfx struct
Add a new macro `GMA_DEFAULT_PANEL(ssc)` as shortcut for specifying one
internal panel at port A (0) in the devicetree.

Change-Id: I5308b53667657d0b255ae5bc543f1a00431f5818
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49054
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-03 11:52:04 +00:00
Kyösti Mälkki d6c57141dd soc/intel: Drop indirect <soc/nvs.h> include
Change-Id: Ia19018685749efdd543cb09c06df117690ab9d66
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48803
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-03 11:37:04 +00:00
Kyösti Mälkki f3f2aa8a50 soc/intel: Replace <soc/nvs.h> with <soc/device_nvs.h>
Change-Id: Ib78e746875e330e47540a6199343be62aa7e92a6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48830
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-03 11:35:51 +00:00
Kyösti Mälkki 26e0f4cefc sb,soc/intel: Convert some CONFIG(CHROMEOS) preprocessor
Change-Id: I964f4340caa20124a15e52c055d2f27ba5113687
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48783
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-03 11:33:54 +00:00
Kyösti Mälkki 1749b77b23 vc/google/chromeos: Move chromeos_set_me_hash() prototype
Change allows to remove some <chromeos/gnvs.h> exposure from
coreboot proper.

Change-Id: I7817914cc7b248331bb8fa79baa642ed548bbc11
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48782
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-03 11:31:14 +00:00
Jason Glenesk 498015d62f soc/amd/picasso: Separate CPUID defs into new header
Move CPUID definitions out of msr.h into new cpuid.h header.

BUG=b:155307433
BRANCH=Zork

Change-Id: I2ed5e0a5a6dbdb38fce8bf3e769f680330718653
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-01-02 22:52:12 +00:00
Jason Glenesk 61624b2d2d acpi: Add cb support to publish CRAT ACPI object
Add cb support to publish CRAT ACPI object in native coreboot.

BUG=b:155307433
BRANCH=Zork

Change-Id: I5fb7c15b11414f6d807645921c0ff1ab927e6e0f
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-01-02 22:50:56 +00:00
Nico Huber 9d233ba9a9 libpayload/lpgcc: Check for `libpayload.config` for in-tree builds
Instead of checking for an already fully build `libpayload.a`, we check
for the `libpayload.config` which is the actual prerequisite to start
using `lpgcc`. This will allow compilation of payload sources before or
in parallel with the build of `libpayload.a`.

Change-Id: Ic0143fefe33560af8b013ae48bbbe231b3ad46f3
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-01-01 21:42:41 +00:00
Nico Huber dc5c83812b libpayload/lpgcc: Turn references to build dir into a variable
Introduce a `$_OBJ` variable, that points to the build directory for
in-tree usage of `lpgcc`. If unset, the default `../build` relative
to the location of `lpgcc` is used.

Change-Id: I35112d7533d69aa51252dd2bceec010a62522403
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47629
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-01 21:41:48 +00:00
Nico Huber 1dba2ed806 libpayload: Keep a copy of .config in the build dir
This should make it easier to find the correct config for in-tree
builds.

Change-Id: I08d396ae3cedc65f63c4b8865701ea123c7d56cb
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47628
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-01 21:31:29 +00:00
Nico Huber 1823d53cbf libpayload: Move .xcompile into $(obj)
Keep libpayload's xcompile in its build dir. While we are at it,
align things with the top-level version.

Having `.xcompile` in a central place led to race conditions when
multiple payloads try to build their own libpayloads in parallel.

Change-Id: I504e1862db79b368289867f7568c9169f27a1549
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-01 21:30:44 +00:00
Michael Niewöhner c4f8fbdb11 soc/intel/cnl: add panel and backlight configuration code
Add code for panel and backlight configuration.

Tested successfully with libgfxinit on Clevo L141CU.

Change-Id: If619b28478b4b0d18f28f318c16336e0de76e129
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-01 21:12:45 +00:00
Michael Niewöhner 97e21d3e95 nb/intel/hsw,soc/intel/{bdw,skl,apl},mb/*: unify dt panel settings
There are multiple different devicetree setting formats for graphics
panel settings present in coreboot. Replace the ones for the platforms
that already have (mostly) unified gma/graphics setup code by a unified
struct in the gma driver. Hook it up in HSW, BDW, SKL, and APL and adapt
the devicetrees accordingly.

Always ensure that values don't overflow by applying appropriate masks.

The remaining platforms implementing panel settings (GM45, i945, ILK and
SNB) can be migrated later after unifying their gma/graphics setup code.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I445defe01d5fbf9a69cf05cf1b5bd6c7c2c1725e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48885
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-01 21:12:12 +00:00
Michael Niewöhner 44fa0d4ca0 soc/intel/bdw,nb/intel/hsw: convert panel delays to ms representation
For easier review of the switch to a new register struct in the
follow-up change, the panel delay times get converted from destination
register raw format to milliseconds representation in this change.

Formula for conversion of power cycle delay:

  gpu_panel_power_cycle_delay_ms =
    (gpu_panel_power_cycle_delay - 1) * 100

Formula for all others:

  gpu_panel_power_X_delay_ms = gpu_panel_power_X_delay / 10

The register names gain a suffix `_ms` and calculation of the
destination register raw values gets done in gma code now.

Change-Id: Idf8e076dac2b3048a63a0109263a6e7899f07230
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-01 11:25:22 +00:00
Shaoming Chen 9e38efc27b soc/mediatek: dsi: Fix EoTp flag
SoC will transmit the EoTp (End of Transmission packet) when
MIPI_DSI_MODE_EOT_PACKET flag is set.

Enabling EoTp will make the line time larger, so the hfp and
hbp should be reduced to keep line time.

BUG=b:168728787
BRANCH=kukui
TEST=Display is normal on Kukui

Signed-off-by: Shaoming Chen <shaoming.chen@mediatek.corp-partner.google.com>
Change-Id: Ifadd0def13cc264e9d39ab9c981fbdc996396bfa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-01 02:58:33 +00:00
Jitao Shi b32e4d6763 mb/google/kukui: Add panel api after dsi start
Some bridge chip or panel requires dsi signal output before dsi
receiver works.

BUG=b:168728787
BRANCH=kukui
TEST=Display is normal on Kukui

Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Change-Id: I3bded27087490f32ee233e615cfad1fd05fb582d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-01 02:58:21 +00:00
Idwer Vollering 93df1d9cfa util/amdfwtool: portability fixes for FreeBSD
Add the stdint.h header, and drop the GLIBC section from amdfwtool.h to build this tool on FreeBSD as well as Linux.

Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Change-Id: I295fd308b0f5e2902931f02c9455823a614976de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48977
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-31 16:06:58 +00:00
Kyösti Mälkki 2c626f332b coreboot_table: Convert some CONFIG(CHROMEOS) preprocessor
Change-Id: I1e63a419db92642df6b7956050c39540c2ae11d6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48781
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-31 12:25:42 +00:00
Kyösti Mälkki 673698636f soc/intel/skylake: Remove device_nvs.h
Change-Id: I9d500be609d61ccf234260216bd5aae3f78e91a8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48802
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-31 12:25:00 +00:00
Yidi Lin b17e805dbf soc/mediatek/mt8192: Move flash_controller.c to common/
The flash controller driver can be shared among mt8173 and mt819x.

TEST=boot to kernel on Asurada
     boot to kernel on Hana (w/o BL31)

Change-Id: I4e5213563189336496122a0f2d8077b3e5245314
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-12-31 03:09:19 +00:00
Huayang Duan 9e685b764a soc/mediatek/mt8192: Add DDR mode register init
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Change-Id: If200f4dcef0b1d0b7e901d4ae6e667b1f75156f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-31 03:08:13 +00:00
Huayang Duan c43e989966 soc/mediatek/mt8192: Do dramc duty calibration
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Change-Id: I317451e41774e983c07566dc71c7ba8833c7f55e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44710
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-31 03:07:52 +00:00
Huayang Duan 2d0117e2fe soc/mediatek/mt8192: Add dramc 8 phase calibration
To get better PI linearity, perform 8 phase calibration to do
MCK 0/180/45 training and select the best PI settings.

Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Change-Id: Ib4ccaa8d43b8382cbc64cf82de86ad1ac16cb89a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-31 03:07:37 +00:00
Huayang Duan 4cb885e5be soc/mediatek/mt8192: Update initial settings of dramc
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Change-Id: I08326cd1e6f7415d3a91d1591678e1b2c52c6781
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-31 03:07:16 +00:00
Matt DeVillier c6589aefc1 drivers/intel/gma: Include gfx.asl by default for all platforms...
which select INTEL_GMA_ACPI. Rework brightness level includes and
platform-level asl files to avoid duplicate device definition for GFX0.

Include gfx.asl for Skylake/Kabylake, since all other soc/intel/common
platforms already do. Adjust mb/51nb/x210 to prevent device redefinition.

Some OSes (e.g. Windows, MacOS) require/prefer the ACPI device for
the IGD to exist, even if ACPI brightness controls are not utilized.
This change adds a GFX0 ACPI device for all boards whose platforms
select INTEL_GMA_ACPI without requiring non-functional brightness
controls to be added at the board level.

Change-Id: Ie71bd5fc7acd926b7ce7da17fbc108670fd453e0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-30 16:35:36 +00:00
Matt DeVillier 5cf4c87da7 soc/intel/common: Move gfx.asl to drivers/intel/gma
Adjust platform-level includes as needed.

Change-Id: I376349ccddb95c166f0836ec1273bb8252c7c155
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48959
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-30 16:35:21 +00:00
G.Pangao 142e6f5ecf soc/mediatek/mt8192: eint: unmask eint event mask register
eint event mask register is used to mask eint wakeup source on mt8192.
All wakeup sources are masked by default. Since most MediaTek SoCs do
not have this design, we can't modify the kernel eint upstream driver to
solve the issue 'Can't wake using power button (cros_ec) or touchpad'.
So we add a driver here to unmask all wakeup sources.

BUG=b:169024614

Signed-off-by: G.Pangao <gtk_pangao@mediatek.com>
Change-Id: I8ee80bf8302c146e09b74e9f6c6c49f501d7c1c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46409
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-30 06:04:10 +00:00
Matt DeVillier 4b9b44696d payloads/tianocore: Clean up build string
Extract the architecture (-a) and package (-p) options into a
new variable (ARCH) to simplify the construction of BUILD_STR.

Test: build/boot various boards w/Tianocore payload

Change-Id: I490d48428ac56d613d0b704700dfcf4ebfb2d245
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48942
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-30 01:27:51 +00:00
Michael Niewöhner fca152cb89 soc/intel/cnl: add Kconfig values for GMA backlight registers
Add the right register values for backlight control to CNL's Kconfig.
To make iasl happy about the reversed register order, split the field.

Change-Id: I05a06cc42397c202df9c9a1ebc72fb10da3b10ec
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-30 01:05:21 +00:00
Michael Niewöhner 6f3c5df55b mb/ocp/deltalake: replace "POST complete" mb code with driver functionality
Replace the mainboard-specific code for "POST complete" signalling with
devicetree entries for using the newly introduced IPMI driver
functionality.

Test: Boot the machine via the BMC web interface and check that sensors
get read correctly by the IPMI firmware when the payload starts.

Tested successfully.

Tested-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Change-Id: I3441c2a971cfb564b34b3a419beceb949fe295b1
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-30 00:31:56 +00:00
Michael Niewöhner 6c3ba50a44 mb/supermicro/x11ssh-tf: configure "POST complete" gpio for IPMI driver
Configure the "POST complete" gpio in the devicetree for the BMC/IPMI
driver and set the pad's initial value to 0 since the signal is active-
high and shall be set by the IPMI/BMC driver.

Also add the pad to early gpio config, since it is expected to have an
external pull-up like X11SSM-F, which is wrong and would confuse the BMC.

Test: Boot the machine via the BMC web interface and check that sensors
get read correctly by the IPMI firmware when the payload starts.

Tested successfully.

Change-Id: If344b2271bfc8d50b8b64847109818f96f2abbcb
Tested-by: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-30 00:31:47 +00:00
Michael Niewöhner 8281a53766 mb/supermicro/x11ssm-f: configure "POST complete" gpio for IPMI driver
Configure the "POST complete" gpio in the devicetree for the BMC/IPMI
driver.

Also add the pad to early gpio config, since it has an external pull-up,
which is wrong and would confuse the BMC. Set the pad's initial value to
zero since the "POST complete" signal is active-high and shall be set by
the IPMI/BMC driver.

Test: Boot the machine via the BMC web interface and check that sensors
get read correctly by the IPMI firmware when the payload starts.

Tested successfully.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I6409b2aca90585e44ee5d32df0ae73b259443f32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-30 00:31:34 +00:00
Michael Niewöhner 961ceffd0d mb/supermicro/x11ssm-f: configure the BMC jumper JPB1
Set `bmc_jumper_gpio` to the JPB1 gpio to enable/disable BMC/IPMI
according to its value.

Test: Boot with jumper set to each enabled and disabled and check debug
log if IPMI gets enabled/disabled accordingly.

Tested successfully.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I8581556d915cbad2c743a79db273479ba55798fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-30 00:30:57 +00:00
Michael Niewöhner 548a3dc7a6 drivers/ipmi: implement "POST complete" notification functionality
Some server boards like OCP Tiogapass and X11-LGA1151 boards use a gpio
for signalling "POST complete" to BMC/IPMI. Add a new driver devicetree
option to set the gpio and configure a callback that pulls the gpio low
right before jumping to the payload.

Test: Check that sensor readings appear in BMC web interface when the
payload gets executed.

Successfully tested on Supermicro X11SSM-F with CB:48097, X11SSH-TF with
CB:48711 and OCP DeltaLake with CB:48672.

Change-Id: I34764858be9c7f7f1110ce885fa056591164f148
Tested-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Tested-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-30 00:30:41 +00:00