Commit Graph

238 Commits

Author SHA1 Message Date
Li-Ta Lo 54f05f6c5c use #define macro for pci class ids
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1563 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-05-14 17:20:29 +00:00
Li-Ta Lo 9f0d0f9669 rename walk_static_devices
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1552 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-05-10 16:05:16 +00:00
Li-Ta Lo 75337f7500 code reformat, fixed a bug in set/unset logical operation
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1551 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-05-07 21:56:48 +00:00
Li-Ta Lo fb4c50f695 code reformat, doxidization
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1549 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-05-07 21:52:47 +00:00
Li-Ta Lo 9782f7538c code refromat, doxidization
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1547 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-05-05 21:15:42 +00:00
Li-Ta Lo d16753be86 chaged chip_device_path::enable to chip_device_path::enabled,
again, I am the only one who can't speak English.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1544 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-04-29 20:30:02 +00:00
Li-Ta Lo 69c5a905ed changed dev->enable to dev->enabled. Sorry, I am the only one who can't speak
English in the project.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1543 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-04-29 20:08:54 +00:00
Li-Ta Lo 5782d273eb check in the current code for IBM/E325, can somebody help to fix it ?
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1538 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-04-26 17:51:20 +00:00
Li-Ta Lo c6bcedb2c4 yhlu's pnp patch
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1518 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-04-21 16:57:05 +00:00
Li-Ta Lo e52666931a Doxidization, reformat
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1469 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-03-23 21:28:05 +00:00
Eric Biederman 5cd81730ec - Moved hlt() to it's own header.
- Reworked pnp superio device support.  Now complete superio support is less than 100 lines.
- Added support for hard coding resource assignments in Config.lb
- Minor bug fixes to romcc
- Initial support for catching the x86 processor BIST error codes.  I've only seen
  this trigger once in production during a very suspcious reset but...
- added raminit_test to test the code paths in raminit.c for the Opteron
- Removed the IORESOURCE_SET bit and added IORESOURCE_ASSIGNED and IORESOURCE_STORED
  so we can tell what we have really done.
- Added generic AGP/IOMMU setting code to x86
- Added an implementation of memmove and removed reserved identifiers from memcpy
- Added minimal support for booting on pre b3 stepping K8 cores
- Moved the checksum on amd8111 boards because our default location was on top of
  extended RTC registers
- On the Hdama added support for enabling i2c hub so we can get at the temperature
  sensors.  Not that i2c bus was implemented well enough to make that useful.
- Redid the Opteron port so we should only need one reset and most of memory initialization
  is done in cpu_fixup.  This is much, much faster.
- Attempted to make the VGA IO region assigment work.  The code seems to work now...
- Redid the error handling in amdk8/raminit.c to distinguish between a bad value
  and a smbus error, and moved memory clearing out to cpufixup.
- Removed CONFIG_KEYBOARD as it was useless.  See pc87360/superio.c for how to
  setup a legacy keyboard properly.
- Reworked the register values for standard hardware, moving the defintions from
  chip.h into the headers of the initialization routines.  This is much saner
  and is actually implemented.
- Made the hdama port an under clockers BIOS.  I debuged so many interesting problems.
- On amd8111_lpc added setup of architectural/legacy hardware
- Enabled PCI error reporting as much as possible.
- Enhanded build_opt_tbl to generate a header of the cmos option locations so
  that romcc compiled code can query the cmos options.
- In romcc gracefully handle function names that degenerate into function pointers
- Bumped the version to 1.1.6 as we are getting closer to 2.0

  TODO finish optimizing the HT links of non dual boards
  TODO make all Opteron board work again
  TODO convert all superio devices to use the new helpers
  TODO convert the via/epia to freebios2 conventions
  TODO cpu fixup/setup by cpu type


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1390 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-03-11 15:01:31 +00:00
David W. Hendricks 854e45292b final merge of YhLu's stuff
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1371 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-02-09 22:47:38 +00:00
Li-Ta Lo db7f47cbbf Change PCI_BRIDGE_CONTROL to PCI_BRIDGE_CTL_VGA
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1324 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-01-08 21:15:49 +00:00
Greg Watson 5965169dad Don't compare low 8 bits, which are revision.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1318 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-12-17 17:39:53 +00:00
Ronald G. Minnich b56ef07600 for tyan. recover from Eric B's error additions to via code :-)
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1220 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-10-15 20:05:11 +00:00
Eric Biederman ad1b35a12b - Minor bugfixes
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1215 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-10-14 02:36:51 +00:00
Eric Biederman 83b991afff - O2, enums, and switch statements work in romcc
- Support for compiling romcc on non x86 platforms
  - new romc options -msse and -mmmx for specifying extra registers to use
  - Bug fixes to device the device disable/enable framework and an amd8111 implementation
  - Move the link specification to the chip specification instead of the path
  - Allow specifying devices with internal bridges.
  - Initial via epia support
 - Opteron errata fixes


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1200 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-10-11 06:20:25 +00:00
Ronald G. Minnich cb3f498296 success. It boots as a bproc slave now.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1176 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-10-02 18:16:07 +00:00
Ronald G. Minnich 6dd6c68507 IRQ setup for EPIA
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1174 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-10-02 00:08:42 +00:00
Ronald G. Minnich 99dcf231f4 The epia now works.
Now to fix the ram ...


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1159 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-09-30 02:16:47 +00:00
Eric Biederman ff0e8465e8 - Include hypertransport.h in hypertransport.c
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1101 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-09-04 03:00:54 +00:00
Eric Biederman 0ac6b41e70 - 1.1.4
Major restructuring of hypertransport handling.
  Major rewerite of superio/NSC/pc87360 as a proof of concept for handling superio resources dynamically
  Updates to hard_reset handling when resetting because of the need to change hypertransport link
    speeds and widths.
    (a) No longer assume the boot is good just because we get to a hard reset point.
    (b) Set a flag to indicate that the BIOS triggered the reset so we don't decrement the
       boot counter.
  Updates to arima/hdama mptable so it tracks the new bus numbers


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1097 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-09-02 17:16:48 +00:00
Eric Biederman e9a271e32c - Major update of the dynamic device tree so it can handle
* subtractive resources
  * merging with the static device tree
  * more device types than just pci
- The piece to watch out for is the new enable_resources method that was needed in all of the drivers


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1096 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-09-02 03:36:25 +00:00
Eric Biederman 30e143a5f0 - Add back in the hard reset code from the freebios1 tree.
This allows generic code to reset the box.
- Update the hypertransport code to automatically calculate link
  widths and freequencies, and to call hard_reset if neecessary for
  the changes to go into effect.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1094 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-09-01 23:45:32 +00:00
Eric Biederman bbb6d1020f - Fix poor resource allocation estimate.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1066 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-08-04 19:54:48 +00:00
Greg Watson 7100d67ae8 code was broken
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1017 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-23 21:34:46 +00:00
Eric Biederman 860ad373ef - First pass at code for generic link width and size determination
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@999 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-21 23:30:29 +00:00
Eric Biederman 2c018fba95 - First pass at s2880 support.
- SMP cleanups (remove SMP only use CONFIG_SMP)
- Minor tweaks to romcc to keep it from taking forever compiling
- failover fixes
- Get a good implementation of k8_cpufixup and sizeram for the opteron


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@998 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-21 20:13:45 +00:00
Greg Watson 8275bad6f6 more chip stuff
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@990 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-21 04:20:08 +00:00
Greg Watson d0580343b6 chip stuff
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@988 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-20 23:28:01 +00:00
Eric Biederman 387a8db88e - Remove excess line from pci_device.c
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@970 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-17 04:10:42 +00:00
Eric Biederman 4086d16ba2 - Implement an enable method for pci devices.
- Add initial support for the amd8131
- Update the mptable to something possible
- hdama/Config add the amd8131 southbridge


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@968 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-17 03:26:03 +00:00
Eric Biederman 5fb929e6e3 - pci_device.c fixes for generic pci bridges to zero the unused portion of bridge resources
- coherent_ht.c remove dead idle loop.
- raminit.c Enable a 64MB mmio window just below 4GB


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@967 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-17 02:15:46 +00:00
Ronald G. Minnich 99acb49cf7 added config and other test files.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@882 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-06-17 16:51:06 +00:00
Eric Biederman 7a5416af95 - Modify the freebios tree so the pci config space api is mostly in sync between
code that runs without ram and code that runs with ram.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@869 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-06-12 19:23:51 +00:00
Eric Biederman 526855741b - Cleanups on the romcc side including a pci interface that uses
fewer registers, and is easier to hardcode.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@838 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-05-19 19:16:21 +00:00
Eric Biederman 5899fd82aa - Small step forward Linux boots and almost works...
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@795 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-04-24 06:25:08 +00:00
Eric Biederman 8ca8d7665d - Initial checkin of the freebios2 tree
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@784 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-04-22 19:02:15 +00:00