espi_setup already clears most of the controller registers. So this
change consolidates the clear logic into one spot.
This shouldn't result in a behavior change on Picasso. Picasso already
has the eSPI decodes clear on boot, so this change is a nop.
BUG=b:183524609
TEST=Boot guybrush to the OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ic57689e50febd29796d8ac8d99c81e41fee5b41c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This is only ever called after espi_setup.
55861 - AMD System Peripheral Bus Overview also says that io ranges
should be configured before enabling the BUS_MASTER bit.
BUG=b:183524609
TEST=Boot guybrush to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I074e487d8768a578ee889a125b9948e3aa6c7269
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52059
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Configure I2C rise/fall time in device tree to ensure I2C CLK runs
accurately at I2C_SPEED_FAST (< 400 kHz).
Measured I2C frequency just as below after tuning:
I2C0(touchpad): 385 kHz
I2C4(audio): 380 kHz
BUG=b:180335053
BRANCH=dedede
TEST=Build and check after tuning I2C clock is under 400kHz
Change-Id: Ic92ee0379456e80260a8026bc38ee41325dad6d2
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51335
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tidy up the interrupt status. This will leave SLAVE0_INT_STS = 0.
BUG=b:183524609
TEST=Boot guybrush to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I950cfb81521e35758c120a482670cfdb924201d2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52056
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This sets the eSPI registers to the reset values specified in the PPR.
On Cezanne, the PSP modifies these registers such that the eSPI
peripheral cannot send DEFER packets. This causes random bus errors.
These reset values are identical to what is currently used on Zork.
I didn't clear out ESPI_DECODE because it's currently being done by
cb:51749.
BUG=b:183524609
TEST=Boot guybrush to the OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ic3a9860747aac78121358b4499d8a38052236c0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
These are defined in the public Picasso PPR - 55570-B1 Rev 3.15.
BUG=b:183524609
TEST=Build guybrush
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7e601f767327e0a24a086146623af039388b2e7b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52057
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There are forthcoming designs that will be utilizing
a discrete TPM 2.0 solution. Split the existing dedede
configuration options so future mainboard variants can
easily select the appropriate Kconfig option using the
newly introduced options:
- BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50
- BOARD_GOOGLE_BASEBOARD_DEDEDE_TPM2
The existing variants all select the former option,
BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 since all those
designs currently utilize Cr50.
BUG=b:184151664
Change-Id: I2bdb1ca4fd78cc0628256d49678ea042c55f6fba
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52030
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aseda Aboagye <aaboagye@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
FSP v2081 has a bug where it uses the information about south XHCI
ports to enable TCSS XHCI ports. This change works around this bug by
enabling south XHCI ports 1 and 2 in brya baseboard devicetree. brya0
already enables south XHCI port 1 in overridetree.cb, however, it is
still enabled in baseboard/devicetree in case more variants are added
to brya before FSP is fixed.
BUG=b:184324979
TEST=Verified that TCSS XHCI ports 1 and 2 are now enabled.
Change-Id: I4b86a98b18234ba309ddf2f30b80d78472951637
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
There's no good reason to use values smaller than 2 GiB here. Well, it
increases available DRAM in 32-bit space. However, as this is a 64-bit
platform, it's highly unlikely that 32-bit limitations would cause any
issues anymore. It's more likely to have the allocator give up because
memory-mapped resources in 32-bit space don't fit within the specified
MMIO size, which can easily occur when using a discrete graphics card.
Change-Id: If585b6044f58b1e5397457f3bfa906aafc7f9297
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52072
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There's no good reason to use values smaller than 2 GiB here. Well, it
increases available DRAM in 32-bit space. However, as this is a 64-bit
platform, it's highly unlikely that 32-bit limitations would cause any
issues anymore. It's more likely to have the allocator give up because
memory-mapped resources in 32-bit space don't fit within the specified
MMIO size, which can easily occur when using a discrete graphics card.
Change-Id: I6cdce5f56bc94cca7065ee3e38af60d1de66e45c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52070
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The `pdwm` part was supposed to be an abbreviation of `power down`, but
it is neither self-explanatory nor properly-spelled. Rename the enum.
Change-Id: I7b83c71d4534b62e18ced04eebe6a65089e1d874
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
These definitions are unused and not particularly useful. Drop them.
Change-Id: I40a824888701870b6713c1a16ab671c19b3770ae
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51900
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use the actual value as it is more informative.
Change-Id: Id3bd8ccdf79d1e3fdf97cda049f81271bb017ef7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Drop unnecessary typedefs and rename DDR4-specific definitions to avoid
name clashes, as done for DDR3 in earlier commits. This allows including
and using both DDR3 and DDR4 headers in the same compilation unit.
Change-Id: I17f1cd88f83251ec23e9783a617f4d2ed41b07f0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51898
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To avoid name clashes with definitions for other DRAM generations,
rename the enum type and values to contain `ddr3` or `DDR3`.
Change-Id: If3710149ba94b94ed14f03e32f5e1533b4bc25c8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51896
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These typedefs are not necessary. Remove them, and rename some elements
to avoid any confusion with other DRAM generations, such as DDR4.
Change-Id: Ibe40f33372358262c540e371f7866b06a4ac842a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51895
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Cezanne PSP configures the eSPI with the assumption that it's a
majolica, setting up both the serial port and the majolica EC IO decode
ranges. Since guybrush is NOT a majolica, this doesn't work very well
there. Clearing the decode ranges allows the guybrush platform to set
the decode ranges needed for its EC.
BUG=b:183524609
TEST=Set up eSPI on Guybrush
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I77cfb948cb9ae6d1cf001bd9e66cede8d93f50b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Previously, the eSPI code would only add to existing decode ranges, and
there wasn't any way to clear ranges. This clears all the ranges so
the eSPI configuration can start fresh.
BUG=b:183207262, b:183974365
TEST=Verify on Guybrush
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ic4e67c40d34915505bdd5b431a064d2c7b6bbc70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51748
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The sizeof() operator was being applied to a pointer-to-struct type.
Correct this, so that the entire struct space gets cleared.
Change-Id: Ieab3aaa2d07a928f27004b94132377d5dae935c0
Found-by: Coverity CID 1451732
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52054
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Sam Lewis <sam.vr.lewis@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These used to be printed before CB:46605. Having them in the logs can be
a huge timesaver when debugging logs sent to you by other people
(especially from systems that don't boot all the way). Let's add them
back.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ifdbfdd29d25a0937c27113ace776f7aec231a57d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
These files were just renamed to put `adlrvp` in between `vbt`
and the memory technology type.
Change-Id: Icefbac462d0ec9c660541e9cf44686d6dcf82dfd
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52032
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
BUG=None
TEST=Build and boot to OS in Guybrush. Ensure that the EC Software Sync
is complete.
Change-Id: Id8655b6f805e14ce3cb71777c1cc175f45841fcc
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Ideally we would like to perform EC Software Sync in payload. But with
the hardware requirement (EC_IN_RW) and firmware requirement (TPM
command to get EC execution environment) not met yet, adding the support
to perform early EC Software sync. With EFS2 enabled, this will also
help cr50 to set the boot mode as NORMAL instead of NO_BOOT.
BUG=None
TEST=Build and Boot to OS in Guybrush. Ensure that the EC software sync
is successfully complete.
CBFS: Found 'ecrw.hash' @0x50400 size 0x20 in mcache @0x020171ec
VB2:check_ec_hash() Hexp RW(active): 2dd8dbb78d0c626358a626037973a3d81982f88f3f38e7f759039bf84e05ccc6
VB2:check_ec_hash() Hmir: 2dd8dbb78d0c626358a626037973a3d81982f88f3f38e7f759039bf84e05ccc6
<snip>
VB2:check_ec_hash() Heff RW(active): 2dd8dbb78d0c626358a626037973a3d81982f88f3f38e7f759039bf84e05ccc6
VB2:sync_ec() select_rw=RW(active)
Change-Id: I820e651c6b22a833fef6f17a4ceb5a8cfb6f1616
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Enable Touchpad by configuring the enable GPIO to logic high. Add
touchpad configuration for ELAN touchpad.
BUG=b:182207444
TEST=Build and boot to OS in Guybrush. Ensure that the trackpad events
are detected using evtest.
Change-Id: Ib47fbb33f2b181eb85f6ded98a5b0ce08fbc7b64
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51962
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change disables touchpad interrupt, as it sends spurious wake signal
via GPP_F14 and immediately wakes the system from S3. It happens because
touchpad's power is gated by deassertion of PLTRST#. The behaviour for
S0ix is unchanged.
BUG=183738135
TEST=manually
Signed-off-by: Boris Mittelberg <bmbm@google.com>
Change-Id: Ia7d282f38d205a94cc43eaa1832729f4606437c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51831
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change exposes the PCH_INT_ODL line in GPP_F17 as interrupt resource for
CREC device
BUG=none
TEST=manual test
Signed-off-by: Boris Mittelberg <bmbm@google.com>
Change-Id: I0c05160cb7894b5f7beee93a0c93776f973eae56
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
PCH_INT_ODL (GPP_F17) is used to wake AP from S3, however it was configured
to reset state on PLT reset assertion. This change reconfigures the pad
using DEEP instead of PLTRST to retain pad configuration across S3.
BUG=b:178545523
TEST=manual: verified that asserting PCH_INT_ODL wakes system and the wake
source is GPP_F17
Signed-off-by: Boris Mittelberg <bmbm@google.com>
Change-Id: I8df5dafedabc7b6af74c39621f0e1eb7019a9a17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reference code does an and-or operation with zero as or-value, reading
and writing to the same address. The accessed register is 32-bit, and
reference code programs bits 22, 21, 20, 16 to zero. However, coreboot
code reads the value from bits 7..0 instead. Correct this.
Change-Id: I33bf268449c2f799321be81a02bbccff855ee1fe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51861
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There is no "volume" defined in cmos.layout now, so removing "volume="
from cmos.default, otherwise building will fail with
CONFIG_USE_OPTION_TABLE set.
Change-Id: I1d6bb68fb927882ddcc052b432bb34b42c58eac7
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Iru Cai (vimacs) <mytbk920423@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
We've mostly stopped using Trogdor-rev0 now and are starting to bring up
rev2 instead. Therefore, the default revisions this builds for should be
the newer ones.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ie433ebb2a03fb1636b5012b4a0567ba6f982579d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52007
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The is used for AMD Grunt board which uses ALC5682 and MAX98357 codec.
kernel driver will need to retrieve MISC FCH memory resource for CLK
enabling per different CID/HID.
BUG=b:171755306
BRANCH=master
TEST=emerge-grunt coreboot
Change-Id: I5f29a2d784a9fc749fff61a9c96c0a487b71a2d7
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51659
Reviewed-by: Yu-hsuan Hsu <yuhsuan@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable Acoustic noise mitigation for lantis and set slew rate to 1/4
which is calibrated value for the board. Other values like PreWake,
Rampup and RampDown are 0 by default.
BUG=b:183561593
BRANCH=dedede
TEST=EE verify acoustic noise test passes.
Change-Id: I5e5f24ed934910726c220678068d085b6ee2bcf6
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51762
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Needed so we write the correct resource into the ACPI tables.
BUG=b:183737011
TEST=Boot OS and see GPIO devices working
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I2ba4349e0ed500912db40aa6ef9b649046f4358f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51961
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This allows the cr50 on guybrush to show up in ACPI.
BUG=b:183737011
TEST=Boot OS and see I2C devices initialized
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ifb5679b7bbefbf753217981874bb1bdaef35f6db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51958
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Needed so get_lid_switch will actually call the EC. Otherwise it
returns -1.
BUG=b:183524609
TEST=Depthcharge no longer halts complaining that coreboot didn't sample
the pin
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4639b3713d726192e251dcffa14381dd92518fa2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51954
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
It looks like we are having SI issues on eSPI at 33 MHz. Switching to 16
MHz makes everything a lot more stable.
BUG=b:183524609
TEST=Boot to OS and run `ectool version` 1000 times and see no problems.
Before with 33 MHz there was an error every few cycles.
declare -i i=0; while ectool version; do i+=1; echo "$i"; sleep .11; done; echo "Finished: $i"
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I6ab515629703a157c1d1ac6adcf5cf379e80f8ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
pci_rom_ssdt reloads the oprom from cbfs. It then places it into cbmem
and writes the offsets as the ROM ACPI node. The GOP driver modifies the
VBIOS so we don't want to reread from cbfs. When using GOP we also pass
the offsets with the VFCT table.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Iaf53e750564f1f0e115cd354790da62e672d74b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Eric Lai