Commit Graph

41738 Commits

Author SHA1 Message Date
Daniel Campello bd64f8ef2e migrate out of flashrom deprecated options
This change replaces --diff and --fast-verify for the supported
equivalent flashrom options

Signed-off-by: Daniel Campello <campello@chromium.org>
Change-Id: I8c48c7f819f968c3ddd94278415e5e9e0ef93924
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2021-04-29 01:05:29 +00:00
John Zhao 97a94429f2 mb/google/volteer: Add EC_HOST_EVENT_USB_MUX
This changes adds the EC_HOST_EVENT_USB_MUX to be dark resume source.

BUG=b:183140386
TEST=In S0ix, remove DP dongle, system does dark resume. AP and EC
synchronized. AP got port partner disconnection.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I53bd4fee21e2e2d1f16f558ab0341a50ef9a0e14
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52716
Reviewed-by: Tanu Malhotra <tanu.malhotra@intel.com>
Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-28 16:48:14 +00:00
Balaji Manigandan B 8aef56ab3b .gitmodules: update vboot submodule to track branch=main
vboot has been updated to track main branch, however the
.gitmodules defaults to master branch following the
coreboot default. This impacts the rebase of submodule
git submodule update --remote --rebase 3rdparty/vboot/

With this change the rebase to latest commit is successful

Signed-off-by: Balaji Manigandan B <balaji.manigandan@intel.com>
Change-Id: I7713aecdec43a5d5623ef81803ac0fc02ce14070
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52664
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-28 16:33:07 +00:00
Patrick Rudolph 985009ad14 soc/intel/common/block/hda: Use azalia device code
The code is already compiled in on all platforms. Use it as it provides
the same functionality. Note that GCAP is no longer R/WO on these
platforms. However, select `AZALIA_LOCK_DOWN_R_WO_GCAP` just in case.
This will be dropped in a follow-up.

Tested on Prodrive Hermes, still detects and initializes both codecs.

Change-Id: I75424559b2b4aca63fb23bf4f8d5074aa1e1bb31
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50795
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-28 16:32:34 +00:00
Anil Kumar b46ec389bd mb/intel/adlrvp_m: Add UART0 GPIO config for ADL-M RVP
This patch adds UART0 config in early GPIO table

Branch=None
Test=Build coreboot and boot on ADLRVP-M board. Check UART logs

Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: Ic0cc955a02936b74f44fed55a9f4b8054646681a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52201
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-28 16:24:41 +00:00
Raul E Rangel 3ad24c7137 soc/amd/common/smi_handler: Print warning when receiving an SCI SMI
We don't have any infrastructure setup to handle SCI SMIs. Instead of
just silently ignoring the SMI, print a warning saying that it is
being ignored.

BUG=none
TEST=Trigger an SCI SMI and see warning printed.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I803e572250925b7d5ffdbb3e8958f9aff1f808df
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52674
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-28 16:16:38 +00:00
Angel Pons a35f1810a2 superio/nuvoton/npcd378: Fall back to non-negative value
This change is needed to update the option API to use unsigned integers.
The CMOS option system does not support negative numbers. So, adjust the
call to get_int_option() to use 3 as fallback instead of -1.

Change-Id: I46c5f5c6f47f99379cbafc0d60258b99dc512e9d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-04-28 16:12:11 +00:00
Angel Pons 8580047dfa mb/dell/optiplex_9010: Always log chosen fan mode
Always print the chosen fan mode, not only when get_int_option() returns
the fallback value. Callers of get_int_option() should not try to handle
option-related errors, and simply proceed using the fallback value.

This change is needed to update the option API to use unsigned integers.
The CMOS option system does not support negative numbers.

Change-Id: Ic8adbe557b48a46f785d82fddb16383678705e87
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-04-28 16:11:22 +00:00
Kangheui Won 68de80838c soc/amd/cezanne: copy psp_transfer.h from picasso
Cezanne version of psp_transfer.h lacks some necessary definitions.
Currently we don't have any plan to change transfer buffer structure in
cezanne, so just copy'em over.

Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I9361c4ab76c8ded06358a7718d5e447c16414721
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52540
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-28 16:06:44 +00:00
Kangheui Won 66c5f258be soc/amd/cezanne: copy Kconfig options for psp_verstage
These are just copied from picasso one.

Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I701d6af63b24e86f8e132fad73504e20148a2bf3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-04-28 16:06:13 +00:00
David Wu 2df58852d3 mb/google/dedede/var/metaknight: Define stop_gpio for goodix touch screen
Define TOUCH_RPT_EN pin(GPP_A11) as the stop_gpio for the touch screen
and control TOUCH_RPT_EN pin to keep low.

BUG=b:176253069
TEST=Build and boot metaknight to OS, confirm GPP_A11 pin keep low.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I816e29eccac0f1935aeaa3b94c907870e2451e3a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52653
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-28 16:04:34 +00:00
Angel Pons 52bab2551c drivers/intel/gma/Kconfig: Simplify Skylake/Kaby Lake conditions
Use `SOC_INTEL_COMMON_SKYLAKE_BASE` to simplify conditions.

Change-Id: Ie69bde31b58bbd973db00bd578a51477c5b21cab
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Timofey Komarov <happycorsair@yandex.ru>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2021-04-28 14:15:19 +00:00
Angel Pons 49c20c00e4 soc/intel: Add Z370, H310C and B365 device IDs
Intel document 335192-004 contains the PCI device IDs for Z370 and
H310C, but lacks the ID for B365. The ID appears on some websites:

https://linux-hardware.org/index.php?id=pci:8086-a2cc-1849-a2cc

Change-Id: Iea3c435713c46854c5271fbc266f47ba4573db52
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52703
Reviewed-by: Timofey Komarov <happycorsair@yandex.ru>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-28 14:14:46 +00:00
Angel Pons b45a769939 soc/intel: Add Kaby Lake PCH-U base device ID
Taken from Intel document 334658-003 (7th Generation Intel Processor
Family I/O for U/Y Platforms and 8th Generation Intel Processor Family
I/O for U Quad Core Platforms, Datasheet - Volume 1 of 2).

Change-Id: I1d48c8868e1e5d453d599ecec835938ce09935d0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52702
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Timofey Komarov <happycorsair@yandex.ru>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-28 14:14:35 +00:00
Angel Pons 9f7e08be61 soc/intel/skylake: Shorten report_platform PCH-H names
For brevity's sake, just print the PCH model.

Change-Id: Ib9e96683e3cb0b63a11344f3b5383292bff88e13
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52701
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Timofey Komarov <happycorsair@yandex.ru>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-28 14:13:27 +00:00
Angel Pons f530e363d1 soc/intel: Rename 200-series PCH device IDs
The code name for these PCHs is Union Point, abbreviated as `UPT`. There
are some 300-series Union Point PCHs (H310C, B365, Z370) which are meant
to be paired with Coffee Lake CPUs instead of Skylake or Kaby Lake CPUs,
and referring to them as `KBP` (Kaby Point, I guess) would be confusing.

Tested with BUILD_TIMELESS=1, HP 280 G2 remains identical.

Change-Id: I1a49115ae7ac37e76ce8d440910fb59926f34fac
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52700
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Timofey Komarov <happycorsair@yandex.ru>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-28 14:13:20 +00:00
Angel Pons 0129393a6b soc/intel/skylake: Drop Lewisburg PCHs from report_platform
These PCHs are used with Xeon-SP processors, which use different code.

Change-Id: I05f67cd57aa9f867e2fab88cd49e0384073a0b20
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52699
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Timofey Komarov <happycorsair@yandex.ru>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-28 14:11:28 +00:00
Eric Lai 21f04d59b5 mb/google/brya: remove WLAN PCIE setting
Brya uses CNVi WiFi module, PCIE setting is not required.

TEST=WiFi is functional in the OS.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ib82c98905ed3b30075e9830c1a2638817f140abe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-28 09:56:33 +00:00
Stefan Ott dc77bc0546 mb/asus/p5q: Document working fan control and FireWire port
Fan control and FireWire work fine on my board.

Signed-off-by: Stefan Ott <stefan@ott.net>
Change-Id: Idc69e902370c4094daef93e843abc6ae564625f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-28 09:56:06 +00:00
Jason Glenesk 925e3896d0 mb/amd/majolica:Set IRQ for GPIO controller
AMD GPIO driver will not load if IRQ is not set. As a consequence,
it does not clear the interrupt when waking from S0i3.

BUG=178728116
TEST=Perform 2 S0i3 cycles, confirming second cycle does not return
instantly due to first interrupt not being cleared.

Change-Id: I3072263e8e68f939a47ed4125444c60133087824
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-28 09:54:57 +00:00
Patrick Rudolph 7a0b9b680b mb/prodrive/hermes: Drop Vref configuration for older boards
Drop Vref verbs from the baseboard table as it's not required for
Rev. 3 and earlier.

Change-Id: I41c207f97dad6c9107c1999eb46d2d6304a6c217
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51919
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
2021-04-28 09:52:57 +00:00
Weiyi Lu 450fd0b536 soc/mediatek/mt8195: Add PLL and clock init support
Add PLL and clock init code.
Add frequency meter and API for raising little CPU/CCI frequency.

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Change-Id: I8ded0236d10826687f080bd5a213feb55d4bae03
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52667
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-28 02:42:03 +00:00
Yidi Lin 2368a310be soc/mediatek: Move the common part of PMIC drivers to common/
The PMIC drivers can be shared by MT8192 and MT8195.

Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: Ie17e01d25405b1e5119d9c70c5f7afb915daf80b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-04-28 02:41:43 +00:00
Raul E Rangel 15ddb363d4 mb/google/guybrush: Fix EC SCI configuration
This change fixes two problems:
1) We had the enum values for .direction and .level swapped. The naming
is very confusing...
2) ESPI_SYS is not a good event to use for EC SCI. It is a level/low
event that is only cleared by reading the eSPI status register 0x9C.
Cezanne has added a new event source that directly exposes the SCI bit.
This is the correct event source to use for EC SCI.

BUG=b:186045622, b:181139095
TEST=`lpc sci` on EC console and see /proc/interrupts increase by 1

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I764b9ec202376d5124331a320767cbf79371dc07
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-04-27 23:36:05 +00:00
Tim Wawrzynczak f62c49474f sb/intel/common: Refactor _PRT generation to support GSI-based tables
Newer Intel SoCs also support _PRT tables, but they route PCI devices to
more than just PIRQs, and statically specify IRQs instead of using link
devices. Extend/refactor intel_acpi_gen_def_acpi_pirq to support this
additional use case.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ica420a3d12fd1d64c8fe6e4b326fd779b3f10868
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-04-27 11:06:38 +00:00
Mike Banon d26cdb3ea3 vc/amd/agesa/f15tn/Config/PlatformInstall.h: enable the AMD CPB feature
Enable the AMD Turbo Core a.k.a. AMD Core Performance Boost (CPB)
feature [1] for f15tn boards - like it's already done for f14 and f16kb.
According to CB:51394 [2] it improves the performance of Lenovo G505S by
up to 50%, and is unlikely to cause regressions for the other boards.

[1] https://en.wikipedia.org/wiki/AMD_Turbo_Core
[2] https://review.coreboot.org/c/coreboot/+/51394

Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I1eaa8ff3953c492e8f9431d7b4a09b86e0ef77a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51396
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-04-27 08:16:50 +00:00
Stefan Ott 98d6385c9a MAINTAINERS: Add myself as reviewer for some boards that I own
I have a Lenovo X200, a Lenovo X201 and an Asus P5Q.

Signed-off-by: Stefan Ott <coreboot@desire.ch>
Change-Id: I9577a848cb799fca237487fc20d6aa9135599f4e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52593
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-26 23:00:38 +00:00
Kevin Chang f005dda9dd mb/google/volteer/variant/lindar: Disable acoustic mitigation
Roll back CPU slow slew rate setting to Intel default "SLEW_FAST_2"
Because baseboard modify slow slew rate setting to "SLEW_FASE_8"
for all project, but Lindar and Lillipup is using "SLEW_FAST_2",
so this setting need to roll back.

BUG=b:186140230
TEST=Build FW and boot to OS checking with CPU log.

Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I7de252b26c75f8dad218f3eb79a0988e60964f4c
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52620
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-26 22:36:42 +00:00
Martin Roth 1fb5395d9d mb/google/guybrush: Add STAPM values to overridetree
This enables STAPM power management.  Values follow the AMD
specification.

BUG=b:185209734
TEST=Build & Boot guybrush

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ib9f2ec9a8ac118c55ae53b9419ea4ff74ce7b599
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: chris wang <Chris.Wang@amd.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-26 21:44:55 +00:00
Martin Roth 9c17665aaa soc/amd/cezanne: Update STAPM vars with units
Like the Picasso platform, it's very useful to have units on these
variables.

BUG=b:185209734
TEST=Build & Boot

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I592c807c5e9a2c17b1c5959e56a01237352c5204
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-26 21:44:47 +00:00
Martin Roth 029d997b6e amd/cezanne: Add slow_ppt_time & thermctl_limit to UPD
These values will be added in the upcoming STAPM configuration update.

BUG=b:185209734
TEST=Build & Boot guybrush

Cq-Depend: chrome-internal:3780259
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I2a6835c16badfe505e3c33b356ca671766cd6972
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: chris wang <Chris.Wang@amd.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-26 20:55:34 +00:00
Tim Crawford 109c4d05d6 mb/system76/oryp6: Add System76 Oryx Pro 6
https://tech-docs.system76.com/models/oryp6/README.html

Tested with TianoCore (UefiPayloadPkg).

Working:

- PS/2 keyboard, touchpad
- Both DIMM slots
- M.2 NVMe
- M.2 SATA
- MicroSD card slot
- All USB ports
- Integrated graphics using Intel GOP driver
- Webcam
- Ethernet
- Internal microphone
- Combined headphone + mic 3.5mm jack
- Combined microphone + S/PDIF 3.5mm jack
- Booting to Ubuntu Linux 20.10 and Windows 10
- Flashing with flashrom

Not working:

- S3 suspend/resume: System hangs on wake from S3
- Discrete/Hybrid graphics: Requires a new driver
- Internal speakers: Enabled in separate patch

Not tested:

- Thunderbolt functionality
- S/PDIF output

Change-Id: If017d65ca6cb36fe1f631d4dadd050a1547c93fa
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47768
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-26 20:45:50 +00:00
Angel Pons a8753e9cbb haswell/broadwell: Replace remaining MCHBAR accessors
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 and Purism Librem 13 v1
remain identical.

Change-Id: I74b633fb0b012304b5b4bd943272ed82dcb6f7d5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52468
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-26 18:39:58 +00:00
Iru Cai cf730ce481 mb/hp/snb_ivb_laptops: Do not set EC SLPT on S5
Linux kernel now uses S5 for reboot, which makes reboot fail if EC
SLPT bit is set.

Tested on HP EliteBook 2560p, reboot and S3 resume work after this
change.

Change-Id: I9b3ea737f85cc4045714263657bcdaac08f3a20d
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-26 13:26:57 +00:00
Angel Pons a4c09c51d0 mb/**/cmos.layout: Drop unreferenced `iommu` option
No code in coreboot uses this option, so it might as well be dropped.

Change-Id: Ie58bab7e87831db08b9f398a777ba350920b707b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52639
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-26 10:32:49 +00:00
Angel Pons d4799d7b04 mainboard: Drop unreferenced CMOS options
Remove CMOS options that are not read anywhere in the code. They may
have been used in the native AMD platform code, or got copied around
from board to board and never did anything to begin with.

Change-Id: Ib19ace4fa6e610a28e68fe2612b4e623f200f064
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52638
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-26 10:29:13 +00:00
Tan, Lean Sheng 2ffa9c6f29 soc/intel/elkhartlake: Remove elog.c
Remove elog.c from EHL soc as EHL does not support chromebook and
hence does not need it.

Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: If66adfe15d00feb0a7fb5e1ced92006a4adebdb7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50173
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-26 08:32:20 +00:00
Tan, Lean Sheng 6e9d8067ca soc/intel/elkhartlake: Update GPIO communities
GPIOs are divided into different communities. Each community
consists of one or more GPIO groups. We need to configure the
groups in coreboot so that they are mapped properly.

GPIO communities should be properly configured in GPIO_CFG and
MISCCFG registers. GPP_* defines in gpio_soc_defs.h are configured
in GPIO_CFG register while the PMC_GPP_* in pmc.h.

GPIO communities in coreboot should match with the kernel gpio
communities also. Kernel reads the ASL file from coreboot. This
patch adds the proper community mapping in ASL code to match with
kernel code. In gpio_soc_defs.c file we are indexing the groups
correctly. In gpio.h file we define all the gpio devices as kernel
populates sysfs with separate gpio device for each community. This
patch is created based on Intel EHL PCH Datasheet with Document
number 614109 and Chapter 21.

Also update GPIO COM3 Port ID and 2 GPIO register values
(HOSTSW_OWN_REG_0 & PAD_CFG_BASE) respectively.

Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: Ifc609b3d6ab9ea2b807dc0f178ec99f95d2db4cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-04-26 08:32:13 +00:00
Ivy Jian 4874c6dff4 mb/google/mancomb: Add mancomb APCBs into build
This adds the Mancomb APCBs into the AMD firmware binary.

BUG=b:182211161
TEST=Build and check log showing APCB sources present.

Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Change-Id: Ifdf1e813fce6f93378c2495cf76bdace81d87c16
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52600
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-26 08:31:57 +00:00
Patrick Huang ed1592b2ec src/soc/amd/picasso: Add HDMI 2.0 disable setting
hdmi2_disable bit0~3 is used to disable HDMI 2.0 function in DDI0~3

BUG=b:179170193
BRANCH=none
TEST=Build; Verify the UPD was passed to system integrated table

Signed-off-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com>
Change-Id: I383bfd04e01f5202db093105662344869e475746
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
2021-04-26 08:31:27 +00:00
Patrick Huang 02cd6b42b5 src/vendorcode/amd/fsp/picasso: Add HDMI 2.0 Disable setting section of FspmUpd.h
This change adds HDMI 2.0 Disable setting

BUG=b:179170193
BRANCH=none
TEST=Build; Verify the UPD was passed to system integrated table

Signed-off-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com>
Change-Id: Ie00389074f3718a23440c41ae0b116455aa8b603
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
2021-04-26 08:31:21 +00:00
Ivy Jian c20f33960c mb/google/mancomb: PCIe GPIOs - enable enables, disable resets
To train PCIe devices, the devices need to be enabled and taken out of
reset.  This patch does the bare minimum needed to train PCIe.  It is
not intended to handle timings, which will be addressed later.

Copy the enables for WLAN into early GPIO Init so that they're
enabled before FSP-M runs and trains the PCIe busses.

Again, this patch is the minimum to let the FSP train the PCIe busses.

BUG=b:182202136
TEST=Boot guybrush from NVME.

Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Change-Id: I5e3e9fe21f44b832e26b0942759ae2ec96ec6c82
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-04-26 08:29:15 +00:00
Kevin Chang 4f4eba9149 mb/google/volteer/variant/lindar: Create dynamic fan table mechanism
Add dynamic fan table mechanism for Lindar and Lillipup.
Create different fan tables that provided from thermal team.

BUG=b:185308432
TEST=Build FW and boot to OS modify CBI test with DPTF tool.

Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I1b79dbe1ae6ee7aa41cef832b4ee305cc8f4b753
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-04-26 08:28:44 +00:00
Karthikeyan Ramasubramanian b6a4476f34 mb/google/guybrush: Enable S0i3
BUG=b:185939089
TEST=Build and boot to OS in Guybrush. Enter S0i3 after passing the
sleep state configuration from the mainboard.

Change-Id: I4b23b014ca45bd09c76b626b73b0332586dec056
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-26 08:28:36 +00:00
Karthikeyan Ramasubramanian 5ad85d95cd soc/amd/cezanne/fsp_m_params: Configure the s0i3_enable UPD
Configure the S0i3 enable UPD based on the mainboard configuration.

BUG=b:178728116
TEST=Build and boot to OS in Guybrush. Enter S0i3 after passing the
sleep state configuration from the mainboard.

Change-Id: I18f43e964d1c70317155394257a5e2c1900816bb
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-26 08:28:29 +00:00
Jason Glenesk 250e610fa0 vc/amd/fsp/cezanne:Add s0i_enable upd control
Add upd to enable S0i3 in fsp.

BUG=b:178728116
TEST=Build and boot to OS in Guybrush. Enter S0i3 after passing the
sleep state configuration from the mainboard.

Cq-Depend: chrome-internal:3777391
Change-Id: I01759caa4d72e284b2b960634f89c6a2ab1dad57
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-26 08:28:22 +00:00
Eric Lai b1e8a8a6ce mb/google/brya: Enable GL9755 SD card reader
Enable GL9755 SD card reader.

BUG=b:185397257
TEST=SD card is functional in the OS.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ib3be54274ca796bedda76ce807a0bd630d1d8e4f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-26 08:28:04 +00:00
John Zhao baecee1052 soc/intel/alderlake: Use device ID from pci_devs header file
This change applies device ID from the SoC pci_devs.h directly.

BUG=None
TEST=Built image successfully.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ic5d2910ca53c02527aef0ad33ed52a35f2bdf7af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-26 08:27:54 +00:00
John Zhao 24ae31cdc6 soc/intel/alderlake: Fix devices list in the DMAR DRHD structure
The VT-d specification states that device scope for remapping hardware
unit which has DRHD_INCLUDE_PCI_ALL flags must be the last in the list
of hardware unit definition structure. This change fixes the devices
list in the DMAR DRHD structure.

BUG=None
TEST=Built image successfully.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I14c34ad66a5ee8c30acabd8fe5a05c22087f9120
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52477
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-26 08:27:46 +00:00
John Zhao ae3f524a1f soc/intel/tigerlake: Use device ID from pci_devs header file
This change applies device ID from the SoC pci_devs.h directly.

BUG=None
TEST=Built image successfully.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I0c3bd60c62664337429e6817d2cf54cf2e8d500b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-26 08:27:34 +00:00