To train PCIe devices, the devices need to be enabled and taken out of
reset. This patch does the bare minimum needed to train PCIe. It is
not intended to handle timings, which will be addressed later.
Copy the enables for WWAN & WLAN into early GPIO Init so that they're
enabled before FSP-M runs and trains the PCIe busses.
Again, this patch is the minimum to let the FSP train the PCIe busses.
BUG=b:182202136
TEST=Boot guybrush from NVME.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I3807e02de1e9ae40b0a4162217afd6aabb5b04ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52115
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This option's value is not used anywhere. Remove it.
Change-Id: I0f30cddd30d459f48b51f377b111bbc04709c5f8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52102
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
It is zero for all mainboards. If one really wanted to ignore VT-d
support, a user-visible Kconfig option would be a better approach.
Change-Id: I320c10317f3fabee5443c16ebdf1ffd0e24193b8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Commit 0591348833 introduced this Kconfig
option inside soc/intel/common scope. However, it was only hooked up in
commit d74cd60b81 for Alder Lake, and in
commit 99157c1f4a for Tiger Lake. Hook up
the `SOC_INTEL_DISABLE_IGD` Kconfig option to all other platforms which
have the `InternalGfx` UPD.
Change-Id: Icd1379a835b445a6d4b028ebde5a3e355ee5b67b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52100
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
WFC Camera driver will control the power sequence.
Therefore, set default to low.
BUG=b:184024459
TEST=abuilds
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I7ce25b83a715a022e36289dc0abf0d39f5798eb0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This is a temporary workaround for a bug that breaks graphics due to
some power management issue.
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie4c8ff8e827901112fd8b2e993898006bc133241
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52141
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
pcie_rst isn't working correctly, so use the AUX resets to reset the
PCIe devices before training.
BUG=b:182202136
TEST=See PCIe devices train & enumerate
Change-Id: I6db21c79dcbd40c7a8c3f01c60b02882a3851278
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This patch adds the functionality to write the DXIO and DDI descriptors
to the UPD data structure to the SoC code and adds the
mainboard_get_dxio_ddi_descriptors function to each mainboard using the
Cezanne SoC that gets called to get the descriptors from the board code.
Change-Id: I1cb36addcf0202cd56ce99e610a13d6d230bc981
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51948
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This allows coreboot to easily iterate over the descriptors.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2ecb3b543f90b8c6a957794f0c55b0ba5c72d59d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51955
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The UPD header files get generated as part of the FSP build process. For
the initial Cezanne development we took the Picasso UPD data structures
as a starting point. This patch replaces it with the first version of
the Cezanne-specific UPD data structures that is present in version 12
of the internal work-in-progress FSP binary drops.
The serial_port_stride UPD-M field is removed, since the information is
already given by serial_port_use_mmio. The stride is 4 bytes for the
MMIO UART case and 1 byte for the legacy I/O case.
BUG=b:182524631
TEST=NVMe works on google/guybrush when the rest of the patch train is
applied as well.
Change-Id: Idca235029bf2e68d403230d55308820cab61a6c0
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
GPIOs should be configured in ramstage even if they are configured in an
earlier stage.
BUG=b:182211161
TEST=builds
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I07d5c46d6ea6dc2bc9ab265d0c01772d653884cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
mb/google/guybrush: Update APCB - disable debug
mb/google/guybrush: Add APCB to get through memory training
soc/mediatek/mt8192: Add EMI Settings of 8GB Normal Mode
soc/mediatek/mt8192: Update MCUPM firmware
soc/mediatek/mt8192: Add version info for SSPM
TEST=Boot guybrush to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I445d753c712670fe80efcdf29459736df2b76666
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This change was promised as a follow-up in
change ID: Ic0302f663cbc931325334d0cce93d3b0bf937cc6
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I9a41b46cc90684746e2b240c8ee442df1b3d7cf5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
On VCCin there was an oscillation which occurred just as the kernel
started (kernel starting... message). On some devices, this behavior
seems even worse. In previous platforms VCCin toggled for a few ms
and then was stable. For volteer, this happens at the same point in
time for around 40ms. However, it starts oscillating again later in
the boot sequence. Once at the root shell, it seems to oscillate
indefinitely at around 100-200Hz (very variable though). To fix this
we need to control the deep C-state voltage slew rate.We have options
for controlling the deep C-state voltage slew rate through FSP UPDs.
This patch expose the following FSP UPD interface into coreboot:
- AcousticNoiseMitigation
- FastPkgCRampDisable
- SlowSlewRate
We are setting SlowSlewRate for all volteer boards to 2 which is Fast/8.
TGL has a single VR domain(Vccin). Hence, the chip config is updated to
allow mainboards to set a single value instead of an array and FSP UPDs
are accordingly set.
BUG=b:153015585
BRANCH=firmware-volteer-13672.B
TEST= Measure the change in noise level by changing the UPD values.
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Change-Id: Ica7f1f29995df33bdebb1fd55169cdb36f329ff8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
From Skylake/Sunrise Point onwards, there are two BIOS_CNTL registers:
one on the LPC/eSPI PCI device, and another on the SPI PCI device. When
the WPD bit changes from 0 to 1 and the LE bit is set, the PCH raises a
TCO SMI with the BIOSWR_STS bit set. However, the BIOSWR_STS bit is not
set when the TCO SMI comes from the SPI or eSPI controller instead, but
a status bit in the BIOS_CNTL register gets set. If the SMI cause is not
handled, another SMI will happen immediately after returning from the
SMI handler, which results in a deadlock.
Prevent deadlocks by clearing the SPI synchronous SMI status bit in the
SMI handler. When SPI raises a synchronous SMI, the TCO_STS bit in the
SMI_STS register is continously set until the SPI synchronous SMI status
bit is cleared. To not risk missing any other TCO SMIs, do not clear the
TCO_STS bit again in the same SMI handler invocation. If the TCO_STS bit
remains set when returning from SMM, another SMI immediately happens and
clears the TCO_STS bit, handling any pending events.
SPI can also generate asynchronous SMIs when the WPD bit is cleared and
one attempts to write to flash using SPI hardware sequencing. This patch
does not account for SPI asynchronous SMIs, because they are disabled by
default and cannot be enabled once the BIOS Interface Lock-Down bit in
the BIOS_CNTL register has been set, which coreboot already does. These
asynchronous SMIs set the SPI_STS bit of the SMI_STS register. Clearing
the SPI asynchronous SMI source should be done inside the SPI_STS SMI
handler, which is currently not implemented. All of this goes out of the
scope of this patch, and is currently not necessary anyway.
This patch does not handle eSPI because I cannot test it, and knowing if
a board uses LPC or eSPI from common code is currently not possible, and
this is beyond the scope of what this commit tries to achieve (fix SPI).
Tested on HP 280 G2, no longer deadlocks when SMM BIOS write protection
is on. Write protection will be enforced in a follow-up.
Change-Id: Iec498674ae70f6590c33a6bf4967876268f2b0c8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50754
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit 52e6194558.
Reason for revert: Graphics actually works now. I should have abandoned this CL.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I83aac3a2c616bb434706f23e36549760bc764080
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Some of the src/vendorcode/ directories are used to import a whole
codebase from somewhere else which uses a completely different coding
style. For those directories, excluding them from checkpatch makes
sense. However, other directories are simply implementing
vendor-specific extensions that were written by coreboot developers
specifically for coreboot in coreboot's coding style. Those directories
should be covered by checkpatch.
This patch narrows the existing blanket exception of src/vendorcode/ to
the amd, cavium, intel and mediatek directories (which actually include
large amounts of foreign source). The eltan, google and siemens
directories (which seem to contain code specifically written for
coreboot) will now be covered by checkpatch.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I1feaba37c469714217fff4d160e595849e0230b9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51827
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch disables checkpatch warnings about two style constructs that
are not illegal in coreboot style and can in my opinion be useful in
certain situations.
The first is an assignment in if conditions like this:
if ((ret = func()))
return ret;
This can save a line compared to the alternative construct which may
help readability, especially in functions that need to do a lot of
these. More importantly, the while-equivalent of this construct is not
forbidden (and a lot more useful, because certain things become very
complicated to write without it), and it seems weird to forbid one but
not the other. We already have GCC warnings that enforce an extra set
of parenthesis to highlight that this is an assignment instead of a
comparison, so the risk of typos or confusion between those two is
already mitigated anyway.
The second is the use of `else` after return like this:
if (CONFIG(TYPE_A))
return response_for_type_a;
else
return response_for_type_b;
While the else is redundant in this case, it serves to highlight the
symmetry and equivalence in importance of the two paths. There are
certainly other situations where the construct of
if (something_went_wrong)
return error;
if (something_else_went_wrong)
return other_error;
if (...)
is more useful, but this usually suggests an "either abort here or
continue on the main path" style flow, whereas the code with `else` is
more suitable to highlight an "either one or the other" flow with two
equal-weighted options. I think the programmer should pick which style
best represents the intentions of their code in these cases, and don't
understand why one of the two should be categorically forbidden.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I130598057c1800277a129ae6b927e961d6e26e42
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51551
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With the current version method, it's not possible to determine if
a different version is older or newer than the current version without
digging into the repository and finding the dates for the version
numbers.
This change adds the commit date to the start of the toolchain version
which will let us tell at a glance how old or new the toolchain is.
It's not perfect because multiple toolchain commits can go in on the
same day, but adding the time made the string even longer, and really
doesn't help that much.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I9c6d27667b922dc15e7a6e132e1beff69eed839c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
TPM_INIT is disabled by default. This prevents TPM to be operational
when VBOOT is disabled.
Remove the TPM_INIT disable.
BUG=N/A
TEST=tested on facebook monolith with VBOOT disabled.
Change-Id: I84d525a18c84643903922fef0a11dcf98abbbe4d
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Make sure the standard for the board options are set when VBOOT is
enabled.
BUG=N/A
TEST=tested on facebook monolith
Change-Id: I9749eeeffbd26e7c5caaeb7c0407a765cf093337
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52053
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Added new LPC and IGD device IDs for Alderlake M.
Also, added entry for CPUID_ALDERLAKE_M_A0 in report_platform.c
TEST=Check if platform information print is coming properly in coreboot
Change-Id: If33c43da8cbd786261b00742e342f0f01622c607
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50138
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable Bayhub SD card reader power-saving mode for Lindar and Lillipup.
BUG=b:173676531
TEST=Boot to OS and test with SD card function.
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I923d6e1beacd007c0e501f39c1f434c3e1085b9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This patch changes the mem_pool implementation to track the last two
allocations (instead of just the last) and allow them both to be freed
if the mem_pool_free() calls come in in reverse order. This is intended
as a specific optimization for the CBFS cache case when a compressed
file is mapped on a platform that doesn't natively support
memory-mapping flash. In this case, cbfs_map() (chaining through to
_cbfs_alloc() with allocator == NULL) will call
mem_pool_alloc(&cbfs_cache) to allocate space for the uncompressed file
data. It will then call cbfs_load_and_decompress() to fill that
allocation, which will notice the compression and in turn call
rdev_mmap_full() to map the compressed data (which on platforms without
memory-mapped flash usually results in a second call to
mem_pool_alloc(&cbfs_cache)). It then runs the decompression algorithm
and calls rdev_munmap() on the compressed data buffer (the latter one in
the allocation sequence), leading to a mem_pool_free(). The remaining
buffer with the uncompressed data is returned out of cbfs_map() to the
caller, which should eventually call cbfs_unmap() to mem_pool_free()
that as well. This patch allows this simple case to succeed without
leaking any permanent allocations on the cache. (More complicated cases
where the caller maps other files before cbfs_unmap()ing the first one
may still lead to leaks, but those are very rare in practice.)
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ic5c4c56a8482752ed65e10cf35565f9b2d3e4b17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
RETURN_FROM_VERSTAGE is a somewhat tricky construct that we don't
normally do otherwise in coreboot. While it works remarkably well in
general, new development can lead to unintentional interactions with
confusing results. This patch adds a debug print to the verstage right
before returning to the bootblock so that it's obvious this happens,
because otherwise in some cases the last printout in the verstage is
about some TPM commands which can be misleading when execution hangs
after that point.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I9ca68a32d7a50c95d9a6948d35816fee583611bc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52086
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
CBFS_VERIFICATION requires the CBFS metadata hash anchor to be linked
into an uncompressed stage, but for platforms using COMPRESS_BOOTBLOCK,
this is only the decompressor stage. The first CBFS accesses are made in
the bootblock stage after decompression, so if we want to make
CBFS_VERIFICATION work on those platforms, we have to pass the metadata
hash anchor from the decompressor into the bootblock. This patch does
just that. (Note that this relies on the decompressor data remaining
valid in memory for as long as the metadata hash anchor is needed. This
is always true even for OVERLAP_DECOMPRESSOR_ROMSTAGE() situations
because the FMAP and CBFS metadata necessarily need to have finished
verification before a new stage could be loaded.)
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I2e6d7384cfb8339a24369eb6c01fc12f911c974e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52085
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds file data hashing for CONFIG_CBFS_VERIFICATION. With
this, all CBFS accesses using the new CBFS APIs (cbfs_load/_map/_alloc
and variants) will be fully verified when verification is enabled. (Note
that some use of legacy APIs remains and thus the CBFS_VERIFICATION
feature is not fully finished.)
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ic9fff279f69cf3b7c38a0dc2ff3c970eaa756aa8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
With the last external user to cbfs_load_and_decompress() gone, we can
stop exporting this function to the rest of coreboot and make it local
to cbfs.c. Also remove a couple of arguments that no longer really make
a difference and fold the stage-specific code for in-place LZ4
decompression into cbfs_prog_stage_load().
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I4b459650a28e020c4342a66090f55264fbd26363
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52083
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This changes updates the iDisp-Link T-mode to 8T required for ADL-M.
The update is made because the HW on ADL now supports 8T mode.
BUG=None
TEST= build and boot ADL-M RVP and verify HDMI/DP audio playback.
Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com>
Change-Id: I9d0bf7dc76348f7e184e8496f042badc30bf3211
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51353
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
1. Configure Power Enable, Reset and Clock GPIO for both camera
2. Use same ASL code as ADL-P RVP
Configure RST, PWR_EN and IMGCLKOUT signals for WFC and UFC
TEST=Build, Boot and Verify streaming in both Camera
Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com>
Change-Id: I70636eaa8d9bdf23d649e811b3ff4f33b1bc604e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50265
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Config ANX7625 line data end same time on all line.
BUG=b:173603645
BRANCH=kukui
TEST=Display is normal on Kukui
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Change-Id: Ia1dc217138a98a79ef2f31225b52ba2b1aaf8672
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Just do it already.
The two SCSI-specific options for p2b-{ls,ds} will be wired up in a
followup. They will be ignored by boards without the hardware.
Change-Id: Ia43d502219d7c23d21f49d651113e3d653c6e9f4
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
These p-suffixed helpers allow dropping pointer casts in call-sites,
which is particularly useful when accessing registers at an offset from
a base address. Move existing helpers in chipset code to arch/mmio.h and
create the rest accordingly.
Change-Id: I36a015456f7b0af1f1bf2fdff9e1ccd1e3b11747
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51862
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit 023fdaffd1 (mb/asus/p2b: Refactor southbridge ACPI stuff)
moved the southbridge ACPI stuff to its own file. It also
(prematurely) listed PM and SMBus I/O port ranges as a #defined
fixed value.
Since these two ranges are not expected to change at runtime anyway,
we can simply drop the ASL code doing the read.
Change-Id: Id5adb37d047621d7c8faf81607ceea4cbcac3d34
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41093
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Martin Roth