Commit Graph

637 Commits

Author SHA1 Message Date
Jon Dufresne 208948787e In the file mainboard/intel/i82801dbm/i82801dbm.c the variable
southbridge_intel_i82801dbm_control should be named
southbridge_intel_i82801dbm_ops. Otherwise a compile error occurs if this
device is included in Config.lb of the mainboard.

Closes #62

Signed-off-by: Jon Dufresne <jon.dufresne@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2526 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-12-14 14:54:00 +00:00
chn f3938bbbbf In src/southbridge/intel/i82801ca, first the smbus registers are mapped at i/o
space offset 0x1000, and later is the acpi registers also mapped at 0x1000. 
This patch fixes this behavior. Closes #44

Signed-off-by: <chn@virtutech.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2523 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-12-14 00:43:50 +00:00
Uwe Hermann a7aa29b943 Use the canonical name of the vendors/devices and the
same format for all CHIP_NAME() entries in LinuxBIOS (Closes #20).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@linuxbios.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2490 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-11-05 18:50:49 +00:00
Stefan Reinauer eca92fb371 Uwe Hermann:
here's a patch which replaces all DOS newlines with Unix newlines, and
removes some useless $Rev$, $Id$, and $Header$ tags.
(part 1)



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2385 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-08-23 14:28:37 +00:00
Stefan Reinauer a14b46895c final rename orgy. sorry for the inconvenience. This should fix it again
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2363 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-08-04 07:50:59 +00:00
Stefan Reinauer c76b85d6a7 ouch. it's 8_2_371. I'll fix it. This commit breaks compilation
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2362 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-08-04 07:47:28 +00:00
Stefan Reinauer d34758f05a rename southbridge i440bx to its actual name i8371eb
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2361 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-08-04 07:45:45 +00:00
Richard Smith d7088c459c - Fix some copy bugs and thinkos in the i440bx SMbus
read code.  SBbus reads to RAM now work. Yah!  
- Rename the register constants to something I can look at 
more easily.
- Make the logic flow match the flow from V1 assembly 
- #if 0 out other SMbus functions that are still broken.



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2353 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-07-30 00:23:20 +00:00
Richard Smith cb8eab482f add framework for i440bx chipset
add support for NSC pc87351 SuperIO
add Bitworks/IMS manboard config

This is a very basic framework for the i440bx chipset and the 
Bitworks IMS board that uses it.  Most things are 
structure only.

Known issues:
- SMbus reads to the RAM SPD come back
all zero.
- dump_spd_registers() is commented out since it breaks with
the default setting of generic_dump_spd.c where it wants
2 memory controllers.



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2347 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-07-24 04:25:47 +00:00
Stefan Reinauer 84e4bf69c7 interesting behavior, i thought svn could do moves.
the result should be ok though..

the purpose is dropping the old i82801er southbridge code
and using the ich5r code instead because its the same chip
but the code looks more solid and is used by many more systems.

Some of the old i82801er features have been ported (like hpet enable)



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2241 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-06 21:40:36 +00:00
Stefan Reinauer 966d0e6d70 break the tree really quick due to svn restrictions, next commit fill fix it
again.



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2240 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-06 21:37:10 +00:00
Steven J. Magnani a25120a30f Bug fixes: read all 16 bits of DMA configuration; set up NMI/SERR handling in I/O space not PCI space. Comment out posted-memory-write code that looks to have been mis-inherited.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2046 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-21 13:54:18 +00:00
Steven J. Magnani ef79223156 Bug fixes: read all 16 bits of DMA configuration; set up NMI/SERR handling in I/O space not PCI space. Comment out posted-memory-write code that looks to have been mis-inherited.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2045 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-21 13:53:44 +00:00
Steven J. Magnani b140d56f63 Bug fix: enable secondary IDE only if enable_b is set.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2044 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-21 13:51:30 +00:00
Steven J. Magnani 3cec9c8433 Bug fix: enable secondary IDE only if enable_b is set.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2043 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-21 13:51:12 +00:00
Steven J. Magnani b3d2d4d441 Rewrite i82801er_enable to do nothing if device does not have an enable/disable bit.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2042 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-21 13:50:38 +00:00
Steven J. Magnani 7557331605 Rewrite i82801dbm_enable to do nothing if device does not have an enable/disable bit.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2041 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-21 13:49:44 +00:00
Steven J. Magnani 706aed8eb9 Initial revision.
Based on i82801er and LB v1 code.

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2036 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-14 15:34:03 +00:00
Steven J. Magnani 09e4ef6702 Cleanup. Only functional change is to drop hard-coding of vendor/subsystem ID.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2035 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-14 13:56:25 +00:00
Steven J. Magnani eb065f0620 Add some P64H2-specific definitions, remove some generic PCI ones.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2034 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-14 13:55:41 +00:00
Yinghai Lu 13f1c2af8b eric patch
1. x86_setup_mtrr take address bit.
        2. generic ht, pcix, pcie beidge...
        3. scan bus and reset_bus
        4. ht read ctrl to decide if the ht chain
           is ready
        5. Intel e7520 and e7525 support
        6. new ich5r support
        7. intel sb 6300 support.

yhlu patch
	1. split x86_setup_mtrrs to fixed and var
	2. if (resource->flags & IORESOURCE_FIXED ) return; in device.c pick_largest_resource
	3. in_conherent.c K8_SCAN_PCI_BUS


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1982 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-07-08 02:49:49 +00:00
arch import user (historical) 6ca7636c8f Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-51
Creator:  Yinghai Lu <yhlu@tyan.com>

cache_as_ram for AMD and some intel


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1967 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-07-06 17:17:25 +00:00
Ronald G. Minnich 284c27f299 fixes to make adl855pc compile.
fixes to emulator.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1806 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-28 04:39:45 +00:00
Ronald G. Minnich 8d41ad83be in loglevel.h, if ASM_CONSOLE_LOGLEVEL is defined, don't try to set it.
Set adl855pc ROM_SIZE to 1M
Other minor debug prints until we get this fixed.

We're almost as far along as we were before the Change :-)


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1780 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-11 14:04:25 +00:00
Eric Biederman 018d8dd60f - Update abuild.sh so it will rebuild successfull builds
- Move pci_set_method out of hardwaremain.c
- Re-add debugging name field but only include the CONFIG_CHIP_NAME is
  enabled.  All instances are now wrapped in CHIP_NAME
- Many minor cleanups so most ports build.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1737 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-04 11:04:33 +00:00
Yinghai Lu bf8bb42d6a *** empty log message ***
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1732 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-02 18:05:22 +00:00
Eric Biederman 6e53f50082 sizeram removal/conversion.
- mem.h and sizeram.h and all includes killed because the are no longer needed.
- linuxbios_table.c updated to directly look at the device tree for occupied memory areas.
- first very incomplete stab a converting the ppc code to work with the dynamic device tree
- Ignore resources before we have read them from devices, (if the device is disabled ignore it's resources).
- First stab at Pentium-M support
- add part/init_timer.h making init_timer conditional until there is a better way of handling it.
- Converted all of the x86 sizeram to northbridge set_resources functions.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1722 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-27 08:53:57 +00:00
Yinghai Lu e99433157b *** empty log message ***
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1707 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-22 21:03:26 +00:00
Eric Biederman 4f9265fdc6 - kill typo so resources are not mixed up in amdk8/northbridge.c
- Enable resources on the lpc bus.  PCI now longer do this by
  default for their children unless they are bridges.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1703 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-22 02:33:51 +00:00
Eric Biederman dbec2d4090 - Bump the LinuxBIOS major version
- Rename chip_config chip_operations throughout the tree
- Fix Config.lb on most of the Opteron Ports
- Fix the amd 8000 chipset support for setting the subsystem vendor and device ids
- Add detection of devices that are on the motherboard (i.e. In Config.lb)
- Baby step in getting the resource limit handling correct, Ignore fixed resources
- Only call enable_childrens_resources on devices we know will have children
  For some busses like i2c it is non-sense and we don't want it.
- Set the resource limits for pnp devices resources.
- Improve the resource size detection for pnp devices.
- Added a configuration register to amd8111_ide.c so we can enable/disable individual ide channels
- Added a header file to hold the prototype of isa_dma_init
- Fixed most of the superio chips so the should work now, the via superio pci device is the exception.
- The code compiles and runs so it is time for me to go to bed.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1698 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-21 10:44:08 +00:00
Eric Biederman 858ac5c5cd - Make all ports use config.h for if they have chip_config or chip_info structures.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1684 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-16 09:13:23 +00:00
Eric Biederman 7003ba4a88 - First stab at running linuxbios without the old static device tree.
Things are close but not quite there yet.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1681 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-16 06:20:29 +00:00
Ronald G. Minnich a4779e80c3 digital logic stuff, fixes for the smbus code in 82801dbm
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1652 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-09-30 16:37:22 +00:00
Ronald G. Minnich e6552bcf39 changes for the dbm part. Still need to remove the sata file ...
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1639 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-08-25 15:40:47 +00:00
Ronald G. Minnich 3b0096313a compiles.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1638 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-08-24 22:27:55 +00:00
Ronald G. Minnich 182615d635 new intel io hub.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1634 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-08-24 16:20:46 +00:00
Yinghai Lu 70093f7875 Intel E7501 P64H2 ICH5R support
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1616 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-07-01 03:55:03 +00:00