Code style fixes for the hp/dl145_g1 system board code.
Change-Id: I3c1a175d954e2d340e82c03c9f984699dcff865e
Signed-off-by: Oskar Enoksson <enok@lysator.liu.se>
Reviewed-on: http://review.coreboot.org/428
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
make w83697hf_set_clksel_48() non-static and add a prototype so as to
get rid of warnings about it being unused
Change-Id: I8ae94cfd61ae4774a367f83dd37e488987e2451a
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/380
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
valid_area will accept a region as valid for the payload if only a part
of coreboot fits in that region. This means if a payload reaches into a
neighboring RESERVED region, coreboot would not care and happily
overwrite that region, as long as the payload also writes to some RAM.
Change-Id: Ie263f83be18009b01a31c71e7285c998747d097f
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/425
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
http://review.coreboot.org/#change,378 introduced a function in k8x8xx.h
move this function to ctrl.c and add a prototype to the header file instead.
Change-Id: I0919ffb2030c53669b95f58b649d4a160f660923
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/429
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
- move cbfs_load_payload to the end so we can drop the prototype
- move lb_start and lb_end to the beginning so they can be used
in other functions.
- drop two unused function declarations
- break a 80+ characters line
- fix a comment
Change-Id: I460aa1e2ccf9d95ac12233af001076f73ab0268e
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/424
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Using RAMINIT_SYSINFO should be beneficial for this platform.
It is also more clean/safe to put data in struct mb_sysconf_t.
It's more consistent with other MB's and I've tested it
thoroughly on my DL145.
Signed-off-by: Oskar Enoksson <enok@lysator.liu.se>
Change-Id: Ie90a134a1efc9605b3fe17a5b5008856226984be
Reviewed-on: http://review.coreboot.org/236
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Instead of writing to config registers in k8x8xx's dram_enable()
and reading those back in vt8237r_cfg(), factor out generation of
the values and reuse that in both places.
Change-Id: I87a37398efe84b33e6678df74cd40b5abfe4f879
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/378
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
vt8237r_enable() so far wrote the function enable values to the same
offset in the config space of every one of the vt8237's functions,
even though the register is located in the ISA bridge only.
Change-Id: I639586dc238132f5b8d2f320b794948718281b9c
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/368
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This was split out when we had separate rules for big bootblock.
Change-Id: Id0a117f6996fb6bdef7bf97e7d80c36f5dec0ad7
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/404
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Fix multiple copy&paste errors and some other bugs in
devtree.asl. Redesign ENCM method to enter configuration mode
and set LDN by parameter. Reordered and commented some
statements to make the code a bit more readable. Add an ifdef
to enable never showing the keyboard controller as disabled,
which seems to cause bugs at least with some Linux kernels.
Remove keyboard controller IO regions from PS/2 mouse device
as e.g. Linux infers them from the keyboard controller device.
Change-Id: I44611339fabe31a8a584a3e6bd225082bfdd0b8e
Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
Reviewed-on: http://review.coreboot.org/357
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Drop explicit Scope(\_SB) from devtree.asl as it forces the SuperIO
to appear as child of the root device.
devtree.asl then needs to be included at a reasonable position inside
the \_SB device tree.
Change-Id: I72a57eddc5ec5f9763fdf789094a7be042758256
Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
Reviewed-on: http://review.coreboot.org/298
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The base is now calculated automatically, and all mentions of that
config option were typical anyway (4GB - XIP_ROM_SIZE).
Change-Id: Icdf908dc043719f3810f7b5b85ad9938f362ea40
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/366
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Adapted from northbridge/intel/e7501 with only minor changes.
This commit provides minimal patch from e7501 and I prefer any
cosmetic clean-up to be done after initial merge.
Due the incomplete register specifications, it is safer to have
e7505 as a separate directory in case I improve it to support
wider range of memory configurations. I have no e7501 to test with.
Change-Id: Iba3bf9d69ff5e9d9ef3a6ebf8259f048c55d637d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/295
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
- move enable_usbdebug() declaration to usbdebug.h
- reinitialize debug driver in ramstage, as copying the data
structure from romstage doesn't work right now. This way of copying
data from romstage to ramstage is really board/cpu specific, and is
likely to break often. So don't do it.
Change-Id: I394678ded6679c1803e29eb691b926182bdcab68
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/355
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
It is meant to be a address and not a dereference. Otherwise MTRR
is filled with code and not with the address.
This is what I hate at most on the AT&T syntax. Instead of taking
the address, it was a dereference. Not greatly visible, except
I wondered why opcode is not 0xb4 but 0xa1 and it took another
half an our to see it.
Change-Id: I6b339656024de8f6e6b3cde63b16b7ff5562d055
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/358
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Change-Id: I3ccb3860207e1b3ccac4313f7b537c434af5166f
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/360
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
No romstage is supposed to use usbdebug functions/defines
directly, so remove all those includes. The usb code is now
called and setup from console code.
Change-Id: I9b1120d96f5993303d6b302accc86e14a91f7a9f
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/354
Tested-by: build bot (Jenkins)
We added some new flag for certain AMD boards after support for
this board was submitted. Also integrate the mptable refactorings
that happened in the meantime.
Change-Id: I50cf50f343a740832fd1a14a2a1ef5b903315675
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/353
Tested-by: build bot (Jenkins)
Reviewed-by: Sven Schnelle <svens@stackframe.org>
The rule to prepare a new coreboot.pre1 was ignored in the
"update image" scenario because a perfectly fine file exists.
Mark it phony to fix it.
Change-Id: Ie7f8b36b71015a593958cd6e19602bad6b854320
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/351
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add a method WAKS to devtree.asl which returns the wake-up source register
to simplify retrieving the wake source e.g. in \_WAK.
Change-Id: Ia258f8fc9ff79b18391c55464da73863889e2255
Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
Reviewed-on: http://review.coreboot.org/297
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
it's a AMD 880+800 mainboard. I port the code
based on the AMD reference code.
update: 1.use CIMX instead of pmio
2.fix some whitespace
3.fix subsystemid of devicetree.cb
Change-Id: I9725ccdbb25365c4007621318efee80b131fec29
Signed-off-by: QingPei Wang <wangqingpei@gmail.com>
Reviewed-on: http://review.coreboot.org/205
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This change removes CONFIG_TINY_BOOTBLOCK, CONFIG_BIG_BOOTBLOCK, and
all their uses, assuming TINY_BOOTBLOCK=y, BIG_BOOTBLOCK=n.
This might break a couple of boards on runtime, but so far, fixes were
quite simple.
There's a flag day: Code that relies on CONFIG_TINY_BOOTBLOCK must be
adapted.
Change-Id: I1e17a4a1b9c9adb8b43ca4db8aed5a6d44d645f5
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/320
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
That value is now generated from a code address and CONFIG_XIP_ROM_SIZE.
This works as MTRRs are fully specified by their size and any address
within the range.
Change-Id: Id35d34eaf3be37f59cd2a968e3327d333ba71a34
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/348
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Linux implements it itself, but older Linuxes and other systems
might not. Without this, the host controller might not respond
to drivers.
Change-Id: I4ff0e3683c02e7aa00d188428847c64c4c5d589d
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/345
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Linux 2.4 is happier that way
Change-Id: I016609ae1e004ec856e8223893352dcdd061b291
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/346
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Choice between printk/print_ is related to CAR, but really
depends whether we compiled with GCC or ROMCC.
Change-Id: I9fe831a215736462e8b3f4b96ffe231133ecf79b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/347
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
called from console code, no need to call it here.
Change-Id: I4c34f89c82cc2478db8de4e98584e69d7ab0ca82
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/350
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The earlier fix for CMOS checksums only fixed the function rtc_set_checksum,
which would fix the checksum, but then coreboot would no longer honor the
settings because it assumed the checksum is wrong after this.
This change fixes the remaining functions.
Change-Id: I3f52d074df29fc29ae1d940b3dcec3aa2cfc96a5
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/342
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Linux 2.6.11 seems to require a certain order in CPUs listed in mptable,
so enforce it. This was only done on arima/hdama, but now is generic.
Unfortunately this is somewhat slow.
Change-Id: I85715ebae8a009cb816bc9ffd6372708f246bf66
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/280
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The code used PCI register 0x92 to enable sata ports,
which is wrong. The ICH7 documentation states:
"This register is only used in systems that do not
support AHCI. In AHCI enabled systems, bits[3:0] must
always be set (ICH7R only) / bits[2,0] must always be set
(Mobile only), and the status of the port is controlled
through AHCI memory space."
Writing 0x0f to ICH7-M doesn't seem to hurt, so lets write
0x0f for both variants. This patch makes sata_ahci work on
my Thinkpad T60 and X60s.
Change-Id: If3b3daec2e5fbaa446de00272ebde01cd8d52475
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/340
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Used by power management code to enable Cx powersaving modes.
Change-Id: I02c6b10762245bc48f21a341286236e203421de0
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/322
Tested-by: build bot (Jenkins)
It is safe to enable this setting on these Boards.
Change-Id: Iaa7377117743d18a95c496c25abf9fb4a1b20ad9
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/330
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Florian Zumbiehl