Update FSP header files to match FSP v77_12
Following fields have been added in FSP-S UPD:
- SkipPunitInit (Skip P-unit Initialization)
- HgSubSystemId (Sub system Vendor ID VGA)
Change-Id: I6c4c2580b2d0d76038b495be31744c04cc0dc959
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-on: https://review.coreboot.org/22820
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
There is a new UPD PcieRpClkSrcNumber introduced in FSP V2.9.2 to
configure clock source(s) of PCIe Root Ports. This UPD is used
to disable clock source(s) of disabled PCIe Root Port which
has active device connected.
CQ-DEPEND=CL:*520658,CL:*520659
BUG=b:
BRANCH=None
TEST= Build and boot soraka
Change-Id: Ia4e4d22be8b00a72de68ddde927a090d3441a76e
Signed-off-by: Balaji Manigandan B <balaji.manigandan@intel.com>
Reviewed-on: https://review.coreboot.org/22692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Update FSP header files to version 2.7.2.
New UPDs added
FspmUpd.h:
*CleanMemory
FspsUpd.h:
*IslVrCmd
*ThreeStrikeCounterDisable
Structure member names used to specify memory configuration
to MRC have been updated, SoC side romstage code is updated
to handle this change.
CQ-DEPEND=CL:*460573,CL:*460612,CL:*460592
BUG=b:65499724
BRANCH=None
TEST= Build and boot soraka, basic sanity check and suspend resume checks.
Change-Id: Ia4eca011bc9a3b1a50e49d6d86a09d05a0cbf151
Signed-off-by: Balaji Manigandan B <balaji.manigandan@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/21679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Cherry-pick from Chromium 414024e.
Update the FSP 1.1 header to version 1.1.7.0, required for
susequent Chromium cherry-picks and to-be-merged Braswell CrOS devices.
As this header update doesn't shift offsets, only adds new fields
in previously unused/reserved space, it should not negatively impact
existing boards built against the older header version.
Original-Change-Id: Ic378b3c10769c10d8e47c8c76b8e397ddb9ce020
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Original-Reviewed-by: Stefan Reinauer <reinauer@google.com>
Original-Tested-by: Martin Roth <martinroth@chromium.org>
Change-Id: Id33d41dee998cfa033264a98dfee40e2d8feead8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
A new UPD named SpiFlashCfgLockDown is added in the FSP-S
header file.
This change is going to come in FSP in the next FSP release.
This patch is pushed to urgently fix the SPI FPR locking issue.
CQ-DEPEND=CL:*414049
BUG=b:63049493
BRANCH=none
TEST=Built and boot poppy
Change-Id: I4725506103781a358b18ee70f4fdd56bf4ab3d96
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/20644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Updating headers corresponding to FSP 2.0.0
Below UPDs are added to FspmUpd.h
* PeciC10Reset
* PeciSxReset
rest of the changes are update to comments
CQ-DEPEND=CL:*340004,CL:*340005,CL:*340006
BUG=None
BRANCH=None
TEST=Build and test on Poppy
Change-Id: Id8ecea6fa5f4e7a72410f8da535ab9c4808b3482
Signed-off-by: Balaji Manigandan B <balaji.manigandan@intel.com>
Reviewed-on: https://review.coreboot.org/19109
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add the MemInfoHob.h provided by FSP v1.6.0 for aid in parsing the
MEM_INFO_DATA_HOB.
BUG=chrome-os-partner:61729
BRANCH=none
TEST=Build and boot KBLRVP
Change-Id: Ia2b528ba4d9f093006cc12ee317d02e7f3e83166
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/18326
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The FSP UPD offsets and the corresponding structure size do not match,
CpuConfigData.h needs an update to align the same. Hence update the
header file based on FSP version 1.4.0.
BUG=chrome-os-partner:61548
BRANCH=none
TEST=Built and booted KBLRVP and verify that all UPDs are in sync in
both coreboot and FSP.
Change-Id: I5ef7cbb569c3d1a44e7846717201952a0acf12ab
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/18285
Tested-by: build bot (Jenkins)
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
These updated header files contain USB tuning parameters as well as
some general cleanup of unused parameters in the UPD Headers. This
patch along with the upcoming FSP 1.3.0 release will allow for USB
tuning on apollolake platforms.
CQ-DEPEND=CL:*315403
BUG=chrome-os-partner:61031
Change-Id: Id7cce1ea83057630d508523ada18c5425804535e
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/18046
Reviewed-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This header update contains updates for skipping punit as well as some
MRC related UPD values.
BUG=chrome-os-partner:60068
BRANCH=none
TEST=built with FSP 1.2.3 and MRC patches for coreboot
CQ-DEPEND=CL:*307357
Change-Id: I8c66c0c0febba5e67ae3290034e9b095c9e68f07
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/17631
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
These header files contain a few new UPDs. The EnableS3Heci2
UPD will be used to save ~100ms from the S3 resume time on
Apollolake chrome platforms.
BUG=chrome-os-partner:58121
BRANCH=none
TEST=built coreboot for reef and verified no regressions
Change-Id: I1f324d00237c7150697800258a2f7b7eed856417
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/16869
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Add Kconfig values to select the FSP setup:
* FSP version: 1.1 or 2.0
* Implementation: Subroutine or SEC/PEI core based
* Build type: DEBUG or RELEASE
* Enable all debugging for FSP
* Remove USE_FSP1_1 and USE_FSP2_0
Look for include files in vendorcode/intel/fsp/fsp???/quark
BRANCH=none
BUG=None
TEST=Build FSP 1.1 (subroutine) and run on Galileo Gen2
Change-Id: I3a6cb571021611820263a8cbfe83e69278f50a21
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16806
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Add header files as is from FSP build output.
Move the FSP header files to new location as in apollolake.
Update all the FSP structure references now that they are
typedef'd.
Change-Id: I148bff04c064cf853eccaaaf7a465d0079c46b07
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16517
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit e96543e1 (vendorcode/intel: Add UDK 2015 Bindings)
had an extra underscore at the end of one of the make lines that
we missed in the review. Remove it.
Fixes this build warning:
.../Makefile.inc:34: Extraneous text after `ifeq' directive
Change-Id: I0bc76d827207b4f641ac5ff08f540a114347533b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16411
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
FSP header files should be located in vendorcode, not soc directory.
This patch includes changes any references to the old location to
the new location.
Change-Id: I44270392617418ec1b9dec15ee187863f2503341
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/16310
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add FSP 2.0 header files, these files are common for Skylake
and Kabylake, name the folder as skykabylake to signify the same.
Change-Id: I71b43a59c9a9b0adf1ee48285e4a72e24a13df2d
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16050
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Switch from passing FSP the serial port address to passing FSP the
serial port output routine. This enables coreboot to use any UART in
the system and also log the FSP output.
TEST=Build and run on Galileo Gen2
Change-Id: I67d820ea0360a3188480455dd2595be7f2debd5c
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16105
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Remove the TODO message from FspUpdVpd.h
TEST=Build and run on Galileo Gen2
Change-Id: Icd565c6062ef59b1e4a68310bb6f9ed62fb014af
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16114
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Specify the memory initialization parameters in
mainboard/intel/galileo/devicetree.cb. Pass these values into FSP to
initialize memory.
TEST=Build and run on Galileo Gen2
Change-Id: I83ee196f5fb825118a3a74b61f73f3728a1a1dc6
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15260
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Scan the boot block when building it with C_ENVIRONMENT_BOOTBLOCK
selected.
TEST=Build and run with Galileo Gen2
Change-Id: I922f761c31e95efde0975d8572c47084b91b2879
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15130
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Add car_stage_entry as an optional routine in the checklist.
TEST=Build and run on Galileo Gen2
Change-Id: I52f6aefc2566beac01373dbebf3a43d35032a0df
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15129
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Pass the serial port address to FSP using a UPD value in the MemoryInit
API.
TEST=Build and run on Galileo Gen2
Change-Id: I86449d80310b7b34ac503ebd2671a4052b080730
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15079
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Build the <board>_checklist.html file which contains a checklist table
for each stage of coreboot. This processing builds a set of implemented
(done) routines which are marked green in the table. The remaining
required routines (work-to-do) are marked red in the table and the
optional routines are marked yellow in the table. The table heading
for each stage contains a completion percentage in terms of count of
routines (done .vs. required).
Add some Kconfig values:
* CREATE_BOARD_CHECKLIST - When selected creates the checklist file
* MAKE_CHECKLIST_PUBLIC - Copies the checklist file into the
Documenation directory
* CHECKLIST_DATA_FILE_LOCATION - Location of the checklist data files:
* <stage>_complete.dat - Lists all of the weak routines
* <stage>_optional.dat - Lists weak routines which may be optionally
implemented
TEST=Build with Galileo Gen2.
Change-Id: Ie056f8bb6d45ff7f3bc6390b5630b5063f54c527
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15011
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Update the file to match the QuarkFsp code.
TEST=Build and run on Galileo Gen2
Change-Id: I090578d32165d34863548aec0e4a38fe915683c6
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14452
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This symbol was added to fix a Kconfig lint error after the
Broadwell DE vendorcode was added. Now that the chipset's in
the codebase, it's no longer needed.
Change-Id: Iedb166129c9265cc2cfcc406d98bde92c1a82d2f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14384
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: York Yang <york.yang@intel.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
The Kconfig lint tool is complaining because this symbol doesn't
exist. Create a temporary definition that can be removed when
the chipset is added.
Change-Id: I6a8abffcc91773aae16721ee1f48c4c64bd6b486
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14091
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Initial vendor codes to support Broadwell-DE SoC. This is FSP 1.0 based
project and is based on Broadwell-DE Gold release. Change has been
verified on Intel Camelback Mountain CRB.
Change-Id: I9262c9d70a58f0c7427f0658948adf080f2f6d8f
Signed-off-by: York Yang <york.yang@intel.com>
Reviewed-on: https://review.coreboot.org/14030
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The previous copy of FspUpdVpd.h was not up to date w.r.t. the
FSP release being used for skylake boards. Fix that.
BUG=chrome-os-partner:50863
BRANCH=None
TEST=Built and booted on chell.
Change-Id: I39896c04d35189b0fb2c903eefda4e5b7c57084a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fd647f354b8d9946b2217751cf1af845f29191b7
Original-Change-Id: I4ad131af6c563c9c33eb2b9207b13617ff24385d
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/331290
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/13984
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Set the UPD values for MemoryInit.
* Update the FspUpdVpd.h file which specifies the parameters for
MemoryInit.
* Add the necessary values to chip.h to enable values to come from
the mainboard's devicetree.cb file
* Add the parameters to the mainboard's devicetree.cb file
* Locate the platform configuration database file (pdat.bin)
* Copy the data values from the chip_info structure into the UPDs
* Display the UPD values
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file:
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate
UEFIPAYLOAD.fd
* Edit .config file and add the following lines:
* CONFIG_DISPLAY_UPD_DATA=y
* Testing successful when the UPD data is displayed before the call to
MemoryInit
Change-Id: Ic64f3d97eb43ea42d9b149769fc96bf78bf804f5
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13896
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Baytrail FSP MR 005 adds two new fields:
AutoSelfRefreshEnable
APTaskTimeoutCnt
Add the device tree definitions.
Change-Id: I12e2a8b0b5cbeb6b7289cf91f65b25e73007a8de
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: https://review.coreboot.org/12973
Tested-by: build bot (Jenkins)
Reviewed-by: York Yang <york.yang@intel.com>
Since this code is pulled in through commonlib, it will break compilation
of cbfstool on OSX.
Change-Id: I342bfa7e755aa540c4563bb5cd8cccacee39d188
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/13525
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Some trivial cleanup.
Change-Id: I866efc4939b5e036ef02d1acb7b8bb8335671914
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13427
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This corresponds with the changes that have already gone into the
soc/intel/skylake chip.h file and is needed to get skylake platforms
building again.
Change-Id: I15bfee4eff50d6632659953ec8f97a39d8810db3
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13022
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
