Drive SPKR_RST_L (GPP_A19) high at boot to take audio amps out of
reset.
BUG=b:78122599
BRANCH=none
TEST="emerge-nocturne coreboot chromeos-bootimage", boot to kernel,
and verify sound works via "aplay /dev/random"
Change-Id: Ia49931f2dc7802edc8a46114b081e4a96eeee604
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/26317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Use of device_t has been abandoned in ramstage.
Change-Id: I36f064b67f14556e38b41b7f64c3e27d8d935367
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Use of device_t has been abandoned in ramstage.
Change-Id: I751b72733de2e3bf3aebd1bc85dc83ec1c406faa
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
CpuMemoryTest in FSP tests 0 to 1M of the RAM after MRC init. With
PAGING_IN_CACHE_AS_RAM enabled for GLK, there was no page table
entry for this range which caused a page fault. Since this test
is anyway not exhaustive, we will skip the memory test in FSP.
There is an option to do PCIe power sequence from within FSP if provided
with the GPIOs used for PERST to FSP. Since we do this from coreboot,
will skip the PCIe power sequence done by FSP.
FSP does not know what the clock requirements are for the device on
SPI bus, hence it should not modify what coreboot has set up. Hence
skipping SPI clock programming in FSP.
CQ-DEPEND=CL:*627827
BUG=b:78599939, b:78599576, b:76058338
BRANCH=None
TEST=Build coreboot for Octopus board.
Change-Id: I4fa7a73fbb4676bb7af2416c8a33bf10ef41dd53
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-on: https://review.coreboot.org/26284
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add distclean targets so these can be called by the junit.xml test
target needed for jenkins testing.
Change-Id: I5991b43503da1778a6d74a57fbc0daf862e570d7
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/26433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Use of device_t has been abandoned in ramstage.
The function prototype for "struct device *add_cpu_device"
is already correct and doesn't need to be fixed.
Change-Id: I7bd8b93922f113bdaf7ba460acf6a7d62c4df013
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26067
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use of device_t has been abandoned in ramstage.
Change-Id: Iccddf3140fd94c2e5a246fe2839573f5dd387147
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Use of device_t has been abandoned in ramstage.
Change-Id: If92825f5bdb1399f61b7eba3ae81caa9c264a554
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Use of device_t has been abandoned in ramstage.
Change-Id: I499414c067b06fa94b53832894e804118f7c3e80
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Use of device_t has been abandoned in ramstage.
Change-Id: I37c6db65be4477dabb6064c3cc7ea1c63e467d19
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Use of device_t has been abandoned in ramstage.
Change-Id: Ia39347f9d07bb0055ea4686a8b319f323f68062e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Use of device_t has been abandoned in ramstage.
Change-Id: Ia46b909c78086d9417cabc1cd65e16d264a8df8e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26402
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The TP_Perf_STRUCT was missing from pi/00670F00. So I copied the file
from src/vendorcode/amd/pi/00630F01/Include/IdsPerf.h and removed
everything that we don't need. I did have to change
MAX_PERFORMANCE_UNIT_NUM so it matches the size used by pi/00670F00.
This struct is used to extract the timestamps from AGESA.
BUG=b:64549506
TEST=built on grunt
Change-Id: I06ec82348e3d10f2430c1192a925a49389ae4414
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/26235
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add 64KB to the reserved memory used for stage_cache. This corrects
an error observed when using a debug build of the AGESA blob.
Messages on initial boot
AGESA: Saving stage to cache
Error: Can't add stage_cache 57a9e101 to imd
and during resume
AGESA: Loading stage from cache
Error: Can't find stage_cache 57a9e101 in imd
TEST=boot/suspend/resume Grunt with debug and release builds
BUG=b:79154155
Change-Id: I3f27059fcef37e335d0301142ba4dedb3809e369
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/26386
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The firmware_Mosys FAFT test does not allow RW_SECTION_A, RW_SECTION_B or
RW_SHARED to be 0-sized, nor located at offset 0x00000000.
Swap UNIFIED_MRC_CACHE and RW_SECTION_A to pass this test.
BUG=b:79865447
TEST=test_that -b grunt ${IP} firmware_Mosys
Change-Id: If60919fd998ac786d58a5a258d7b5ded727db64b
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/26356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch enables the new bootblock compression feature on RK3399,
which requires moving MMU initialization into the decompressor stage and
linking the decompressor (rather than the bootblock) into the entry
point jumped to by the masked ROM.
RK3399's masked ROM seems to be using a bitbang SPI driver to load us
(very long pauses between clocking in each byte), with an effective data
rate of about 1Mbit. Bootblock loading time (as measured on a SPI
analyzer) is reduced by almost 100ms (about a third), while the
decompression time is trivial (under 1ms).
Change-Id: I48967ca5bb51cc4481d69dbacb4ca3c6b96cccea
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/26341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Masked ROMs are the silent killers of boot speed on devices without
memory-mapped SPI flash. They often contain awfully slow SPI drivers
(presumably bit-banged) that take hundreds of milliseconds to load our
bootblock, and every extra kilobyte of bootblock size has a hugely
disproportionate impact on boot speed. The coreboot timestamps can never
show that component, but it impacts our users all the same.
This patch tries to alleviate that issue a bit by allowing us to
compress the bootblock with LZ4, which can cut its size down to nearly
half. Of course, masked ROMs usually don't come with decompression
algorithms built in, so we need to introduce a little decompression stub
that can decompress the rest of the bootblock. This is done by creating
a new "decompressor" stage which runs before the bootblock, but includes
the compressed bootblock code in its data section. It needs to be as
small as possible to get a real benefit from this approach, which means
no device drivers, no console output, no exception handling, etc.
Besides the decompression algorithm itself we only include the timer
driver so that we can measure the boot speed impact of decompression. On
ARM and ARM64 systems, we also need to give SoC code a chance to
initialize the MMU, since running decompression without MMU is
prohibitively slow on these architectures.
This feature is implemented for ARM and ARM64 architectures for now,
although most of it is architecture-independent and it should be
relatively simple to port to other platforms where a masked ROM loads
the bootblock into SRAM. It is also supposed to be a clean starting
point from which later optimizations can hopefully cut down the
decompression stub size (currently ~4K on RK3399) a bit more.
NOTE: Bootblock compression is not for everyone. Possible side effects
include trying to run LZ4 on CPUs that come out of reset extremely
underclocked or enabling this too early in SoC bring-up and getting
frustrated trying to find issues in an undebuggable environment. Ask
your SoC vendor if bootblock compression is right for you.
Change-Id: I0dc1cad9ae7508892e477739e743cd1afb5945e8
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/26340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch adds more parameters to bootblock_main_with_timestamp() to
give callers the opportunity to add additional timestamps that were
recorded in the platform-specific initialization phase.
Change-Id: Idf3a0fcf5aee88a33747afc69e055b95bd38750c
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/26339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This reverts commit f3d99b6a65.
Reason for revert: We're now doing this through CBFS types instead, so
this shouldn't be needed anymore.
Change-Id: I9e0d5446365f8ecc045615e4ba1a1313080c9479
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/26448
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit 8ccf59a947.
This wasn't meant to be submitted yet and seems to be causing issues,
just as Patrick warned me..
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I8c4b57ba92ef4e0535e4975485188114a1084f09
Reviewed-on: https://review.coreboot.org/26452
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use of device_t has been abandoned in ramstage.
Change-Id: If540a8b0afb93c1ba8e901c4771228a43c1e6a14
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Use of device_t has been abandoned in ramstage.
Change-Id: I6002949fa90a46a2dd0e3519acbf2606bb679322
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Use of device_t has been abandoned in ramstage.
Change-Id: I48ab6d77be0201ac7b49b26e0366b6e3a1e5ac52
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Use of device_t has been abandoned in ramstage.
Change-Id: Ic4137bc4008d08e0e0d002e52c353fc29355ccb1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Use of device_t has been abandoned in ramstage.
Change-Id: I2ff065c863a9d2b480f7432c6280ef59917c8863
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26396
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use of device_t has been abandoned in ramstage.
Change-Id: I995981fbaaf8c22889920a81faae631b3fd3b2ef
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Use of device_t has been abandoned in ramstage.
Change-Id: Id8a5043015806d8a433a948fc1889ee867ca3aeb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Use of device_t has been abandoned in ramstage.
Change-Id: Ia4be6e9b81fe4627d84c9ed7589a3e6ef2bcede2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Use of device_t has been abandoned in ramstage.
Change-Id: Iac87af2f1a1e331fee70b89548a0d6bbc5839ea0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26410
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Use of device_t has been abandoned in ramstage.
Change-Id: I143617bb1a4ab1812ec50155861ae2f75060851b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Use of device_t has been abandoned in ramstage.
Change-Id: Iaca908cc9ba5d11468a97d2f43911db925b93f1e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Use of device_t has been abandoned in ramstage.
Change-Id: Ie48b42cf2999df075e23dc8ba185934b4e600157
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Use of device_t has been abandoned in ramstage.
Change-Id: I53acc7dd4ddf2787fc1e59d604cadc4f3b4cb49c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Use of device_t has been abandoned in ramstage.
Change-Id: I587b32e33af72a37be8299b9db2ce26ba825a689
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26407
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Use of device_t has been abandoned in ramstage.
Change-Id: I818f808e1cd8b156158251724352f8be6041030c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26418
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Bip should have different devicetree entries than Yorp; it doesn't have
a DA7219 audio codec (instead it uses ALC5682).
BRANCH=none
BUG=b:79771967
TEST=boot, no longer see DA7219 ACPI in console.
Change-Id: Ic63bbc51e122afc9fc2e8ec7fb024d18a3815b38
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/26342
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Change to 16bit read of the standard register.
Change-Id: Id085935eb17838c07bd78716158e622f45f56906
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Use of device_t has been abandoned in ramstage.
Change-Id: I59078ff96428d134f108ff2551556c8a7d2d3b37
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Use of device_t has been abandoned in ramstage.
Change-Id: I04a1fc27f67555132667e42f14fd0263a18b56c6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Use of device_t has been abandoned in ramstage.
Change-Id: Ib432d3c3ce2788b0138a1b0e852385ab4f9b65ee
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26425
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Use of device_t has been abandoned in ramstage.
Change-Id: Ic58bb58b88ffc309472ee9ffc8a9c8619659811b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Stack smashing was detected during raminit when not loading from MRC.
Adding CAR_GLOBAL to a struct inside raminit was suggested in
https://mail.coreboot.org/pipermail/coreboot/2018-May/086677.html in
order to fix the problem.
Adding CAR_GLOBAL to the ram timings variable solves the issue (adding
it to the ram_training or raminfo struct had no effect).
This is just a workaround and might need a proper fix in the future.
Tested on Lenovo X201i with 2+2 and 4+4 GB RAM.
Change-Id: I21b380db61be2aedc045201821d83e18e7d07ad1
Signed-off-by: Matthias Gazzari <mail@qtux.eu>
Reviewed-on: https://review.coreboot.org/26388
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Use of device_t has been abandoned in ramstage.
Change-Id: Id634edd7005db85690cdc93579c1f97588ffc5f8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Use of device_t has been abandoned in ramstage.
Change-Id: Ie16a1c131ec41eeccc0bf5235b3fc2341095d4a8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Use of device_t has been abandoned in ramstage.
Change-Id: I9841fa591c4051653267b9e7c2f5b347d6f25b74
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Use of device_t has been abandoned in ramstage.
Change-Id: I85aafdc204731734ba4f02551ba5ccdd6535df77
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Use of device_t has been abandoned in ramstage.
Change-Id: I265130532965c1655c34fd7dab6ca9ef0e27beca
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Use of device_t has been abandoned in ramstage.
Change-Id: Iace820ad788fde7b230f63d95543470ce925b451
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26417
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Use of device_t has been abandoned in ramstage.
Change-Id: I2335b7e193663bb6c82bf267aaeb0b2367986f62
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
It turns out that even with the `-gnatp` switch to suppress runtime
checks, the compiler is still allowed to generate them (it only doesn't
have to). If we can't control generation of checks, we also can't
make assumptions about propagation of their exceptions.
The compiler warning that led to this change seems spurious, though
(the check might be generated, but is dropped later). So we might
revert this decision if the compiler can be fixed.
Change-Id: I7470d74b1f96f90d0d15b24dfd636d5f1c778d46
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/26350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Add a new RAM ID of memrory PN:K4F6E3S4HM-MGCJ
BUG=b:78491470
TEST= emerge-coral coreboot chromeos-bootimage.
Change-Id: Ic40e36ab222572945f8588eb3df063e4fe0dbeb5
Signed-off-by: Ren Kuo <Ren.Kuo@quantatw.com>
Reviewed-on: https://review.coreboot.org/26365
Reviewed-by: Ren Kuo <ren.kuo@quantatw.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Code is not used with EARLY_CBMEM_INIT and it
appears to have been invalid register anyways.
Change-Id: If0662937b38aec71292113ce8abd88da0b73feee
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-by: Martin Roth <martinroth@google.com>
This patch ensures that user can select a specific AP to run
a function.
BUG=b:74436746
BRANCH=none
TEST=Able to run functions over APs with argument.
Change-Id: Iff2f34900ce2a96ef6ff0779b651f25ebfc739ad
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26034
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With the recent change 4c518e1 (timestamp: Add timestamps for TPM
communication) to add more timestamps for TPM communication, now we
are overflowing the TIMESTAMP region in verstage. This change
increases TIMESTAMP region size to 512 bytes to accomodate this.
BUG=b:79888151, b:79974682
Change-Id: I94c5403f256f0176d10ac61e9e1f60adf80db08b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Describe the USB devices in the devicetree so they can get
generated into the SSDT and presented to the OS.
This was tested on an eve board and the resulting SSDT was
verified to show the expected values in _UPC and _PLD.
Change-Id: I292426f588ea74d61a5c4e4b01386bb18834c117
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/26176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
To support generating USB devices in ACPI the platform needs to
know how to determine a device name for each USB port, and for any
root hubs that may be present.
The AMD Stoney Ridge platform has separate controllers for USB 2.0
and USB 3.0. The USB 2.0 ports are connected through a hub to an
EHCI controller while the USB 3.0 ports are directly connected to
the xHCI controller.
This topology is described in ACPI and the port names are exposed
by the soc_acpi_name() function.
The USB controllers are configured to scan for static USB devices
in the devicetree and use the soc_acpi_name() function to identify
them.
Change-Id: I2bb677f84a49d2531929985dba319455b88e1686
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/26175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
To support generating USB devices in ACPI the platform needs to
know how to determine a device name for each USB port, and for
any root hubs that may be present.
Recent Intel platforms route all ports to an XHCI controller
through a root hub. This is supported by considering the root
hub to be USB port type 0, the USB 2.0 ports to be type 2, and
the USB 3.0 ports to be type 3.
This was tested with a Kaby Lake platform by adding entries to
the devicetree and checking the resulting SSDT.
Change-Id: I527a63bdc64f9243fe57487363ee6d5f60be84ca
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/26174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add a support for generating USB port descriptors for ACPI based
on their definition by the board in devicetree.cb. This will
generate a _UPC and _PLD for each port, using a generic _PLD by
default. The _PLD can also be customized for more accurate
descriptions if necessary.
This sample devictree.cb shows a USB 2.0 type-A port behind a root
hub connected to an xHCI controller:
device pci 14.0 on
chip drivers/usb/acpi
register "desc" = ""Root Hub""
register "type" = "UPC_TYPE_HUB"
device usb 0.0 on
chip drivers/usb/acpi
register "desc" = ""USB 2.0 Type-A""
register "type" = "UPC_TYPE_A"
device usb 2.0 on end
end
end
end
end
It will generate the following ACPI code in the SSDT:
Scope (\_SB.PCI0.XHCI.RHUB.HS01)
{
Name (_DDN, "USB 2.0 Type-A")
Name (_UPC, Package (0x04)
{
0xFF,
0x00,
Zero,
Zero
})
Name (_PLD, ToPLD (
PLD_Revision = 0x2,
PLD_IgnoreColor = 0x1,
PLD_Red = 0x0,
PLD_Green = 0x0,
PLD_Blue = 0x0,
PLD_Width = 0x0,
PLD_Height = 0x0,
PLD_UserVisible = 0x1,
PLD_Dock = 0x0,
PLD_Lid = 0x0,
PLD_Panel = "UNKNOWN",
PLD_VerticalPosition = "CENTER",
PLD_HorizontalPosition = "CENTER",
PLD_Shape = "RECTANGLE",
PLD_GroupOrientation = 0x0,
PLD_GroupToken = 0x0,
PLD_GroupPosition = 0x0,
PLD_Bay = 0x0,
PLD_Ejectable = 0x0,
PLD_EjectRequired = 0x0,
PLD_CabinetNumber = 0x0,
PLD_CardCageNumber = 0x0,
PLD_Reference = 0x0,
PLD_Rotation = 0x0,
PLD_Order = 0x0,
PLD_VerticalOffset = 0x0,
PLD_HorizontalOffset = 0x0)
)
}
Change-Id: I7024390e407fda4b195211bd4755bb5ca53b2b37
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/26173
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Instead of just checking the immediate parent for an device name,
walk up the tree to check if any parent can identify the device.
This allows devices to be nested more than one level deep and
still have them identified in one place by the SOC.
Change-Id: I9938fc20a839db91ff25e91bba08baa7421e3cd4
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/26172
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is now unused, since all intel northbridges now use the
equivalent in drivers/mrc_cache.
Change-Id: I3e4b4afa53acc0a82b4ba961f13f816b04931fea
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23485
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The common mrc cache driver allows to save the raminit training
results to a separate fmap region which is more manageable than a
cbfsfile.
Change-Id: I25a6d3fe5466d142e3d10429a87b19047040c251
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
In case the Option ROM isn't a multiple of 4KiB the last buffer was
truncated to prevent a buffer overrun. But tests on nouveau showed
that nouveau expects a buffer that has the requested size and is zero
padded instead.
Always return a buffer with requested size and zero pad the remaining
bytes. Fixes nouveau on Lenovo W520 with Option ROM not being multiple
of 4 KiB.
Change-Id: I3f0ecc42a21945f66eb67f73e511bd516acf0fa9
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/25999
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Rikken <nico@nicorikken.eu>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Use of device_t has been abandoned in ramstage.
Change-Id: I661b2435d9f0306b246a3e89aac24eb30c959085
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26253
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Use of device_t has been abandoned in ramstage.
Change-Id: I5c18fdc24bd0432f6b7a1131af68c792d377c3ac
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Use of device_t has been abandoned in ramstage.
Change-Id: I2176ea83fac30052c02d9f6e98c89c40436a38e8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Use of device_t has been abandoned in ramstage.
Change-Id: I7d9d0a205f9a650eb87bc8f90f2a28a5c4b2891c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Use of device_t has been abandoned in ramstage.
Change-Id: I10fb736a7406a6571dffce883fb82c2711526762
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
The I2C CLKs of SoC should be 400kHz, but waveform show 460kHz to
470kHz. Add I2C parameters to adjust I2C CLKs which 5% lower than
400kHz.
BUG=b:78819970
TEST=The I2C CLKs are 5% lower than 400kHz.
Change-Id: I2c3012b5b59c089801cda8fd7b0c433aad9df36d
Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/26282
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The CNVi wifi/bt module prevents entry into S5 by keeping internal
SoC clocks running. Therefore it's necessary to disable BT prior to
S5 entry.
BUG=b:79606769
TEST= Test if BT device works under following cases:
1. Power-on
2. Press powerbtn before OS entry
3. Power-on from S5 again
Change-Id: Ibc14b4080a27de48d197e16d0eed162603482de2
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/26238
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Provide a valid ACPI path for coreboot's SSDT generators.
Fixes all ACPI errors found while booting GNU Linux 4.15 on
Lenovo T410.
Change-Id: Idd4986f39f21cb53cb019d0893d40fed94c6505b
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/26287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Update dptf.asl from tuning of the thermal team.
BUG=b:72974136
TEST=Match the result from DPTF UI.
Change-Id: I21ddc337359c3e11ad9756e61ba174b33dfc3c75
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/26209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Increase AP timeout limit for sgx_configure function. As per debug log
sgx_configure was not successful on all cores with given timeout value.
TEST=Ensures no timeout error in AP function execution.
Change-Id: Ia83f7a7eb6cd6c4808d55febfebe32724a633173
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@google.com>
Since there are two ALS device nodes on Nami, need to remove one.
BUG=b:79227879
BRANCH=master
TEST=Verify if only one ALS node is found in /sys/bus/iio/devices
Change-Id: I850af06bec833739afa0c8c516d351d81952ce2c
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/26271
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Make cbfsf_file_type public to support detecting the payload type at
runtime. To be used by the following commits.
Possible payload types are:
* simple ELF
* FIT
Change-Id: I37e9fb06f926dc71b001722a6c3b6205a2f20462
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25859
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Store the type of the loaded program after locating the file and add a
method to retrieve the type.
Will be used to distinguish between SELF and FIT payloads.
Change-Id: Ic226e7e028d722ab9e3c6f7f1c22bde2a1cd8a85
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/26028
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To calculate the CBMEM address we need to determine the framebuffer
size early in the ROMSTAGE. We now do the calculation before
cbmem_recovery() and configure the memory controller right away.
If the calculation was done from cbmem_top() instead, we'd loose some
logging that seems useful, since printk() would recurse to cbmem_top() too
with CONSOLE_CBMEM enabled.
If we didn't configure the memory controller at this point, we'd
need to store the result somewhere else. However, CAR_GLOBAL is not
practical at this point, because calling car_get_var() from cbmem_top()
would recurse back to cbmem_top().
Change-Id: Ib9ae0f97f9f769a20a610f8d76f14165fb924042
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/25798
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This reverts commit 717ba74836.
This breaks seabios and a few other payloads. This is not
ready for use.
Change-Id: I48ebe2e2628c11e935357b900d01953882cd20dd
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/26310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Because thermal table is not included the values of DPTF_TSR1_ACTIVE_AC
from internal nami/vayne thermal team. Add conditional compilation
in _ACx methods if DPTF_ENABLE_FAN_CONTROL is defined in the dptf.asl.
BUG=b:72974136
TEST=Match the result.
Change-Id: I4b593118ca460a59aa49786cb99df417d135112a
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/26210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add APIs and required parameters for creating Realtek 5682 SSP
endpoint in NHLT table.
BUG=b:79235534
TEST=check that NHLT table defined is created properly.
With the series merged & required driver support in kernel.
Verify Headset Audio playback.
Change-Id: Ic26a0b881f77af64ba00fd714b08c0f17c0acb3d
Signed-off-by: Naveen Manohar <naveen.m@intel.com>
Reviewed-on: https://review.coreboot.org/26057
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Kyösti Mälkki