Commit Graph

48613 Commits

Author SHA1 Message Date
Lean Sheng Tan c856313f08 3rdparty/fsp: Update submodule pointer to latest master
The latest master adds the missing MemInfoHob.h to IOT ADL-P &
ADL-S folders.

Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I8ef998b2e414d3d63494e6177b4fde2dc26e9d55
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
2022-08-03 13:31:59 +00:00
David Wu 5f9849ebd5 mb/google/brya: Enable DRIVERS_GENESYSLOGIC_GL9755 for kuldax
Enable DRIVERS_GENESYSLOGIC_GL9755 support for kuldax.

BUG=b:232858957
TEST=build pass

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I1b2c0bff8497d727c697ea6287078055a39bd1f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2022-08-03 12:46:15 +00:00
Tony Huang f3e5f9966f mb/google/brya/variants/agah: set tcc_offset to 3
Set tcc_offset value to 3 in devicetree for Thermal Control Circuit
(TCC) activation feature. This value is suggested by Thermal team.

BUG=b:240600260
TEST=emerge-draco coreboot
     verified by thermal team

Change-Id: I3044643d52f1d6e883beb3ec87a77f32d086f46c
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-08-03 12:45:52 +00:00
Meera Ravindranath d307d0d2fb soc/soc/intel: Add UFS device with ref-clk-freq property
UFS storage devices require the bRefClkFreq attribute to be set to
operate correctly in high speed mode. The correct value is determined by
what the SoC / board supports. For the ADL UFS controller, it is
19.2 MHz.

a) Introduce a new ACPI property "ref-clk-freq".
b) Add support to configure this property using an SoC Kconfig.

Kernel patch:
https://web.archive.org/web/20220801060732/https://lore.kernel.org/all/
20220715210230.1.I365d113d275117dee8fd055ce4fc7e6aebd0bce9@changeid/

BUG=b:238262674
TEST=Build,boot Nirwen and dump SSDT entries and check that the kernel
correctly parses ref-clk-freq as 19.2 MHz.

Scope (\_SB.PCI0)
    {
        Device (UFS)
        {
            Name (_ADR, 0x0000000000120007)  // _ADR: Address
            Name (_DDN, "UFS Controller")  // _DDN: DOS Device Name
            Name (_DSD, Package (0x02)  // _DSD: Device-Specific Data
            {
                ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301")
                /* Device Properties for _DSD */,
                Package (0x01)
                {
                    Package (0x02)
                    {
                        "ref-clk-freq",
                        0x0124F800
                    }
                }
            })
        }
    }

Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Change-Id: I80c338a8a61f161b0feb6c5a3ca00cf5e0cfb36c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66051
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-08-03 12:45:20 +00:00
Felix Held 3046948867 soc/amd/sabrina/fch: enable XTAL pad disabling in S0i3
Switching off the pads of the internal crystal oscillator that connect
to the crystal on the board in S0i3 saves a little power, so enable it.
No measurements to quantify the power savings have been made. PPR #57243
revision 1.59 was used as a reference.

BUG=b:237647468
TEST=None

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I52f14ae5c614ad8ff0479b619de7164afa1e7648
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66336
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2022-08-03 12:44:18 +00:00
Vinod Polimera 4ce67c02b2 mb/google/herobrine: Add support to enable display
This change adds support to enable edp gpios, display init for
herobrine.

BUG=b:182963902,b:216687885
TEST=Validated on qualcomm sc7280 development board.
Monitor name: LQ140M1JW49

Change-Id: I01dbe23afbb3d41d87f24cb7dcfa456cb7f133fb
Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64885
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-03 03:26:13 +00:00
Vinod Polimera 4e93e94c7c qualcomm/sc7280: Add support for edp and mdp driver
- Add support for edp aux read and write.
- Update edp panel properties based on edid read.
- Configure edp controller and edp phy.

Panel details:
Manufacturer: SHP Model 1523 Serial Number 0
Made week 53 of 2020
EDID version: 1.4
Digital display
8 bits per primary color channel
DisplayPort interface
Maximum image size: 31 cm x 17 cm
Gamma: 220%
Check DPMS levels
Supported color formats: RGB 4:4:4
Default (sRGB) color space is primary color space
First detailed timing is preferred timing
Supports GTF timings within operating range
Established timings supported:
Standard timings supported:
Detailed timings
Hex of detail: 5a8780a070384d403020350035ae10000018
Detailed mode (IN HEX): Clock 346500 KHz, 135 mm x ae mm
               0780 07b0 07d0 0820 hborder 0
               0438 043b 0440 0485 vborder 0
               -hsync -vsync
Did detailed timing
Hex of detail: 653880a070384d403020350035ae10000018
Detailed mode (IN HEX): Clock 144370 KHz, 135 mm x ae mm
               0780 07b0 07d0 0820 hborder 0
               0438 043b 0440 0485 vborder 0
               -hsync -vsync
Hex of detail: 000000fd003090a7a7230100000000000000
Monitor ranges (bare limits): 48-144Hz V, 167-167kHz H, max dotclock
350MHz
Hex of detail: 000000fc004c513134304d314a5734390a20
Monitor name: LQ140M1JW49

Changes in V2:
- Remove Misc delays in edp code.
- Move mdss soc code to disp.c
- Update EDID read using I2C write & read.
Changes in V3:
- Remove unrelated delays.
- Misc changes.

BUG=b:182963902,b:216687885
TEST=Validated on qualcomm sc7280 development board.
Monitor name: LQ140M1JW49

Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com>
Change-Id: If89abb76028766b19450e756889a5d7776106f95
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61342
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2022-08-03 03:26:13 +00:00
Vinod Polimera 7528311929 commonlib: Add support for rational number approximation
This patch adds a function to calculate best rational approximation
for a given fraction and unit tests for it.

Change-Id: I2272d9bb31cde54e65721f95662b80754eee50c2
Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66010
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-03 03:26:13 +00:00
Paul Menzel 65377eba7f Makefile.inc: Disable compiler warning array-compare for GCC
gcc 12 fails the build with the warning below:

        CC         romstage/lib/cbfs.o
    src/lib/cbfs.c: In function 'switch_to_postram_cache':
    src/lib/cbfs.c:31:32: error: comparison between two arrays [-Werror=array-compare]
       31 |         if (_preram_cbfs_cache != _postram_cbfs_cache)
          |                                ^~
    src/lib/cbfs.c:31:32: note: use '&_preram_cbfs_cache[0] != &_postram_cbfs_cache[0]' to compare the addresses

Instead of following gcc’s suggestion, disable the warning for gcc as
requested by Julius [1]:

> Can we just set -Wno-array-compare instead? There's nothing illegal
> about that expression and as we can see in this case, there are
> perfectly reasonable cases where you might want to do something like
> that. On the other hand, I don't really see a realistic scenario where
> this warning could prevent a real problem (anyone who doesn't know
> that array1 == array2  doesn't compare the array elements in C
> shouldn't have any business submitting code to coreboot).

[1]: https://review.coreboot.org/c/coreboot/+/62827/1

Found-by: gcc-12 (Debian 12-20220313-1) 12.0.1 20220314 (experimental) [master r12-7638-g823b3b79cd2]
Found-by: gcc (Debian 12.1.0-7) 12.1.0
Change-Id: I322f7cc57dcca713141bddaaaed9ec034898754d
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66105
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-08-02 21:16:52 +00:00
Meera Ravindranath be5dc3daa0 soc/intel/alderlake: Configure DDR5 Physical channel width to 64
A DDR5 DIMM internally has two channels each of width 32 bit.
But the total physical channel width is 64 bit.

BUG=b:180458099
TEST=Boot DDR5 to kernel

Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: Ic5e9c58f255bdf86a68ce90a4f853bf4e7c7ccfe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52730
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-08-02 18:32:20 +00:00
FrankChu b85997df25 mb/google/dedede/var/pirika: Add Elan touchscreen support
Enable I2C2 and register touchscreen ACPI device for pirika.

BUG=b:236564261
TEST=touch screen is functional.

Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: Id2fd5606b7126eabc1c88bf516198ff00b5d75dd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-08-02 17:14:28 +00:00
Eric Lai 71a488d428 mb/google/brya/var/ghost: Enable AMP power
Follow latest schematic, GPP_A17 is used to enable AMP power.

BUG=b:240006200
BRANCH=firmware-brya-14505.B
TEST=Check I2C scan can see the AMP return ACK.

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ia6c52302a12ddec68303714ac07e96a65a8f8fb8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66325
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
2022-08-02 17:14:12 +00:00
Tim Crawford 57fecef66f mb/system76: Change touchpad detection method
Use the new "detect" method instead of "probed". Fixes an uncommon issue
where i2c-hid fails to initialize the device on Linux.

Tested on: gaze15, gaze16-3060, lemp10, oryp8

Tested:
- Linux: Touchpad works across 50 reboots
- Windows: Touchpad is still detected as an I2C HID device
- Windows: Extra I2C HID devices are not shown in Device Manager

Change-Id: I6a899c64a6d77b65a2ae57ab8df81cd84b568184
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-08-02 15:51:16 +00:00
Rex-BC Chen 1250820916 mb/google/geralt: Enable Chrome EC
Initialize SPI bus 0 for Chrome EC control.

TEST=build pass
BUG=b:236331724

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I6de5ea8a0273a3b0c725e4cdbcf69f4db74c5db7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-08-02 12:20:52 +00:00
Matt DeVillier 4c24606637 payloads/tianocore/Makefile: Fix restoring default boot logo
the missing `; \` at the end of the line meant subsequent lines
were no longer run from $project_dir, so Logo.bmp was silently
failing to restore. This led to the working dir being dirty,
and on subsequent runs, any change to a different branch in the
same repo would fail.

Change-Id: I17a323bc2dda19b69d809e398b273f24e14b43af
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66321
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-02 12:19:34 +00:00
Tim Crawford b739d80197 soc/intel/alderlake: Add IRQ constraints for CPU PCIe ports
Copy the constraint from ADL-S to ADL-P.

Fixes the following warning in Linux on System76 oryp9, which has an
NVIDIA GPU on the bridge.

    pcieport 0000:00:01.0: can't derive routing for PCI INT A

This, in turn, resolves an IRQ conflict with the PCH HDA device that
would cause a stack track on every boot.

    irq 10: nobody cared (try booting with the "irqpoll" option)
    <snip>
    [<00000000bf549647>] azx_interrupt [snd_hda_codec]
    Disabling IRQ #10

Change-Id: I550c80105ff861d051170ed748149aeb25a545db
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66285
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-02 12:19:17 +00:00
Simon Yang 60ac26521e mb/google/nissa/craask: Add eMMC DLL tuning value
Configure eMMC DLL tuning values for Craask board.

BUG=b:238985924
TEST="Use the value to boot on Nivviks and Craask successfully."

Change-Id: I14f3e2329404cca94e14034d1fb52fcb99a2ddc9
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66218
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-08-02 08:12:00 +00:00
Subrata Banik 1bc4bb75fb mb/google/rex: Enable CSE Lite SKU
The first CSE Lite SKU is available, therefore enable the Kconfig
option to have the CSE reboot the system into its RW FW during a cold
boot.

BUG=b:240228892
TEST=TBD

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I00ef4176cf08cbeed06e446cfe68f06cb1ea27b4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66287
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-02 07:10:30 +00:00
Subrata Banik 8b468400f1 util/cbfstool/elogtool: Support logging FW vboot info in elog
List of changes:
1. Add support for new elog event type to log vboot info (type 0xB7).
2. Add support string for fw_slot name, boot status and boot mode.
3. Print fw slot information like FW try count, FW current slot,
    previous FW slot, previous FW boot result and boot mode.

BUG=b:215615970
TEST=Able to build and boot google/kano to OS.
localhost # elogtool list
0 | 2022-07-01 11:10:27 | Log area cleared | 4088
1 | 2022-07-01 11:10:27 | Memory Cache Update | Normal | Success
2 | 2022-07-01 11:10:42 | System boot | 360
3 | 2022-07-01 11:10:42 | Power Fail
4 | 2022-07-01 11:10:42 | SUS Power Fail
5 | 2022-07-01 11:10:42 | ACPI Wake | S5
6 | 2022-07-01 11:10:42 | Wake Source | Power Button | 0
7 | 2022-07-01 11:10:42 | Chrome OS Developer Mode
8 | 2022-07-01 11:10:42 | Firmware vboot info |
                          boot_mode=Developer |
                          fw_tried=B | fw_try_count=0 |
                          fw_prev_tried=B | fw_prev_result=Unknown
9 | 2022-07-01 11:11:42 | System boot | 361
10 | 2022-07-01 11:11:42 | System Reset
11 | 2022-07-01 11:11:42 | Firmware vboot info |
			  boot_mode=Developer |
			  fw_tried=B | fw_try_count=0 |
			  fw_prev_tried=B | fw_prev_result=Success

localhost # crossystem recovery_request=1
localhost # elogtool list
41 | 2022-07-13 12:13:48 | Firmware vboot info |
			  boot_mode=Manual recovery boot |
		          recovery_reason: 0x1/0 (Recovery requested
			  from legacy utility) | fw_tried=A |
			  fw_try_count=0 | fw_prev_tried=A |
			  fw_prev_result=Unknown

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I48b5d54723683cef51e416fc6f58da000507fbcc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65562
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-02 07:06:52 +00:00
Subrata Banik 2d20b68b6e vc/google/elog: Record vboot FW boot information into elog
This patch calls into vboot API (vb2api_get_fw_boot_info) to retrieve
FW slot boot information like (tries count, current boot slot, previous
boot slot, previous boot status and boot mode).

Upon retrieval of the vboot information, elog callback from ramstage
records the info into the eventlog.

Additionally, this patch refactors the existing event logging mechanism
to add newer APIs to record vboot firmware boot related information.

BUG=b:215615970
TEST=Build and boot google/kano to ChromeOS and run below command to
check the cbmem log:
Scenario 1:
localhost ~ # cbmem -c | grep VB2
[INFO ]  VB2:vb2_check_recovery() Recovery reason from previous boot:
         0x0 / 0x0
[INFO ]  VB2:vb2api_fill_boot_config() boot_mode=`Developer boot`
         VB2:vb2api_get_fw_boot_info() fw_tried=`A` fw_try_count=0
            fw_prev_tried=`A` fw_prev_result=`Success`.
....

Scenario 2:
localhost ~ # crossystem recovery_request=1
localhost ~ # cbmem -c | grep VB2
[INFO ]  VB2:vb2api_fill_boot_config() boot_mode=`Manual recovery boot`
         VB2:vb2api_fill_boot_config() recovery_reason=0x13 / 0x00
         VB2:vb2api_get_fw_boot_info() fw_tried=`A` fw_try_count=0
            fw_prev_tried=`A` fw_prev_result=`Unknown`.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I6882cd1c4dbe5e24f6460388cd1af4e4a05fc4da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65561
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-02 07:06:30 +00:00
Subrata Banik 8c2cef02ac Update vboot submodule to upstream main
Updating from commit id a975eed306:
   2kernel.c: check display request in vb2api_kernel_phase2
to commit id 18cb85b52d:
   2load_kernel.c: Expose load kernel as vb2_api

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I58c5d54723683cef51e416fc6f58da000507fbcc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66269
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-02 07:06:17 +00:00
Fred Reitberger fdb0758256 soc/amd/common/block/apob/apob_cache.c: Add assert for APOB DRAM size
Add static check to ensure the reserved APOB DRAM space is the same size
as the MRC_CACHE region specified in the fmap.

Update sabrina APOB DRAM size to match the fmap.

TEST: Timeless builds identical. Test build with a larger MRC_CACHE than
APOB DRAM failed the assert as expected.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ia14f6ef94b9062df0612fe96098b1012085ccf9c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65878
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-01 20:44:09 +00:00
Karthikeyan Ramasubramanian 0b4f49c792 util/spd_tools/spd_gen/lp5: Remove maxSpeed for Sabrina
Firmware component that does memory training already limits the memory
controller to train at 5500 Mbps for all memory parts in Sabrina. Hence
removing this interim SPD change to limit the speed.

BUG=b:238074863
TEST=Build and boot to OS in Skyrim.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I2bc82c7407a97aac282708c3e0bd56ae99a8fc31
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66290
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-01 20:30:39 +00:00
Veerabhadrarao Badiganti 84753144d0 soc/qualcomm: Fill coreboot table with PCIe info
In order to pass PCIe base address to payloads, implement pcie_fill_lb()
to fill coreboot table with PCIe info.

BUG=b:182963902,b:216686574,b:181098581
TEST=Verified on Qualcomm sc7280 development board with NVMe endpoint
(Koixa NVMe, Model-KBG40ZPZ256G with FW AEGA0102). Confirmed NVMe is
getting detected in response to 'storage init' command in depthcharge
 CLI prompt.

Output logs:
 ->dpch: storage init
   Initializing NVMe controller 1e0f:0001
   Identified NVMe model KBG40ZPZ256G TOSHIBA MEMORY
   Added NVMe drive "NVMe Namespace 1" lbasize:512, count:0x1dcf32b0
   *  0: NVMe Namespace 1
    1 devices total

Also verified NVMe boot path that is depthcharge is able to load the
kernel image from NVMe storage.

Change-Id: I1ca2be55b98c8d1b86576072078cdda02ac55940
Signed-off-by: Veerabhadrarao Badiganti <quic_vbadigan@quicinc.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57614
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-01 19:00:20 +00:00
Veerabhadrarao Badiganti 7a0440afc6 libpayload: Enable PCIe driver for sc7280
Enable PCIe driver for herobrine board.

BUG=b:182963902,b:216686574,b:181098581
TEST=Verified on Qualcomm sc7280 development board with NVMe card
(Koixa NVMe, Model-KBG40ZPZ256G with FW AEGA0102). Confirmed NVMe is
getting detected in response to 'storage init' command in depthcharge
CLI prompt.

Output logs:
  ->dpch: storage init
    Initializing NVMe controller 1e0f:0001
    Identified NVMe model KBG40ZPZ256G TOSHIBA MEMORY
    Added NVMe drive "NVMe Namespace 1" lbasize:512, count:0x1dcf32b0
    *  0: NVMe Namespace 1
    1 devices total

Also verified NVMe boot path, that is depthcharge is able to load the
kernel image from NVMe storage.

Change-Id: Idb693ca219ba1e5dfc8aec34027085b53af49a2c
Signed-off-by: Veerabhadrarao Badiganti <quic_vbadigan@quicinc.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65661
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-01 18:04:54 +00:00
Prasad Malisetty 857d3781e2 libpayload/pci: Add pci_map_bus function for Qualcomm platform
Add 'pci_map_bus' function and PCIE_QCOM config for Qualcomm platform.

BUG=b:182963902,b:216686574,b:181098581
TEST=Verified on Qualcomm sc7280 development board with NVMe endpoint
(Koixa NVMe, Model-KBG40ZPZ256G with FW AEGA0102). Confirmed NVMe is
getting detected in response to 'storage init' command in depthcharge
CLI prompt.

Output logs:
 ->dpch: storage init
   Initializing NVMe controller 1e0f:0001
   Identified NVMe model KBG40ZPZ256G TOSHIBA MEMORY
   Added NVMe drive "NVMe Namespace 1" lbasize:512, count:0x1dcf32b0
  *  0: NVMe Namespace 1
    1 devices total

Also verified NVMe boot path that is depthcharge is able to load the
kernel image from NVMe storage.

Change-Id: I7d1217502cbd7d4d0cdd298919ae82435630d61c
Signed-off-by: Prasad Malisetty <quic_pmaliset@quicinc.com>
Signed-off-by: Veerabhadrarao Badiganti <quic_vbadigan@quicinc.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57615
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-01 18:04:54 +00:00
Veerabhadrarao Badiganti 16611f31eb mb/google/herobrine: Add PCIe domain support
Add PCIe domain support for herobrine by enabling it in the devicetree.

BUG=b:182963902,b:216686574,b:181098581
TEST=Verified on Qualcomm sc7280 development board with NVMe card
(Koixa NVMe, Model-KBG40ZPZ256G with FW AEGA0102). Confirmed NVMe is
getting detected in response to 'storage init' command in depthcharge
CLI prompt.

Output logs:
  ->dpch: storage init
    Initializing NVMe controller 1e0f:0001
    Identified NVMe model KBG40ZPZ256G TOSHIBA MEMORY
    Added NVMe drive "NVMe Namespace 1" lbasize:512, count:0x1dcf32b0
    *  0: NVMe Namespace 1
     1 devices total

Also verified NVMe boot path, that is depthcharge is able to load the
kernel image from NVMe storage.

Change-Id: Ied8fbbc8d20698ee081d93ba184b7d0291bb6a76
Signed-off-by: Veerabhadrarao Badiganti <quic_vbadigan@quicinc.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65137
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-01 18:04:54 +00:00
Prasad Malisetty 78298f5c8f soc/qualcomm/sc7280: Enable PCIe driver
Enable PCIe functionality on sc7280 and supply all the needed data
for PCIe generic platform driver.

BUG=b:182963902,b:216686574,b:181098581
TEST=Verified on Qualcomm sc7280 development board with NVMe card
(Koixa NVMe, Model-KBG40ZPZ256G with FW AEGA0102). Confirmed NVMe is
getting detected in response to 'storage init' command in depthcharge
CLI prompt.

Output logs:
 ->dpch: storage init
   Initializing NVMe controller 1e0f:0001
   Identified NVMe model KBG40ZPZ256G TOSHIBA MEMORY
   Added NVMe drive "NVMe Namespace 1" lbasize:512, count:0x1dcf32b0
   *  0: NVMe Namespace 1
   1 devices total

Also verified NVMe boot path, that is depthcharge is able to load the
kernel image from NVMe storage.

Change-Id: I1f79a0ae2dea594d6026d55a15978eeb92a8ff18
Signed-off-by: Prasad Malisetty <quic_pmaliset@quicinc.com>
Signed-off-by: Veerabhadrarao Badiganti <quic_vbadigan@quicinc.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66148
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-01 18:04:54 +00:00
Zhixing Ma a47a490635 mb/google/brya: Disable the Package C-state demotion
Disabling the Package C-state demotion feature for brya baseboard
as a work around to the S0ix issue and also this doesn't have any
impact on the power and performance measured and verified by the
PNP team.

This feature will be enabled after its functionality is verified with no
issues and also based on its impact on PNP.

BUG=none
BRANCH=firmware-brya-14505.B
TEST=Boot and verified that S0ix issue is resolved.

Signed-off-by: Zhixing Ma <zhixing.ma@intel.com>
Change-Id: Id3941c8870d41b25488c8ac5d38534fa94664d4a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-08-01 18:03:58 +00:00
Martin Roth 239b5df268 include: Add SPDX-License-Identifiers to files missing them
This adds SPDX-License-Identifiers to all of the files in src/include
that are missing them or have unrecognized identifiers.

Files that were written specifically for coreboot and don't have license
information are licensed GPL-2.0-only, which is the license for the
overall coreboot project.

Files that were sourced from Linux are similarly GPL-2.0-only.

The cpu/power files were committed with source that was licensed as
GPL-2.0-or-later, so presumably that's the license for that entire
commit.

The final file, vbe.h gives a pointer to the BSD-2-Clause license
at opensource.org.

Change-Id: I3f8fd7848ce11c1a0060e05903fb17a7583b4725
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-08-01 13:59:11 +00:00
Karthikeyan Ramasubramanian 6e3d40f2d1 Revert "UPSTREAM: soc/amd/sabrina,vc/amd/fsp/sabrina: Add UART support for Sabrina"
This reverts commit 78261e308de5361b2ff045091e8fb18cad2a5035.

Reason for revert: Now that PSP supports a soft fuse flag to toggle the
verstage serial logs, prevent PSP verstage from writing to the UART.

BUG=None
TEST=Build and boot to OS in Skyrim with PSP verstage. Ensure that PSP
verstage logs are not seen twice in the console.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I7ef2d585c320ea5903197939136dd2049a71af95
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-08-01 12:36:31 +00:00
Karthikeyan Ramasubramanian 63696fcf90 soc/amd/sabrina: Enable HW Modexp engine
HW Modexp engine is verified to be working fine. Any verification
failures during PSP verstage are because the firmware body is not read
correctly. This might be because of the incorrect SPI ROM mapping. Hence
enable the HW modexp engine for keyblock, preamble and firmware body
verification.

BUG=b:240175446
TEST=Build and boot to OS in Skyrim with PSP verstage using one of the
FW slots.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I8f6742630a7049354a24053fce28c477e53259e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-08-01 12:35:19 +00:00
Karthikeyan Ramasubramanian 51f914d4a4 util/amdfwtool: Support PSP whitelist file on recovery A/B layout
This is required to enable PSP verstage on SoCs with recovery A/B
layout.

BUG=b:217414563
TEST=Ensure that the concerned type 0x3a PSP entry is present in PSP L2
directory. Build and boot to OS in Skyrim with both PSP and x86
verstage.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I5fae2b5dbcc95a99af3df9f59bb8516280ec1281
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-08-01 12:34:46 +00:00
Matei Dibu 24b7307d9d drivers/elog: Use format string
clang shows the warning below:

src/drivers/elog/elog.c:171:13: error:
format string is not a string literal
(potentially insecure) [-Werror,-Wformat-security]
            elog_debug(msg);
                       ^~~

Found-by: clang (13.0.1)
Change-Id: I3f8949f9ce0c4ef4823530c61c503b0883bb5efc
Signed-off-by: Matei Dibu <matdibu@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66262
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-08-01 09:27:50 +00:00
Prasad Malisetty b66675d433 soc/qualcomm: Add PCIe support
Add PCIe platform driver for Qualcomm platforms.

Reference:
  - linux/drivers/pci/controller/dwc/pcie-qcom.c
  - Linux driver base commit: 82a823833f4e3769e82cdb4df1bc2234bc65b16c

BUG=b:182963902,b:216686574,b:181098581
TEST=Verified on Qualcomm sc7280 development board with NVMe card
(Koixa NVMe, Model-KBG40ZPZ256G with FW AEGA0102). Confirmed NVMe is
getting detected in response to 'storage init' command in depthcharge
CLI prompt.

Output logs:
 ->dpch: storage init
   Initializing NVMe controller 1e0f:0001
   Identified NVMe model KBG40ZPZ256G TOSHIBA MEMORY
   Added NVMe drive "NVMe Namespace 1" lbasize:512, count:0x1dcf32b0
   *  0: NVMe Namespace 1
    1 devices total

Also verified NVMe boot path, that is depthcharge is able to load the
kernel image from NVMe storage.

Change-Id: Iccf60aa56541f5230fa9c3f821d7709615c36631
Signed-off-by: Prasad Malisetty <quic_pmaliset@quicinc.com>
Signed-off-by: Veerabhadrarao Badiganti <quic_vbadigan@quicinc.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53902
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-31 18:19:19 +00:00
Sean Rhodes 37bf8c6dd5 payloads/tianocore: Update MrChromebox’ default branch to 202207
Update MrChromebox’ default branch from uefipayload_202107 to
uefipayload_202207.

This is based on upstream edk2, commit f26b70c (UefiPayloadPkg:
Add support for logging to CBMEM console).

Tested on:
* StarBook Mk V
* StarLite Mk III

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I16a012485e4b4957439e776914ffd016b4506a47
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66083
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-07-30 18:43:09 +00:00
Matt DeVillier 38a682fe92 payloads/tianocore: Use SMMSTORE when branch is MrChromeBox
SMMSTORE support in edk2 was not allowed in upstream edk2
as it was bootloader specific.

Shortly, it will be built from edk2-platforms and then,
it will be retired.

For now, the patches exist in the MrChromeBox fork (TIANOCORE_UEFIPAYLOAD), so enable
these by default when SMMSTORE_v2 is enabled.

Change-Id: I1861bf739c2e25f661b4f06a303348f0537dc8b3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65867
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-30 18:41:55 +00:00
Sean Rhodes c5055883eb payloads/tianocore: Allow passing custom build params to all versions
Allow passing custom build parameters to any version of edk2, not
just forks.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I4eed535415ba15ae73e22cada9153820538f5f6d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-07-30 18:40:58 +00:00
Bora Guvendik 85c9a7320f vendorcode/intel/fsp: Fix wrong license
Fix the license in header file.

BUG=none
BRANCH=firmware-brya-14505.B
TEST=none

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I025f7c571d09e4cc63a659279e63d17c098c01cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66253
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2022-07-30 18:40:10 +00:00
Bill XIE 4e43abf9c1 mb/hp/z220_series: Improve the port for z220_sff_workstation
- Move configs for PCIe ports not present on z220_sff_workstation
  from the devicetree.cb of base board to the overridetree.cb of
  z220_cmt_workstation.

- Add a note for ME/AMT Flash Override jumper, for it is hard to
  flash from OEM firmware either internally or externally without
  closing this jumper.

- Add a side note for similar HP Compaq Elite 8300 SFF.

Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I35d8b97f52a83910a61c12b1f7367ee7a19a9ad7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65703
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-30 18:39:31 +00:00
Raihow Shi a955efc190 mb/google/brask/variants/moli: Add DPTF setting in Moli
DPTF Policy and temperature sensor values from thermal team.

BUG=b:236294162
TEST=emerge-brask coreboot

Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: Iebcfb74c4bc719e6d8d8d9317435becd912eaf85
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-07-30 18:30:06 +00:00
Jakub Czapiga 190afda543 security/vboot: Simplify image signing
futility now supports image truncation and signing of whole images with
a single command invocation. Use it for vboot-enabled coreboot images.

TEST=Build and run coreboot on google/volteer

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I49eb7e977b635ccb9f6c1b76e53c36e82be1d795
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-07-30 18:29:25 +00:00
Elyes Haouas ae157d38e3 crossgcc: Upgrade LLVM from 13.0.1 to 14.0.6
Test build for QEMU x86 i440fx/piix4.

Change-Id: I97d059947f7049b2491a98985795a4655891c3b3
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-07-30 18:27:30 +00:00
Felix Singer a44620dea9 arch/x86/acpi: Replace Store() with ASL 2.0 syntax
Change-Id: I30bbd0288475fbefec55ce294e7963df1de6aa6a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2022-07-30 00:11:58 +00:00
Felix Singer 311981ef48 arch/x86/acpi: Replace And() with ASL 2.0 syntax
Change-Id: I21b954ce62259bb77d88775c3086cfac17dd90c7
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2022-07-30 00:11:36 +00:00
Felix Singer b4a7f74436 arch/x86/acpi: Replace LNotEqual(a,b) with ASL 2.0 syntax
Replace `LNotEqual(a, b)` with `a != b`.

Change-Id: If0e9fcea680d487c28a965e944b3333bb5a07026
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60696
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-30 00:11:08 +00:00
Felix Singer 7ee6b5a3a5 arch/x86/acpi: Replace LLess(a,b) with ASL 2.0 syntax
Replace `LLess(a, b)` with `a < b`.

Change-Id: Ief1d069ae0fb19a2179f08c2e9cf416367661e69
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60674
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-30 00:10:27 +00:00
Felix Singer 50002b7fac arch/x86/acpi: Replace Add(a,b,c) with ASL 2.0 syntax
Replace `Add (a, b, c)` with `c = a + b`.

Change-Id: If848d391e5ec33ebfb08515414739dbdd5011e08
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2022-07-29 23:58:51 +00:00
Subrata Banik 8072b420a6 mb/google/rex: Perform display configuration override
This patch enables display port configuration as per the Rex
schematics.

TEST=Able to dump FSP UPD to ensure the override is successful.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I9e81d037416e46e52cb72344425d6d8725dae192
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-07-29 19:58:01 +00:00
Stanley Wu 828243ebca mb/google/nissa/var/pujjo: Enable OZ711LV2LN SD card controller
Pujjoflex support OZ711LV2LN SD card controller,
Select the Bayhub LV2 driver for OZ711LV2LN SD card.

BUG=b:215487382
TEST=Build FW and checking SD card work as expected in OS.

Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I6759fde1eaf24599a1fdb364d6e78f4e4e12f311
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-07-29 15:06:46 +00:00