Commit Graph

41194 Commits

Author SHA1 Message Date
Elyes HAOUAS 9148cd145f soc/intel/common/block/itss/itss.c: Remove repeated word
Change-Id: Icc4954bcc1540f1935b0e34107febb4a1e947a36
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2021-01-18 07:35:33 +00:00
Elyes HAOUAS 59ab203f1c soc/intel/skylake/chip.h: Remove repeated word
Change-Id: Id5bf9255e9a16a4f311e3b15eb77ad6e4bb13f66
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2021-01-18 07:35:14 +00:00
Elyes HAOUAS 1a8d0e5886 soc/nvidia/tegra124/spi.c: Remove repeated word
Change-Id: I0018ea16f304a0d2cedfbd55525ecabbf2d89aa1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2021-01-18 07:35:02 +00:00
Elyes HAOUAS b9d95c5f64 soc/nvidia/tegra210/spi.c: Remove repeated word
Change-Id: Iea0c973b2bd493eb69ef76289b5b4fc66ac622f6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2021-01-18 07:34:48 +00:00
Elyes HAOUAS a833698280 ec/google/chromeec/ec.h: Remove repeated word
Change-Id: I7f567f2b4c582e4b2bb102ef0e0f68c5bf6cfb9e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2021-01-18 07:34:34 +00:00
Elyes HAOUAS 4041772535 drivers/intel/gma/intel_bios.h: Remove repeated word
Change-Id: I5866a5e3240e49119e29f728202b33dd82ceaf77
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2021-01-18 07:34:12 +00:00
Elyes HAOUAS cb0584ecdb device/xhci.c: Remove repeated word
Change-Id: Ia1648bd7ba4858268ca5f1a5c7b42b7de717d3d6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49513
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2021-01-18 07:33:25 +00:00
Elyes HAOUAS 0ce74161ad device/pci_device.c: Remove repeated word
Change-Id: Ia6936675684e3eaf2a57e2d28e465b1f0768249b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49512
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2021-01-18 07:33:13 +00:00
Elyes HAOUAS cc2c5c9ec7 cpu/x86/smm/smm_module_loaderv2.c: Remove repeated word
Change-Id: I712fca09b1618017412a3d91f81627ec876f2894
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49511
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2021-01-18 07:31:46 +00:00
Elyes HAOUAS 07f11db69c cpu/x86/mtrr/earlymtrr.c: Remove repeated word
Change-Id: I7e7570ff6a4319a0cf583ae5b76e7c24f0241509
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2021-01-18 07:31:23 +00:00
Elyes HAOUAS 398df49d3f cpu/intel/smm/gen1/smmrelocate.c: Remove repeated word
Change-Id: I478f8ab0cf0a4004b4d7294efb330dc800253e4a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49509
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2021-01-18 07:31:06 +00:00
Elyes HAOUAS 27af8a7e5d nb/intel/gm45/gm45.h: Remove duplicated include
Change-Id: Iabd6c69cd4c28f0015d4cf1f95d5ae0b6dc8b47e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2021-01-18 07:30:48 +00:00
Elyes HAOUAS 6a2ca474a4 soc/amd/common/block/smi/smi_util.c: Remove repeated word
Change-Id: Ifeac919ac7214c1baf877a36fd3d57636fc83563
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-18 07:29:48 +00:00
Eric Lai f8248f38a1 soc/intel/alderlake: Update PCH and CPU PCIe RP table
According ADL EDS to update the PCH and CPU PCIe RP table.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Idcc21d8028f51a221d639440db4cf5a4e095c632
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-01-18 07:28:51 +00:00
Eric Lai de2ab41fc4 soc/intel/common: Move L1_substates_control to pcie_rp.h
L1_substates_control is common define. Move out of soc level.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I54574b606985e82d00beb1a61cce3097580366a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-01-18 07:28:32 +00:00
Matt DeVillier cb18524b4a mb/purism/librem_cnl: Update HDA verbs for Librem Mini
Disable all NIDs other than those for the front combo jack.
Adjust attributes to match jack physical location, appearance, etc.
Correct group number for verbs for HDMI output.

Test: run hdajackretask, verify NID characteristics correct for each
verb. Verify headphone detection and output functional.

Change-Id: If9fca5d9795d56bd38c8ea47f8de985c14ac8fab
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49464
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-18 07:28:01 +00:00
Furquan Shaikh ea3e6b06cc soc/intel/common/pcie: Allow pcie_rp_group table to be non-contiguous
In case of CPU PCIe RPs, the RP numbers might not be contiguous for
all the functions in a slot.

Example: In ADL, RP1 is 00:06.0, RP2 is 00:01.0 and RP3 is 00:06.2 as
per the FSP expectations.

Hence, this change updates the defintion of `struct pcie_rp_group` to
include a `start` member which indicates the starting PCI function
number within the group. All common functions for PCIe RP are
accordingly updated to take the `start` member into account.

Thus, in the above example, ADL can provide a cpu_rp_table as follows:
{
  { .slot = PCIE_SLOT_6, .start = 0, .count = 1 },
  { .slot = PCIE_SLOT_1, .start = 0, .count = 1 },
  { .slot = PCIE_SLOT_6, .start = 2, .count = 1 },
}

Since start defaults to 0 when uninitialized, current PCH RP group
tables don't need to be updated.

Change-Id: Idf80a0f29e7c315105f76a7460c8e1e8f9a10d25
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49370
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-18 07:27:43 +00:00
Jeremy Soller 7cc513557d ec/system76/ec: Add fan and temperature reporting
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Change-Id: Iee19e7518ffaacd9a847cb6d28c839d4ec464514
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-18 07:27:26 +00:00
Jakub Czapiga a2b21c23d5 tests: Add lib/imd_cbmem-test test case
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Ie893b5e8fc91c230ff96a14146085de16d78b1c1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-01-18 07:27:16 +00:00
Kyösti Mälkki e1aa9833c1 lib/ramtest: Fix ram_check() declarations
For a long time, second parameter 'stop' has been
ignored. The tested range is within 1 MiB above 'start'.

Change-Id: Icbf94cd6a651fbf0cd9aab97eb11f9b03f0c3c31
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48561
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-18 07:26:32 +00:00
Seunghwan Kim 4c4f916172 mb/google/dedede/var/sasuke: Disable PCIE RP8 and CLKSRC3
This change disables unused PCIE RP8 and CLKSRC3.
Without this change sasuke cannot enter into s0ix properly.

BUG=b:176862270
TEST=Built and verified entering s0ix

Change-Id: I0828813ed7924669cb0ff97be2565579762c810f
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49300
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Jamie Chen <jamie.chen@intel.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-18 07:25:48 +00:00
Seunghwan Kim 88418a74cf mb/google/dedede/var/sasuke: Add USB2 PHY parameters
This change adds fine-tuned USB2 PHY parameters for sasuke.

BUG=176060155
TEST=Built and verified USB2 eye diagram test result

Change-Id: Id374ed238d92077ca28c1162fd9f070029ee71bd
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49321
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-18 07:25:35 +00:00
Wisley Chen 9f2d082005 mb/google/volteer/var/elemi: Configure USB2 ports
Configure the USB2 port 3/4/9
1. USB2 port3 assign to WWAN, and elemi have no WWAN.
2. USB2 port4/port9 connect to Type-C C1/C0

BUG=b:177483059
TEST=emerge-volteer coreboot

Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Change-Id: I9affc69cc325b5eb0219b50bfe46f66eb0bb2016
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49473
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-18 07:25:28 +00:00
Stanley Wu a7586772d0 drivers/i2c/sx9324: Add IrqCfg1 register
Add IrqCfg1 register for proximity IRQ function and polarity setting.

BUG=b:175932166
BRANCH=dedede
TEST=Build passed.

Change-Id: I3cee84a5658fecf55d2d8b8621879588ffe0158d
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49220
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-18 07:25:02 +00:00
Kyösti Mälkki 0fcbd3a125 ChromeOS: Refactor SMBIOS type0 bios_version()
Pointer to an empty string (filled with spaces) is
stored inside GNVS. Rearrange things to avoid having
<chromeos/gnvs.h> in SMBIOS code.

Change-Id: I9405afbea29b896488b4cdd6dd32c4db686fe48c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49281
Reviewed-by: Lance Zhao
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-18 07:23:53 +00:00
Kyösti Mälkki 661ad4666c ACPI: Select ACPI_SOC_NVS only where suitable
Having some symmetry with <soc/nvs.h> now allows to reduce
the amount of gluelogic to determine the size and cbmc field
of struct global_nvs.

Since GNVS creation is now controlled by ACPI_SOC_NVS,
drivers/amd/agesa/nvs.c becomes obsolete and soc/amd/cezanne
cannot have this selected until <soc/nvs.h> exists.

Change-Id: Ia9ec853ff7f5e7908f7e8fc179ac27d0da08e19d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lance Zhao
2021-01-18 07:21:34 +00:00
Angel Pons 286a0572e7 util/lint/spelling.txt: Disable `pres`
It would seem that `pres` is an abbreviation for `presence`. Personally,
over the last ~2.5 years, I have seen checkpatch complaints about `pres`
on several occasions, and all of them were abbreviations for `presence`.

Given the high false positive rate for this entry, comment it out.

Change-Id: I72f1811fb1f766e7de7c4957fd9ba844c0728029
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49463
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-17 16:49:00 +00:00
Michael Niewöhner cf2f7005f6 mb/google/volteer: do UART pad config at board-level
UART pad configuration should not be done in common code, because that
may cause short circuits, when the user sets a wrong UART index. Thus,
add the corresponding pads to the early UART gpio table for the board as
a first step. Common UART pad config code then gets dropped in CB:48829.

Also switch to `bootblock_mainboard_early_init` to configure the pads in
early bootblock before console initialization, to make the console work
as early as possible. The board does not do any other gpio configuration
in bootblock, so this should not influence behaviour in a negative way
(e.g. breaking overrides).

Change-Id: I5e07584d7857052c7a9388331a475f5a073af038
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49425
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-16 19:50:16 +00:00
Michael Niewöhner e31bfef2b0 mb/system76/lemp9: do early pad configuration in early bootstage
Do early pad configuration in early bootblock before console init, to
make the console work as early as possible. The board does not do any
other gpio configuration in bootblock, so this should not influence
behaviour in a negative way (e.g. breaking overrides).

Change-Id: Ie122a441145383b820d96e32ce1581dfc27fa57b
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49418
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
2021-01-16 08:23:51 +00:00
Patrick Georgi 2cc5bcbf7f build system: Always add coreboot.pre dependency to intermediates
They all operate on that file, so just add it globally.

Change-Id: I953975a4078d0f4a5ec0b6248f0dcedada69afb2
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-01-15 23:54:09 +00:00
Patrick Georgi 0b7d3a154e build system: Remove flock calls from intermediate processing
Now that intermediate coreboot.pre manipulation is serialized within
the build system, remove the flock calls.

Change-Id: I8a767918aec5fcb7127ebb19ac46e58bed7967fb
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-01-15 23:54:07 +00:00
Raul E Rangel 2a1638a9ce mb/amd/mandolin: Clean up IRQ numbers
We no longer need the IO-APIC assignments since we use the GNB IO-APIC.
We were also missing the E-H IRQ mapping. I also renumbered them since
IRQ 8 is used by the rtc.

TEST=none
BRANCH=zork

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia956ae457669aeda6fa49e127373aad3807f7b9b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-15 23:04:59 +00:00
Kevin Chiu 3379879c6c mb/google/zork: update USB 2.0 controller Lane Parameter for dirinboz
Enhance USB 2.0 M/B C0, DB C1 A1 port:
HS DC Voltage Level(TXVREFTUNE0): 0xe
COMPDISTUNE(COMPDISTUNE0): 0x7

BUG=b:165209698
BRANCH=zork
TEST=emerge-zork coreboot

Change-Id: I371e4295c2ee161096f0a277c0c649bf217269b2
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-15 22:38:14 +00:00
Kane Chen bc148df898 mb/google/zork/var/shuboz: update STAPM add telemetry setting
1. Modify STAPM time constant 2500 to 1400.

2. Add telemetry setting:
VDD Slope : 30518
VDD Offset: 435
SOC Slope : 22965
SOC Offset: 165

BUG=b:177399751
BRANCH=master
TEST=emerge-zork coreboot chromeos-bootimage

Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I251029389c10ee0f17f368b1c00ac666d372fc3c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-01-15 22:11:57 +00:00
Kevin Chiu 25e9dc6be9 mb/google/zork: update DRAM table for berknip
Add Hynix DDR4 DRAM H5ANAG6NCJR-XNC, index was generated by gen_part_id

BUG=b:176313722
BRANCH=zork
TEST=emerge-zork coreboot

Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: Ia1947fa158a1113c4a0b1a0d55f657ddaac43382
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-01-15 21:57:51 +00:00
Shaoming Chen 769320d1c4 mb/google/kukui: Add new ddr architecture support for kukui
Two configuration files are added:
1. H9HCNNNFAMMLXR-NEE-8GB: new byte mode
2. MT53E1G32D2NP-046-4GB: new single rank mode

Also initialize the rank number field 'rank_num' for all configs.

BUG=b:165768895
BRANCH=kukui
TEST=DDR boot up correctly on Kukui

Signed-off-by: Shaoming Chen <shaoming.chen@mediatek.corp-partner.google.com>
Change-Id: I1786c1e251e8d6e110cbdce79feeb386db220404
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49108
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-15 11:29:34 +00:00
Shaoming Chen 5ff588dbc1 soc/mediatek/mt8183: Support byte mode and single rank DDR
1. Add emi setting to support byte mode and single rank ddr sample
2. Modify initial setting for DDR with different architecture

BUG=b:165768895
BRANCH=kukui
TEST=DDR boot up correctly on Kukui

Signed-off-by: Shaoming Chen <shaoming.chen@mediatek.corp-partner.google.com>
Change-Id: Id2845b2b60e2c447486ee25259dc6a05a0bb619b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-15 11:29:17 +00:00
Frank Wu f296273692 mb/google/zork/var/vilboz: Add WiFi SAR for Vilboz
The fw_config field SPI_SPEED is not used for zork devices.
To define SAR config, use the fw_config bit[23..26].
Then vilboz can loaded different WiFi SAR table for different SKUs.

BUG=b:176858126, b:176751675, b:176538384
BRANCH=zork
TEST=emerge-zork coreboot chromeos-bootimage, then verify that tables are
in CBFS and loaded by iwlwifi driver.

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I5ba98799e697010997b515ee88420d0ac14ca7ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-01-15 11:28:31 +00:00
Jason Glenesk 276e865e7f soc/amd/picasso: Generate ACPI CRAT objects in cb
Add code to collect all required information and generate ACPI CRAT
table entries. Publish tables generated from cb, rather than use the
tables created by FSP binary.

BUG=b:155307433
TEST=Boot trembyle and compare coreboot generated tables with tables
that FSP published previously.
BRANCH=Zork

Change-Id: If64fd624597b2ced014ba7f0332a6a48143c0e8c
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-15 11:27:23 +00:00
David Wu fd104e1c5d mb/google/volteer/var/voema: Configure USB2 ports for Type C
Based on voema schematics, two USB2 ports 3 and 5 are assigned to type C
connectors on Voema board.

BUG=b:177483061 b:172535001
TEST=Build and boot Voema.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I12cef85595e511801ab9c563ae4aa26e25875679
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-15 11:26:41 +00:00
Michael Niewöhner ec1c0f5337 mb/siemens/mc_apl1: do LPC/eSPI pad configuration at board-level
Do LPC/eSPI pad configuration at board-level to match other platforms.

Early gpio configuration was done in romstage, while LPC pads were
configured in bootblock. Instead of adding another dedicated gpio table
for bootblock, move early gpio configuration completely to bootblock on
these boards. This won't hurt, since there is no code touching the pads
in between.

The soc code gets dropped in CB:49410.

Change-Id: I2a614afb305036b0581eac8ed6a723a3f80747b3
Tested-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-01-15 11:26:20 +00:00
Angel Pons 7519ca42b5 nb/intel/sandybridge: Clarify command timing calculation
Command timing is the absolute value of the most negative `pi_coding`
value across all ranks, or zero if there are no negative values. Use the
MAX() macro to ease proving that `cmd_delay` can never be negative, and
then drop the always-false underflow check.

The variable type for `cmd_delay` still needs to be signed because of
the comparisons with `pi_coding`, which is a signed value. Using an
unsigned type would result in undefined and also undesired behavior.

Change-Id: I714d3cf57d0f62376a1107af63bcd761f952bc3a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-15 11:24:41 +00:00
Angel Pons 0a7d99c089 nb/intel/sandybridge: Fix handling of clock timing
Clock is a differential signal and propagates faster than command and
control, therefore its timing needs to be offset with `pi_code_offset`.
It is also a periodic signal, so it can safely wrap around.

To avoid potential undefined behavior, make `clk_delay` signed. It makes
no difference with valid values, because the initial value can be proven
to never be negative and `pi_code_offset` is always positive. With this
change, it is possible to add an underflow check, for additional sanity.

Change-Id: I375adf84142079f341b060fba5e79ce4dcb002be
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-15 11:24:32 +00:00
Angel Pons 89200d2786 nb/intel/sandybridge: Remove wrong and nonsense condition
Commit 7584e550cc (nb/intel/sandybridge: Clean up program_timings)
introduced this condition along with a comment that says the opposite.
Command and clock timings always need to be computed, so drop both the
nonsensical condition and the equally-worthless corresponding comment.

Change-Id: I509f0f6304bfb3e033c0c3ecd1dd5c9645e004b2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-15 11:24:15 +00:00
Angel Pons bda1c552e9 cpu/intel/haswell/acpi.c: Use C-state enum definitions
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 does not change.

Change-Id: I0ca98cbe45e10d233607f68923f08752fdda9698
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46923
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-15 11:23:41 +00:00
Angel Pons ba5761a947 cpu/intel/haswell: Factor out ACPI C-state values
There's no need to have them in the devicetree. ACPI generation can now
be simplified even further, and is done in subsequent commits.

Change-Id: I3a788423aee9be279797a1f7c60ab892a0af37e7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46908
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-15 11:23:23 +00:00
Angel Pons 6d2d19de74 mb/intel/baskingridge: Replace invalid C-state values
Basking Ridge is not ULT, thus does not support C-states deeper than C7.
Replace them with the values used by all other Haswell non-ULT boards to
allow subsequent commits to cleanly factor them out of the devicetree.

Change-Id: Ife34f7828f9ef19c8fccb3ac7b60146960112a81
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46907
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-15 11:22:58 +00:00
Karthikeyan Ramasubramanian 8832de380d mb/google/dedede/var/boten: Update LTE GPIO configuration
LTE module is not expected to be powered off during warm reset. Hence
configure the LTE_PWR_OFF_ODL (GPP_A10) gpio pad reset configuration to
PWROK and set the TX state to 1.

BUG=b:163100335
BRANCH=dedede
TEST=Verified through the waveforms that power sequence is meeting the LTE module requirements.

Change-Id: I8676da6186559288aabe078b6158fc01075c7b41
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-01-15 11:22:37 +00:00
Angel Pons 06e6983002 soc/intel/braswell: Prevent NULL pointer dereference
Exit early if the chipset power state info isn't in CBMEM. Return -1 in
order to ensure the one caller of this function exits early as well.

Found-by: Coverity CID 1442304
Change-Id: Ifa42ba3024d3144de486d90ed7752820482549bf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49359
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Lance Zhao
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-15 11:22:28 +00:00
Tim Chen 77a7520385 mb/google/dedede/var/metaknight: Add LTE power on/off sequence
LTE module used in metaknight has a specific power on/off sequence.
GPIOs related to power sequence are:
* GPP_A10 - LTE_PWR_OFF_R_ODL
* GPP_H17 - LTE_RESET_R_ODL
1. Power on: GPP_A10 -> 20ms -> GPP_H17
2. Power off: GPP_H17 -> 10ms -> GPP_A10
3. Warm reset: GPP_A10 keeps high, GPP_H17 goes low at least 2ms
Configure the GPIOs based on these requirements.

BUG=b:173671094
TEST=Build and boot Metaknight to OS. Ensure that the LTE module power
sequence requirements are met.

Change-Id: Ibff16129dfe2f1de2b1519049244aba4b3123e52
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-01-15 11:22:13 +00:00