Commit Graph

15818 Commits

Author SHA1 Message Date
Aaron Durbin f969d4a5ef google/chell: fix hynix spd data
Spreadsheet as built indicates:

Samsung 4*8Gb - K4E8E304EE-EGCF - 0b0000
Samsung 4*16Gb - K4E6E304EE-EGCF - 0b0001
Hynix 4*8Gb H9CCNNN8GTMLAR-NUD - 0b0010
Hynix 4*16Gb H9CCNNNBJTMLAR-NUD - 0b0011

Adjust the Hynix spds to match accordingly.

BUG=chrome-os-partner:46573
TEST=None
BRANCH=None

Change-Id: I2ae0335af3557c787cced899bfb80db045f99cd0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 35ed2b0a5af53203480c726b875875d7c2cfd855
Original-Change-Id: I3cb38b28c454fbd60b776954c377b4559c6efebd
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.orG>
Original-Reviewed-on: https://chromium-review.googlesource.com/306580
Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/12159
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-27 15:19:50 +01:00
Lee Leahy d5855ec532 FSP1_1: Always use common code
Always use the common FSP code.  Remove the FSP_RAM_INIT, FSP_ROMSTAGE,
FSP_STACK and FSP_STAGE_CACHE Kconfig values.

BRANCH=none
BUG=None
TEST=Build and run on Kunimitsu

Change-Id: Ib3d015cb2dc257e46c2340cc7bc09cf0ffb0492c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5197b1354d138759dfaa428c665de6cbfb8e8911
Original-Change-Id: I3e3c1c9e6f73009a099c1ec3688dbd8c326fc766
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/306142
Original-Commit-Ready: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12158
Tested-by: build bot (Jenkins)
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2015-10-27 15:19:23 +01:00
Lee Leahy 66208bd3d5 FSP 1.1: Replace soc_ prefix with fsp_
Rename soc_display_upd_value to fsp_display_upd_value since the routine
was moved from src/soc/intel/common into src/drivers/intel/fsp1_1.

BRANCH=none
BUG=None
TEST=Build and run on Kunimitsu

Change-Id: Ifadf9dcdf8c81f8de961e074226c349fb9634792
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 95238782702999a178989467694ac1f15c079615
Original-Change-Id: Ibd26ea41bd5c7a54ecd3c237f7fb7bad6dbf7d8a
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/306351
Original-Commit-Ready: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12157
Tested-by: build bot (Jenkins)
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2015-10-27 15:19:12 +01:00
Lee Leahy 94b856ef9a FSP 1.1: Move common FSP code
Move the FSP common code from the src/soc/intel/common directory into
the src/drivers/intel/fsp1_1 directory.  Rename the Kconfig values
associated with this common code.

BRANCH=none
BUG=None
TEST=Build and run on kunimitsu

Change-Id: If1ca613b5010424c797e047c2258760ac3724a5a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e8228cb2a12df1cc06646071fafe10e50bf01440
Original-Change-Id: I4ea84ea4e3e96ae0cfdbbaeb1316caee83359293
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/306350
Original-Commit-Ready: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12156
Tested-by: build bot (Jenkins)
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2015-10-27 15:19:03 +01:00
pchandri 597de2849d ec/chrome: Disable LPC Continuous Serial IRQ Select
This patch removes the auto select of SERIRQ_CONTINUOUS_MODE
as part of the EC_GOOGLE_CHROMEEC_LPC.

BUG=chrome-os-partner:44993
BRANCH=none
TEST=Builds and Boots on fab3 kunimitsu.

Change-Id: I4aed2c53bfdcbb8f7cd28f9a23fad86c9cd5086e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 90a1e0785857a4da556e7664a8b83e9c8a0a78a7
Original-Change-Id: Ia411966bab557c269afa1d7e88ab2550eb35447e
Original-Signed-off-by: pchandri <preetham.chandrian@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/305580
Original-Commit-Ready: Preetham Chandrian <preetham.chandrian@intel.com>
Original-Tested-by: Preetham Chandrian <preetham.chandrian@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Preetham Chandrian <preetham.chandrian@intel.com>
Reviewed-on: http://review.coreboot.org/12155
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-27 15:18:50 +01:00
Aaron Durbin aeb2e15428 boot_device: add call to boot_device_init()
In the program loading paths using vboot it's possible that
the boot media has not been initiazed for that stage. Therefore,
provide this call such that it's guaranteed to be called at least
once.

BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados.

Change-Id: I3a0ef4d9eebbf5f15780316cc76b469e8ac3f358
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6ee0c5bb36d17fd80ba34762e7547359fd8971ce
Original-Change-Id: If8dfeedbe1243ec482764e05c8d3f333c18aedd2
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/305540
Original-Tested-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/12154
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-27 15:18:33 +01:00
pchandri 1d77c721d3 intel/kunimitsu FAB3: Configure LPC to Quiet Mode.
This patch configures the LPC to quiet mode and sets
enables CLKRUN so that LPC can be power gated.

BUG=chrome-os-partner:44993
BRANCH=none
TEST=Builds and Boots on fab3 kunimitsu.

Change-Id: I46ff21f75b70f54da3f12dcc56d61f84b436cd7d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: edd37df385bc013b62f26435267291acc0a9b9a4
Original-Change-Id: Ide0f9e91127aebb8ac027ee0a598608b50aa4278
Original-Signed-off-by: pchandri <preetham.chandrian@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/305396
Original-Commit-Ready: Preetham Chandrian <preetham.chandrian@intel.com>
Original-Tested-by: Preetham Chandrian <preetham.chandrian@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Preetham Chandrian <preetham.chandrian@intel.com>
Reviewed-on: http://review.coreboot.org/12153
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-27 15:18:09 +01:00
Duncan Laurie f16bb7cce3 google/chell: Add new mainboard for chell
This is based on glados with minor changes:
- updated GPIOs based on schematic
- add _PRW for trackpad wake now that it is on a new GPIO
- add SPD for new memory config
- disable ALS

BUG=chrome-os-partner:46289
BRANCH=none
TEST=emerge-chell coreboot

Change-Id: Id5746bf2b5b26000fcc3f029b901bfe29b788dac
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9c5ebe98cf599ba80aac5e9ef238b7996789a819
Original-Change-Id: I75efda64a50b0e6e4a5c9008ce05d76c1e605b0c
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/304927
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12151
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-27 15:17:17 +01:00
Duncan Laurie 09170f16a4 google/chell: copy glados to chell
Only change is renaming all occurrences of glados to chell, keeping
capitalization.

Change-Id: I8b1a3efd03d415f27c8872827f8687babbc539f7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/12150
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-27 15:16:46 +01:00
Duncan Laurie 4a6ac1e0e7 google/glados: Add USB phy settings and update enabled options
- Add placeholder USB phy settings, needs tuning still
- Change UART2 to be skipped during FSP init
- Update headphone codec irq to be level triggered as
that is how the kernel is configuring it

BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-glados coreboot

Change-Id: I9a15a27dab49d4e19f8ef0574ee2e61ae90c99fc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6e7a0032ba23d6762342639c2c7cb877c1f90452
Original-Change-Id: Ie1439f21116022b0644d06853df9490e4651a9ae
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/304926
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12149
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-27 15:16:38 +01:00
Duncan Laurie a9ba459550 google/glados: Enable TPM PIRQ
Enable the config option for TPM to use PIRQ instead of SERIRQ
and enable the MAINBOARD_HAS_LPC_TPM option.

BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-glados coreboot

Change-Id: I990901117a2c478045c403f1039d6eedfc278255
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 44ecaaae1eb482ef5d4cf1e051de4571cc4441be
Original-Change-Id: I115d468c72c3fd015abdddffdd1626368bfedb6e
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/304925
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12148
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-27 15:16:30 +01:00
Duncan Laurie 8b11b2c4df tpm: acpi: Add support for TPM PIRQ
With SPI TPMs there is no SERIRQ for interrupts, instead it is
a PIRQ based interrupt.  The TCG PC Client Platform TPM Profile
Specification says it must be active low and shared.

This can be enabled with the CONFIG_TPM_PIRQ option that will
specify the interrupt vector to report for the TPM.

BUG=chrome-os-partner:40635
BRANCH=none
TEST=verify TPM interrupt functionality in /proc/interrupts on glados

Change-Id: Iad3ced213d1fc5380c559f50c086206dc9f22534
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: abdd0b8ecdf51ff32ed8bfee0823bbc30d5d3d49
Original-Change-Id: If7d22dfcfcab95dbd4c9edbd8674fc8d948a62d2
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/304133
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12147
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-27 15:16:22 +01:00
Subrata Banik d0def39413 intel/skylake: IRQ programming through UPD
Implemented Device IRQ porgramming, PxRC to IRQ mapping,
GPIO IRQ routing, SCI IRQ select through UPD

BUG=NONE
BRANCH=NONE
CQ-DEPEND=CL:*232948
TEST= build and booted sklrvp,kunimitsu with this changes.

Change-Id: Ic98074491fe5251a48ed55b6fb7ef31809c3abf3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 534bd65e5df8654d745c8efe491a332336c9cdc3
Original-Change-Id: I4ea6f3cdb15d371c6023bfd046f3475290f5aa26
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/291403
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12146
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-27 15:16:02 +01:00
Rizwan Qureshi 9cd8e5aebf intel/kunimitsu: USB Phy settings and Skip UART2 init in FSP
FSP 1.7.0 provides UPD to configure USB phy settings
update the same for kunimitsu.

FSP 1.7.0 also provides UPD to indicate FSP not to reinitialise
UART2 controller during MemoryInit.

BRANCH=none
BUG=chrome-os-partner:45684,chrome-os-partner:41374,chrome-os-partner:42284
TEST=build for Kunimitsu, boot on FAB3, Also checked for Boot from USB,
	Boot from eMMC, USB Audio, Onboard Audio, Touch, Wifi, S3 entry/resume

CQ-DEPEND=CL:303661

Change-Id: Ie0a545c954f472cc822b63786d40399ec93d5166
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 90296e04942c70d972c225fc75dfab6de44d10ed
Original-Change-Id: If79e81ef3323e782e96db307d89a01c14174b435
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Signed-off-by: Rishavnath Satapathy <rishavnath.satapathy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/304032
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12145
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-27 15:15:50 +01:00
Rizwan Qureshi 952cb03b9e intel/skylake: FSP 1.7.0 MemoryInit/SiliconInit params update
In FSP 1.7.0 SataMode and SataEnable have been moved from
MemoryInit to SiliconInit. Also, GpioTablePtr has been removed.

USB phy settings added to SiliconInit, Enable the configs for USB
equalization settings in coreboot.

Addition of serialIO UPD to indicate FSP not to reinitialise
UART2 controller during MemoryInit.

BRANCH=none BUG=chrome-os-partner:45684, chrome-os-partner:42284, chrome-os-partner:41374
TEST=build for Kunimitsu, boot on FAB3, Also checked for Boot from USB, Boot from eMMC,
	USB Audio, Onboard Audio, Touch, Wifi, S3 entry/resume

CQ-DEPEND=CL:*232947, CL:*232946, CL:*232948, CL:*232949

Change-Id: I2e8e6e32fc7074774ddcf1fb4c270bb56372b7df
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 623c5a52f3afedaf2c0bfe7361cfd627d093cb73
Original-Change-Id: I8b3be2c49893c564fe2197aa32bde6323bf425e9
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Signed-off-by: Rishavnath Satapathy <rishavnath.satapathy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/303661
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12144
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-27 15:15:39 +01:00
pchandri e57e72681f intel/kunimitsu Fab3: Strengthening Rcomp target CTRL value
This patch strengthens the Rcomp Target CTRL by 10% for
8GB memory part K4E6E304EE-EGCF as with the current values
the MRC training is failing due to more load on CS#

BRANCH=None
BUG=chrome-os-partner:44647
TEST=BUilds and boots on Kunimitsu.

Change-Id: I478002bbebabaac418356d4b5b4755bb56009268
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b208659e690d8cb5b8dcaf30eed53c01b9f77f6d
Original-Change-Id: Ia0a0c1358649af77a3a0d301cb791f26f1e039bf
Original-Signed-off-by: pchandri <preetham.chandrian@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/304103
Original-Commit-Ready: Preetham Chandrian <preetham.chandrian@intel.com>
Original-Tested-by: Preetham Chandrian <preetham.chandrian@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Preetham Chandrian <preetham.chandrian@intel.com>
Reviewed-on: http://review.coreboot.org/12143
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-27 15:15:30 +01:00
robbie zhang b45dde0b78 intel/skylake: Add support for Gfx PEIM (AKA GOP)
This patch implements the igd_opregion using the write_acpi_tables
mechanism to support GOP usage.

BRANCH=none
BUG=chrome-os-partner:44559
TEST=W/o GOP_SUPPORT in config, Built and boot on kunimitsu/glados.
W/ GOP_SUPPORT enabled, build and boot on kunimitsu/glados, but on
glados Dev screen can not be seen (OS display is fine).
CQ-DEPEND=CL:303539

Change-Id: I4cd63dfe0d3f456c5f084e38db976425143f79e7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4db57463a69c6114b1e2ed4035d378ee3a82783f
Original-Change-Id: I6f3c29c1b608eeaad8f2bf79d17394d49f8e412c
Original-Signed-off-by: robbie zhang <robbie.zhang@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/303387
Original-Commit-Ready: Robbie Zhang <robbie.zhang@intel.com>
Original-Tested-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12142
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-27 15:15:22 +01:00
robbie zhang 32074149f7 fsp/intel common: Add support for Gfx PEIM (AKA GOP)
This patch provides the lb_framebuffer() for coreboot table with
fsp gop usage, add Igd Opregion register defines, and update the
UPD naming following fsp.

BRANCH=none
BUG=chrome-os-partner:44559
TEST=Built and boot on kunimitsu/glados.

Change-Id: I9cf9d991eb09d698e7a78323cd855c4c99b55eca
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cd6834057cca60716bc0e24cfc2cd60fed02be7a
Original-Change-Id: I64987e393c39a7cc1084edf59e7ca51b8c5ea743
Original-Signed-off-by: robbie zhang <robbie.zhang@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/303539
Original-Commit-Ready: Robbie Zhang <robbie.zhang@intel.com>
Original-Tested-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12141
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-27 15:15:15 +01:00
robbie zhang 246115eb01 coreboot: make lb_framebuffer a weak function
This is to support other gfx enable method such as Gfx Peim (AKA GOP)
for Intel soc.

BRANCH=none
BUG=chrome-os-partner:44559
TEST=Built and boot on kunimitsu/glados.

Change-Id: Ib8010ea6901ea906a8b4129807b94ace71ef1165
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ad26a99560009c487070cccf6ab132188b9e247d
Original-Change-Id: Id132718a8bcec5446cc4c0d9d636d26e8a99bb15
Original-Signed-off-by: robbie zhang <robbie.zhang@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/303801
Original-Commit-Ready: Robbie Zhang <robbie.zhang@intel.com>
Original-Tested-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12140
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-27 15:15:09 +01:00
Timothy Pearson 2003844378 cpu/amd/car: Add initial Suspend to RAM (S3) support
Romstage handoff copied from cpu/intel/haswell/romstage.c

Change-Id: I1e1a67fa3c2c13cebcf8f0af318055b9d97d0a59
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11953
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-27 15:12:08 +01:00
Shawn Nematbakhsh ff5d0b2518 libpayload: usb: Retry get_descriptor() on failure
Certain Lexar USB disks may fail during the first calls to
get_descriptor(..., DT_CFG, ...) for unknown reasons. Therefore, make
several attempts before giving up.

BUG=chromium:466758
TEST=Manual on Samus. Go to recovery mode, verify that Lexar LJDS70 USB
stick is bootable.
BRANCH=None

Change-Id: I476ac22f9c4f844c60ebc6e53af8c144d70bb9d4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 93a0570b343479dd22506ad4d7961f0ea4251f8c
Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Original-Change-Id: Ie581c7c71c53816065c7f59202581888a79e445e
Original-Reviewed-on: https://chromium-review.googlesource.com/302403
Original-Commit-Ready: Shawn N <shawnn@chromium.org>
Original-Tested-by: Shawn N <shawnn@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/12133
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-27 15:00:16 +01:00
Alexander Couzens d1adafec05 cpu: create an empty file when no microcode files are given
Having an empty microcode file makes it more easy to debug
in comparison to a not existing file in cbfs. There are some
platforms (e.g. ep80579) which support microcode updates but
not having any microcode updates yet in our tree.

These platform hang the build because `cat` is called with no
parameters.

Change-Id: I2699bde0c62ae62ca888686f8b496e845c36d970
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: http://review.coreboot.org/12109
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-10-27 11:12:02 +01:00
Julius Werner c19f876e94 Makefile: Fix dependency tracking for linker scripts
When the memlayout framework was initially developed in the Chromium OS
tree, the accompanying build system changes unified handling for all
file types (including .ld and .asl) in a single template. This had the
advantage that compiler invocation options pertaining to the build
system itself could be centralized in a single place.

On upstreaming this was reverted for some reason, keeping the old
special handling for ASL files and writing a custom template for LD. The
duplicated compiler invocation code for the latter was missing the -MMD
flag required for dependency tracking. It was also missing at least one
$-sign which causes the $(<class>-ld-ccopts) variable to be evaluated at
the time it's parsing the template generator (before the subdirectory
pass). This should not cause any issues with current code, but all the
ccopts variables were meant to be evaluated after the subdirectory pass
(so things like archs and SoCs can manipulate them if needed), so this
patch fixes both issues.

BRANCH=None
BUG=None
TEST='make; touch src/soc/.../memlayout.ld; make' re-links all stages
and includes the changed symbol addresses from the new address map.

Change-Id: I4be458112908380268229b3220cfa0062add5c5d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e8a36f994ef6a819ded7bf6b39b1e0fce8e52279
Original-Change-Id: If2310b46b53d888975cb2113edce20a896be39ef
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/303054
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/12139
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-10-27 09:26:06 +01:00
Rudolf Marek a00e61599a asus/f2a85-m: Activate IOMMU support
Activate the IOMMU support for the Asus F2A85-M.

Add the device to `devicetree.cb`.

    $ lspci -s 0.2
    […]
    00:00.2 IOMMU: Advanced Micro Devices [AMD] Family 15h (Models 10h-1fh) I/O Memory Management Unit
    $ dmesg
    […]
    [    0.000000] ACPI: IVRS 00000000bf144e10 00070 (v02  AMD   AMDIOMMU 00000001 AMD  00000000)
    [    0.000000] ACPI: SSDT 00000000bf144e80 0051F (v02    AMD     ALIB 00000001 MSFT 04000000)
    [    0.000000] ACPI: SSDT 00000000bf1453a0 006B2 (v01 AMD    POWERNOW 00000001 AMD  00000001)
    [    0.000000] ACPI: SSDT 00000000bf145a52 00045 (v02 CORE   COREBOOT 0000002A CORE 0000002A)
    […]

Linux 3.10 reported several IO page faults, which could never be explained and
which the vendor firmware did not. These errors couldn’t be reproduced with
Linux 3.18 by Damien Zammit.

Change-Id: I0aa530be17d31656e65db6113343f2ea7008b843
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/3517
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-27 09:04:13 +01:00
Timothy Pearson 99e1a672ec northbridge/amd/amdfam10: Limit maximum RAM clock to BKDG recommendations
Change-Id: I45eb03a4b351e458e8448245896743bd6fa57637
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11943
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-27 05:31:57 +01:00
Timothy Pearson b8a355dcdf northbridge/amd/amdmct: Fix broken AMD K10 DDR3 memory initalization
The native AMD DDR3 memory initialization code was riddled with
numerous errors and was missing critical configuration code segments;
this made it so that DDR3 memory did not function on most AMD boards.

This patch corrects enough of the DDR3 initialization such that
UDIMMs can be used on most channels of G34 Opteron boards.  Further
work is needed to fix the broken RDIMM code and remaining UDIMM issues.

Change-Id: Iab690db769e820600693ad1170085623b177b94e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11941
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-10-26 23:52:54 +01:00
Timothy Pearson 7a5413a81c southbridge/amd/sr5650: Add AMD Family 15h CPU support
Change-Id: I88203907270db1a268bd377151f15c24fca1efdc
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11964
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-26 07:32:58 +01:00
Stefan Reinauer 850e7d4884 vgabios: fix compilation after x86emu changes
This utility links in coreboot code, and has been broken for a while
again after removing some hacks from coreboot. I hadn't realized how
bad it was broken last time, and since most of this stuff is still
in a pretty bad shape, I decided to throw all of the changes together.

Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Change-Id: If3e4399b1b0e947433b97caa29962ef66ea2993d
Reviewed-on: http://review.coreboot.org/11736
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-25 21:33:32 +01:00
Jonathan A. Kollasch 3acece2362 AMD Family 0Fh: ensure CONFIG_CBB and CONFIG_CDB have sane values
(this probably fixes relocate_sb_ht_chain() on tyan/s2885)

Change-Id: I5a26f4280b00bfb259c600048f6a7391a6c1268f
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/10913
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-10-25 16:46:50 +01:00
Aaron Durbin 5213c53f6f cbfstool: have decompress functions provide ouput data size
Currently cbfs stage files that are compressed do not have
the decompressed size readily available. Therefore there's
no good way to know actual size of data after it is
decompressed. Optionally return the decompressed data size
if requested.

Change-Id: If371753d28d0ff512118d8bc06fdd48f4a0aeae7
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12173
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-25 13:23:15 +01:00
Aaron Durbin cd9ba8ac03 cbfstool: initialize offset field in buffer_init()
If one wants to use buffer_init() for initializing a
struct buffer all the fields should be initialized.

Change-Id: I791c90a406301d662fd333c5b65b2e35c934d0f7
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12172
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-25 13:22:21 +01:00
Denis 'GNUtoo' Carikli 8eb63fa063 Add support for the Silicon Image "Ultra ATA-133 Host Controller"
This patch was tested with the following card:
  IDE interface: Silicon Image, Inc. PCI0680 Ultra ATA-133 Host Controller [1095:0680] (rev 02)

Change-Id: I988b73684b54942d8ee6e44a9319dcc54086fca7
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/12171
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-25 07:33:24 +01:00
Lee Leahy 5c68bbc7d6 intel/kunimitsu: Add chromeos to verstage
In order to build stand alone verstage the chromeos.c
file needs to be part of the verstage target.

BRANCH=none
BUG=chrome-os-partner:44827
TEST=Build and run on kunimitsu

Change-Id: I9c547ae177dc95030c8c545a302a2349bf1c9cf8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 07b6465f0b3e18d30647959b8e1db44d8647cf90
Original-Change-Id: I49bf7f1bd2edb32ffe9cc22f6fce1348434fd234
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/301243
Original-Commit-Ready: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12152
Tested-by: build bot (Jenkins)
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2015-10-25 07:32:50 +01:00
David Hendricks f23216dc5b rockchip/rk3288: Remove 1392MHz option for RK3288 APLL
It's no longer used.

BUG=none
BRANCH=none
TEST=it compiles

Change-Id: I3d9385e0e1f14977c1632f3a8dda771c684ce458
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5381b6434996da10706dd358928f98703ac0892c
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: Ib0cfaf1bb173a7150f7ff504b9f58a62eb82e781
Original-Reviewed-on: https://chromium-review.googlesource.com/302634
Reviewed-on: http://review.coreboot.org/12138
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2015-10-25 07:32:10 +01:00
David Hendricks fd9cdf6dec google/veyron_rialto: Throttle to 1416MHz @ 1200mV in bootblock
The 1392MHz value used to throttle the RK3288 earlier was somewhat
arbitrary. This patch brings the throttling in sync with the operating
points specified in the Linux device tree for RK3288.

BUG=chrome-os-partner:42054
BRANCH=none
TEST=Saw print statement in image.serial.bin indicating that APLL
was set to the desired frequency.

Change-Id: Ibe570267bbfe23f010ad5e1ea651356291b9c63c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a146f23b13cb0f6da93ada65648cf33ecfaaa7d6
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I6bcdb5fd6ffa3f9a22e79c519bdb7980492e2318
Original-Reviewed-on: https://chromium-review.googlesource.com/302633
Reviewed-on: http://review.coreboot.org/12137
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2015-10-25 07:31:57 +01:00
David Hendricks 4a14dc2fd9 rockchip/rk3288: Add 1416MHz as an option for RK3288 APLL
BUG=chrome-os-partner:42054
BRANCH=none
TEST=tested with subsequent patch

Change-Id: I92d67ff4b706c16677661ead1edd5c190ccc6d95
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: dced0fcbc35457d7326d590948ce5fe098a5e735
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I7b29c647380046ac41a290b19fdfba186bcb2127
Original-Reviewed-on: https://chromium-review.googlesource.com/302632
Reviewed-on: http://review.coreboot.org/12136
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2015-10-25 07:31:47 +01:00
David Hendricks ccecd457df google/veyron_rialto: Reduce voltage and frequency in recovery mode
This applies CL:300617 to Rialto to down throttle further in
recovery mode.

BUG=chrome-os-partner:42054
BRANCH=none
TEST=Saw print statment in recovery mode with image.serial.bin,
device only got mildly warm after several minutes (not hot).

Change-Id: I08b6024d31c83c6bbd8c8d9d9a07adc9835e81fd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 74eb9143fbe13df5f386185eab9e5ba9df27cadf
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I9e57d826750cb523c115332fa13a6143bcff7449
Original-Reviewed-on: https://chromium-review.googlesource.com/302631
Reviewed-on: http://review.coreboot.org/12135
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2015-10-25 07:31:40 +01:00
David Hendricks c8c099f1ea rockchip/rk3288: Add 600MHz as an option for RK3288 APLL
BUG=chrome-os-partner:41201
BRANCH=firmware-veyron
TEST=tested with subsequent patch on mickey
Signed-off-by: David Hendricks <dhendrix@chromium.org>

Change-Id: I7081d92be128f522e1a33eee6f3de9dfbbf042ea
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a390c927ad8ed035520c8a813db808715dc5e527
Original-Change-Id: I3ce0f7b2772c8c652b7f461749d01cc7b669b6cf
Original-Reviewed-on: https://chromium-review.googlesource.com/300616
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/12134
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2015-10-25 07:31:34 +01:00
Stefan Reinauer 67a71ea230 yabel: explicitly cast values to match printk expectations
Change-Id: Id2230ecd800b138b6ccbbac318e71c9edf076c75
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12116
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-25 07:29:55 +01:00
Stefan Reinauer 21f8193843 yabel: Use IS_ENABLED where appropriate
Change-Id: Ib078b21ddf0493ad6795c6ab79125b3917ff7049
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12115
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-25 07:29:38 +01:00
Stefan Reinauer 4919047d31 yabel: Don't cast pointer to u32
Change-Id: I45b3412263507d92f443743d2ee63c9a8ef94795
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12114
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-25 07:29:32 +01:00
Konstantin Aladyshev 6544cb3f1b Separate bootsplash image menuconfig option from others
The possibility of adding a bootsplash image to ROM should be independent
from VGA_ROM_RUN and VESA menuconfig options.
For example, the stored image could be saved in CBFS not for coreboot
but for later use in SeaBIOS.

Change-Id: I3a0ed53489c40d4d44bd4ebc358ae6667e6c797f
Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru>
Reviewed-on: http://review.coreboot.org/12129
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-25 07:28:38 +01:00
Timothy Pearson 4731423b91 southbridge/amd/sb700: Add option for last power state after failure
Change-Id: Ieb27bd51dfd45dd15d24a576865d38180a07444e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12175
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: build bot (Jenkins)
2015-10-25 06:22:50 +01:00
Timothy Pearson 83c3c9e1d5 cpu/amd/car: Use standard integer types in post_cache_as_ram.c
Change-Id: I02c1fba5c749d5adb33ec86777bde108e587caa6
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12185
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2015-10-25 06:08:08 +01:00
Timothy Pearson ee3ec8e212 southbridge/amd/sb700: Set up uninitialized devices in early boot
LPC decodes were not enabled, leading to a failure of POST 80 cards
and similar debugging devices.  Enable the relevant LPC decodes
to allow debugging.

Additionally, the SMBUS controllers were not properly set up.
Enable both the primary and auxiliary controllers.

Finally, K10 and higher CPUs were hanging during boot due to
a misconfigued IOAPIC.  Properly configure the IOAPIC.

Change-Id: I9ffb6542ce445ac971fb81f4f554e7f1313e6a98
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12177
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: build bot (Jenkins)
2015-10-25 05:05:46 +01:00
Timothy Pearson 2a16acee6b northbridge/amd/amdfam10: Enable advanced PCIe setup options
TEST: Booted ASUS KGPE-D16 and verified device functionality.

Change-Id: Ic6f5b3ca86eb55dc04291be0db67d06c34c6a6dc
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12188
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Peter Stuge <peter@stuge.se>
2015-10-25 04:51:00 +01:00
Timothy Pearson 785b3eb6e8 device/pciexp_device: Tune PCIe bridges before scanning children
Change-Id: Ieccafe8864d622c651e6a524e9898505ded15e54
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12187
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Peter Stuge <peter@stuge.se>
2015-10-25 04:49:31 +01:00
Timothy Pearson 7d8a478e70 device/pci_device: Set bridge primary bus number before scanning
Certain devices, such as the Intel 82575GB, contain multiple nested
PCIe bridges (for example the PES12N3A).  Coreboot does not set
the primary bus number of the lower bridges, causing upstream
forwarding failure.  This in turn causes coreboot to fail to find
the lowest devices (in this case the NICs), and as a result the
required resources are not allocated and the NICs do not function.

Change-Id: I4fd3aa21a04dbe89ac6a5995e7707af914d432b1
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12186
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Peter Stuge <peter@stuge.se>
2015-10-25 04:47:10 +01:00
Timothy Pearson d657446884 cpu/amd/car: remove PRINTK_IN_CAR #define that was hardcoded to 1
Change-Id: I5139ee222a0dca7f8e62612a39d30cad7976b505
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12184
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2015-10-25 04:25:39 +01:00
Timothy Pearson 1c4508e77c cpu/amd: Add initial support for AMD Socket G34 processors
Change-Id: Iccd034f32c26513edd52ca3a11a30f61c362682d
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11940
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-10-24 21:33:07 +02:00