Commit Graph

40615 Commits

Author SHA1 Message Date
Felix Held f1eaa67221 soc/amd/common/block/data_fabric: add warning about broadcast reads
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If1b65ae3dd2b5c8fe7bc29a267d108e4d3a3e567
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50883
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-19 23:13:56 +00:00
Felix Held 746f438ada soc/amd: move SMM finalization to common code
This adds the SMM finalization to Cezanne.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1a2b433d92df2a76979e2e6a3d1dde996303ba78
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50801
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-19 22:11:30 +00:00
Felix Held 7aacdd1d35 soc/amd/cezanne: add MP init and SMM initialization
Change-Id: I38d52394b5f6ffb837fa753fc9e82c0450c6aae3
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50505
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-19 22:11:14 +00:00
Moritz Fischer f6e3254a9b soc/rockchip/rk3399/clock: Add rkclk_ddr_reset() function
This adds the rkclk_ddr_reset() function equivalent for the RK3399.

Signed-off-by: Moritz Fischer <moritzf@google.com>
Change-Id: If1da85064d75bdf49b7555d09257409443c25e8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50889
Reviewed-by: ron minnich <rminnich@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-19 19:09:02 +00:00
Moritz Fischer c73102d0f5 soc/rockchip/rk3399/sdram: Add phy_ctrl_reset
Add support for resetting PHY PCTRL for both channel 0 and 1.

On the ROCKPro64 board this allows getting past a pctl_cfg() failure.

Signed-off-by: Moritz Fischer <moritzf@google.com>
Change-Id: I9f807e318ffc63c568d04518c3edd02c1064e185
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50890
Reviewed-by: ron minnich <rminnich@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-19 19:08:29 +00:00
Moritz Fischer d8f352b4fd soc/rockchip/rk3399/sdram: Clear PI_175 IRQs in data training
Clear PI_175 interrupts before attempting training in all relevant
calls.

Ported from u-boot.

Signed-off-by: Moritz Fischer <moritzf@google.com>
Change-Id: Ib73f58265db62494282dbec42ec4bf2950617e12
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50886
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-19 19:06:35 +00:00
Angel Pons d8fcd42089 mb/hp/280_g2: Add new mainboard
This is a µATX mainboard with a LGA1151 socket and two DDR4 DIMM slots.

There are two possible BOM configurations: Sid has no legacy devices,
whereas Manny provides two serial ports, a parallel port, a PCI slot
and PS/2 keyboard/mouse connectors. These boards also have different
Super I/O models: Manny uses an ITE IT8625E, whereas legacy-free Sid
comes with an ITE IT8656E instead.

This coreboot port has been done using a Sid board, thus support for
Manny-specific features is missing. Booting should still be possible,
though: none of these legacy features is essential.

The board has an unpopulated 6-pin header, wired to PCH UART 2. This
can be used to retrieve coreboot logs.

Working:
- Both DIMM slots (Micron CT4G4DFS8213.8FA11, Hynix HMA851U6AFR6N-UH)
- PCH SerialIO UART 2 to get coreboot logs
- Rear USB ports
- Realtek RTL8111 GbE NIC
- Integrated graphics on DVI with libgfxinit
- At least one SATA port
- Flashing internally with flashrom
- S3 suspend/resume
- VBT
- SeaBIOS 1.14 to boot Arch Linux (kernel linux-5.10.15.arch1-1)

Untested:
- Audio
- VGA: DP2VGA chip uses DDI E, and libgfxinit doesn't support DDI E yet
- Front USB headers
- Non-Linux OSes
- PCI slot
- IT8625E peripherals: serial, parallel and PS/2 ports

Change-Id: Iadf11c187307a24b15039a5a716737d9d74944e6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48386
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-19 14:27:19 +00:00
Mathew King 44948a7c5c mb/google/guybrush: Enable CONFIG_CHROMEOS
BUG=b:175143925
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I8d038126b3e511bd16df2144652992c2d5b56c87
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50507
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-19 13:34:31 +00:00
Felix Held e09294f57a include/cpu/amd/msr: rename MSR_PSP_ADDR to PSP_ADDR_MSR
The new name is more consistent with the rest of the MSR definitions.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5666d9837c61881639b5f292553a728e49c5ceb2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50855
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-19 13:20:16 +00:00
Felix Held 285dd6ec3a soc/amd/common/amdblocks/psp: move MSR_PSP_ADDR to include/cpu/amd/msr.h
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5bd6f74bc0fbe461fa01d3baa63612eaec77b97a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50854
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-19 13:19:24 +00:00
Julius Werner 82d16b150c memlayout: Store region sizes as separate symbols
This patch changes the memlayout macro infrastructure so that the size
of a region "xxx" (i.e. the distance between the symbols _xxx and _exxx)
is stored in a separate _xxx_size symbol. This has the advantage that
region sizes can be used inside static initializers, and also saves an
extra subtraction at runtime. Since linker symbols can only be treated
as addresses (not as raw integers) by C, retain the REGION_SIZE()
accessor macro to hide the necessary typecast.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ifd89708ca9bd3937d0db7308959231106a6aa373
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-02-19 08:39:26 +00:00
Mathew King 422501fb14 mb/google/mancomb: Add new mainboard
Mancomb is a new Google mainboard with an AMD Cezanne SOC.

BUG=b:175143925
TEST=builds

Change-Id: I1264f44a0b986f7f7c89ac7b42f1e4e4119a35e6
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50007
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-19 08:38:58 +00:00
Patrick Rudolph e75f1807e1 mb/prodrive/hermes/eeprom: Add function to read HSI from EEPROM
Will be used to determine the board revision.

Change-Id: I41e4c6ad83e23c9d79e6abab3f38ad46bd3bec06
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50788
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-19 08:37:59 +00:00
Patrick Rudolph b67f385b69 mb/prodrive/eeprom: Add BMC settings
Add settings describing the BMC.
Will be used by the following patch to read the board revision.

Change-Id: If464138fc1bdf02a45a21f638b179048d68d974d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50787
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-19 08:37:49 +00:00
Tim Wawrzynczak 2091965973 mb/google/brya: Enable MLB USB Type-A Port
The USB Type-A port on the MLB was added to the schematic at the last
minute and it was missed when adding brya0's overridetree. Also fix
a few USB ACPI entries.

BUG=b:180403898
TEST=`lsusb` shows plugged-in flash drive

Change-Id: I8bf96a8b365cb4ea2fc07d7cf673b08e8872ff88
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-18 23:58:22 +00:00
Angel Pons 887cf3017a soc/intel/common: Drop unused `fast_spi_flash_read_wpsr` function
Also remove one macro that was only used inside that function.

Change-Id: Id798e08375c5757aa99288ca4a7df923309f4d67
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-02-18 23:57:54 +00:00
Angel Pons 5207243270 soc/intel/common/block/fast_spi: Define __SIMPLE_DEVICE__
Change-Id: Iff6111ab379229daec7a3892c330de6b5f0e5157
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-02-18 23:21:04 +00:00
Karthikeyan Ramasubramanian a7e6788ea7 drivers/i2c/hid: Enforce level triggered IRQ mode
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4,
the interrupt line used by the device is required to be level triggered.
This change ensures that the IRQ is appropriately configured.

References:
[1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx

BUG=b:172846122
TEST=./util/abuild/abuild. Build and boot to OS in Dedede.

Change-Id: I3245a9de6e88cd83528823251083e62288192f0d
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-02-18 22:48:27 +00:00
Subrata Banik 02bec2bd5c lib: Add DDR5 DRAM type
TEST=Not seeing default msg "Defaulting to using DDR4 params." with
this CL.

Change-Id: Ib751396ec74b1491fd08b88b07462b315c4a152d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50745
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18 22:47:59 +00:00
Moritz Fischer c867cd3675 soc/rockchip/rk3399/sdram: Move WDQL training into a separate function
Move WDQL training into its own function to enable better error handling.

Signed-off-by: Moritz Fischer <moritzf@google.com>
Change-Id: I8544d6956ca1ce655093a549e7d2928ac9b279bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50865
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18 21:28:53 +00:00
Moritz Fischer 401c7a648a soc/rockchip/rk3399/sdram: Move RL training into a separate function
Move RL training into its own function to enable better error handling.

Signed-off-by: Moritz Fischer <moritzf@google.com>
Change-Id: I02ffbd9deb3fff3bfd8d6e28d6e6d84a4b8c39ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50864
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18 21:27:30 +00:00
Moritz Fischer 12d360012c soc/rockchip/rk3399/sdram: Move RG training into a separate function
Move RG training into its own function to enable better error handling.

Signed-off-by: Moritz Fischer <moritzf@google.com>
Change-Id: I12f17123bc963ffa2dec1559343a141406a5e98d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50863
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18 21:26:43 +00:00
Moritz Fischer 68365e10e3 soc/rockchip/rk3399/sdram: Move WL training into a separate function
Move WL training into its own function to enable better error handling.

Signed-off-by: Moritz Fischer <moritzf@google.com>
Change-Id: I7917846c51982a2473f11d14c51c270e59e59d74
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50862
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18 21:26:13 +00:00
Moritz Fischer f71902da5f soc/rockchip/rk3399/sdram: Move CA training into a separate function
Move CA training into its own function to enable better error handling.

Signed-off-by: Moritz Fischer <moritzf@google.com>
Change-Id: Iefaec3121afbb3b29858e03f903d2ffc5ac75da0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50861
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18 21:24:46 +00:00
Moritz Fischer a76f659840 soc/rockchip/rk3399/sdram: Order and group tsel variables
Order and group tsel variables in a meaningful way.

No functional changes.

Signed-off-by: Moritz Fischer <moritzf@google.com>
Change-Id: I417e0fbc129c2d9ad1b345bcff2e25ca6eca83bc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50866
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18 21:23:49 +00:00
Jakub Czapiga c4ca8c3556 tests: Add lib/memcmp-test test case
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Ib63123a36179127af4e3720ed01ca2611daa607e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-02-18 19:12:46 +00:00
Moritz Fischer 6410a0002f soc/rockchip/rk3399/sdram: Shorten sdram_params to params
This shortens the use of sdram_params variable names to params.

No functional changes.

Signed-off-by: Moritz Fischer <moritzf@google.com>
Change-Id: I122035078ce37fe65b16bb1f3a2b2d58956431aa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50860
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18 16:19:16 +00:00
Moritz Fischer f34bdf8c5e mainboard/pine64/rockpro64: Add initial ROCKPro64 support
This adds initial support for the Pine64 ROCKPro64 board.

The ROCKPro64 (http://pine64.org/rockpro64) is a SBC using the
RK3399 SoC with up to 4GB LPDDR4.

So far only the bootblock part works, the romstage starts to execute,
though.

For ramstage to work we'll need to port some of the changes required
for LPDDR4 vs LPDDR3. This will be addressed in follow up changes.

UART2 on the PI-2 connector can be used as a coreboot console.

  GND is pin 6
  TXD is pin 8
  RXD is pin 10

Flashing:
  I used an OpenWRT nightly for the ROCKPro64 and its builtin tool.

  $ mtd write coreboot.rom /dev/mtd0

Recovering from a bad flash:
  To recover from a bad flash bridging pins 23 and 25 on the PI-2
  connector will make the board boot from SD card.

Signed-off-by: Moritz Fischer <moritzf@google.com>
Change-Id: I47d0031fff8ee10b11ad74935eaeb05f1f7eb4b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50625
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18 16:18:18 +00:00
Felix Held b2d633db07 soc/amd/common/block/data_fabric: fix data_fabric_write32 broadcast case
Calling data_fabric_write32 with BROADCAST_FABRIC_ID as instance_id
would have caused an infinite recursion, so call the right function
data_fabric_broadcast_write32 for that case instead.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If7f0a80f0430e8bfb29ee510ef86c278e3a42063
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-18 11:41:15 +00:00
Angel Pons ff254ea60b nb/intel/pineview: Drop unused `GPIO32` macro
It's not used, and GPIO registers are on the southbridge.

Change-Id: I0b7b6edc22d461007f24618eca42091439a53d3c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45423
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18 10:14:56 +00:00
Jakub Czapiga 7a940dfb22 tests: Add lib/memset-test test case
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I6750caa8ccdc442f78b782407ebfb3af78f476ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-02-18 10:14:21 +00:00
Paul Menzel 54d500788c Makefile: Do not use GCC specific options with LLVM/clang
Building with LLVM/clang (`COMPILER_LLVM_CLANG=y`), Debian clang version
11.0.1-2 fails due to unknown warning options.

    error: unknown warning option '-Wlogical-op'; did you mean '-Wlong-long'? [-Werror,-Wunknown-warning-option]
    error: unknown warning option '-Wduplicated-cond' [-Werror,-Wunknown-warning-option]

As these are GCC specific, only add them, when building with GCC (and
not scan-build).

Fixes: 04e0712f46 ("Treewide: Add some gcc's warning options")
Change-Id: I6190c1f3df97fb0be51f8dab7e1f5f2a033f5d86
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-18 10:12:57 +00:00
Angel Pons 0a20872de0 nb/intel/sandybridge: Use 133 MHz ref clock for DDR3-2400
The 100 MHz reference clock seems to be unstable when using high
multipliers. Use the 133 MHz reference clock instead.

Change-Id: I400e4f91776306d54d818fa249d7a845020ac37b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45503
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18 10:12:43 +00:00
Angel Pons fe276fb250 nb/intel/sandybridge: Clean up `dram_freq` function
The thing that this function initializes is the MPLL (Memory PLL). So,
call it by its name. Also add a missing newline in a printk, and update
a comment on the callsite of this function.

Tested on Asus P8Z77-V LX2, still boots.

Change-Id: I86ab643bc87253554346dfed3630eb9ddbd44eb3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-02-18 10:12:18 +00:00
Arthur Heymans 1999bc5d00 soc/intel/skylake: Move soc_fsp_load
Move this function into the compilation unit where it is called.

Change-Id: Ia4bdcd545827c2564430521a98246fc96bf0ba92
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50796
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18 10:11:55 +00:00
Angel Pons c027ece821 southbridge: Ensure common Kconfig gets included last
Change-Id: Icaa64e664499090fec3e98687b4827ef27cc201b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-18 10:11:39 +00:00
Patrick Rudolph 442bde7b62 src/cpu: Remove unused symbols
Remove the unused Kconfig symbol CPU_MICROCODE_MULTIPLE_FILES.

Change-Id: I18115e07694658a2f77c447d3ab5c899c1bdcc61
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-18 10:11:24 +00:00
Angel Pons 959a448806 sb/intel/ibexpeak: Drop obsolete SATA register settings
Code was copy-pasted from older chips and has no effect on ibexpeak.

Change-Id: I3c5b2b8e4aa6211975c3e3dc1d64432886ef9352
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47864
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18 10:11:08 +00:00
Angel Pons 805ff571e3 nb/intel/haswell: Drop incorrect MMIO_PAVP_MSG write
This write was copied from Sandy Bridge. Neither Haswell reference code
nor Broadwell perform this write. Therefore, it seems safe to remove it.

Change-Id: I8869ff3e66362d9910235c554c3a07e91f479a82
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46994
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18 10:10:54 +00:00
Angel Pons 2fa838dbab mb/google/brya: Remove `Some generic macros` comment
This comment is useless, and was dropped from the tree in the past.

Change-Id: Ie46bf13ec27ff9cd9423795fc170cc7526e18122
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49124
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18 10:10:28 +00:00
Angel Pons 9b629ad37f sb/intel/lynxpoint: Correct read width in RMW cycle
The register is 32 bits wide, so do not read 16 bits out of it.
LynxPoint PCH reference code version 1.9.1 always uses 32-bit accesses.

Change-Id: I18fbba0603579417e09ae4eb4eb273f7fcd903fc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47098
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18 10:10:13 +00:00
Julius Werner ea9c96aa9c commonlib/bsd: Fix direct inclusion of <endian.h>
<endian.h> should never be included directly in commonlib files and
should instead be chain-included via <commonlib/bsd/sysincludes.h>.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ibc67ea97da36ec58738236ef22f961d9bbaf8574
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-02-18 02:33:04 +00:00
Julius Werner 10ee7fc03a cbfs: Fix attribute tag printing in cbfs_find_attr()
Attribute tags are defined as hexadecimal constants, not decimal, so it
makes more sense to print them like that in error messages as well.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I3a5a6a8c9b8d24e57633595fc47221a483d8593a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-02-18 02:32:56 +00:00
Julius Werner 5779ca718c cbfstool: Replace FILENAME_ALIGN 16 with ATTRIBUTE_ALIGN 4
cbfstool has always had a CBFS_FILENAME_ALIGN that forces the filename
field to be aligned upwards to the next 16-byte boundary. This was
presumably done to align the file contents (which used to come
immediately after the filename field).

However, this hasn't really worked right ever since we introduced CBFS
attributes. Attributes come between the filename and the contents, so
what this code currently does is fill up the filename field with extra
NUL-bytes to the boundary, and then just put the attributes behind it
with whatever size they may be. The file contents don't end up with any
alignment guarantee and the filename field is just wasting space.

This patch removes the old FILENAME_ALIGN, and instead adds a new
alignment of 4 for the attributes. 4 seems like a reasonable alignment
to enforce since all existing attributes (with the exception of weird
edge cases with the padding attribute) already use sizes divisible by 4
anyway, and the common attribute header fields have a natural alignment
of 4. This means file contents will also have a minimum alignment
guarantee of 4 -- files requiring a larger guarantee can still be added
with the --alignment flag as usual.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I43f3906977094df87fdc283221d8971a6df01b53
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47827
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-02-18 02:32:45 +00:00
Julius Werner f0cc7adb2f cbfstool: Ensure attributes always come last in the metadata
In a rare placement edge case when adding a file with alignment
requirements, cbfstool may need to generate a CBFS header that's
slightly larger than it needs to be. The way we do this is by just
increasing the data offset field in the CBFS header until the data falls
to the desired value.

This approach works but it may confuse parsing code in the presence of
CBFS attributes. Normally, the whole area between the attribute offset
and the data offset is filled with valid attributes written back to
back, but when this header expansion occurs the attributes are followed
by some garbage data (usually 0xff). Parsers are resilient against this
but may show unexpected error messages.

This patch solves the problem by moving the attribute offset forwards
together with the data offset, so that the total area used for
attributes doesn't change. Instead, the filename field becomes the
expanded area, which is a closer match to how this worked when it was
originally implemented (before attributes existed) and is less confusing
for parsers since filenames are zero-terminated anyway.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I3dd503dd5c9e6c4be437f694a7f8993a57168c2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-02-18 02:32:37 +00:00
Julius Werner ff61a39e90 cbfstool: Remove location pointer from parse_elf_to_stage()
The *location argument to parse_elf_to_stage() is a relic from code all
the way back to 2009 where this function was still used to parse XIP
stages. Nowadays we have a separate parse_elf_to_xip_stage() for that,
so there is no need to heed XIP concerns here. Having a pointer to
represent the location in flash is absolutely irrelevant to a non-XIP
stage, and it is used incorrectly -- we just get lucky that no code path
in cbfstool can currently lead to that value being anything other than
0, otherwise the adjustment of data_start to be no lower than *location
could easily screw things up. This patch removes it.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ia7f850c0edd7536ed3bef643efaae7271599313d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49369
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-02-18 02:32:28 +00:00
Julius Werner 84446e6e54 rmodtool: Make memlayout symbols absolute and do not relocate them
Memlayout is a mechanism to define memory areas outside the normal
program segment constructed by the linker. Therefore, it generally
doesn't make sense to relocate memlayout symbols when the program is
relocated. They tend to refer to things that are always in one specific
spot, independent of where the program is loaded.

This hasn't really hurt us in the past because the use case we have for
rmodules (ramstage on x86) just happens to not really need to refer to
any memlayout-defined areas at the moment. But that use case may come up
in the future so it's still worth fixing.

This patch declares all memlayout-defined symbols as ABSOLUTE() in the
linker, which is then reflected in the symbol table of the generated
ELF. We can then use that distinction to have rmodtool skip them when
generating the relocation table for an rmodule. (Also rearrange rmodtool
a little to make the primary string table more easily accessible to the
rest of the code, so we can refer to symbol names in debug output.)

A similar problem can come up with userspace unit tests, but we cannot
modify the userspace relocation toolchain (and for unfortunate
historical reasons, it tries to relocate even absolute symbols). We'll
just disable PIC and make those binaries fully static to avoid that
issue.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ic51d9add3dc463495282b365c1b6d4a9bf11dbf2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50629
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-02-18 02:32:06 +00:00
Felix Held a2642d0ffe Revert "soc/amd: Add option to select if SOC supports ESPI sub decode"
This reverts commit 64d0ad347b. In the
current revision 3.001 of the PPR #56569 the register exists and the bit
definitions match.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie7a97843c3dac897f79f229b660b7e30b34eef93
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-18 01:17:19 +00:00
Felix Held b284013065 soc/amd/cezanne/root_complex: provide ACPI name in PCI device_operations
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7f17348b1146a07fcb3e905122d7185b60da962f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-18 01:16:04 +00:00
Felix Held 51c4d68fa7 soc/amd/cezanne/chip: add soc_acpi_name
We were missing this, so we ran into the scope assert in
acpi_device_write_pci_dev for the data fabric PCI devices.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I566791527ba839ba52ec5fa28f0f6c25f547d1da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50815
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18 01:15:55 +00:00