Commit Graph

17392 Commits

Author SHA1 Message Date
Lin Huang c4cbf482f7 rockchip: rk3399: add sdram driver
Add the sdram driver for rk3399. With this patch we can boot
into depthcharge.

This patch also include a config file for lpddr3-hynix-4GB
that generated bases on its datasheet.

Please refer to TRM V0.3 Part1 Chapter 9 for DMC.

BRANCH=none
BUG=chrome-os-partner:51537
TEST=boot to depthcharge on kevin

Change-Id: I2afcaa3b68dbad77a5fe677b835289b675ed2bef
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5d777e29942057fb7237eefa34051d1f54b19405
Original-Change-Id: Ifa1fe98a7058869518757d50678a64620610d91d
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/332562
Reviewed-on: https://review.coreboot.org/14716
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09 08:45:13 +02:00
Shunqian Zheng 5dae9306d9 rockchip: rk3399: init the secure setting
set sdram, sram and all device to non-secure status,
so we can free to do mmu operation in coreboot. bl31
will care about secure control.

BRANCH=none
BUG=chrome-os-partner:51537
TEST=emerge-kevin coreboot

Change-Id: I11e02246550630c6dfe4e0cbad01e8cd5b83ef1e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ae2df532856110c4d87eb162fd3687f8de27c77f
Original-Change-Id: Ia026cf685a9d7bdf7b0c7181b1b325c54bc4554f
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/338947
Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/14715
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09 08:44:52 +02:00
Lin Huang ef2eb9df6c rockchip: rk3399: enable pwm
Reuse the rockchip common pwm driver.

BRANCH=none
BUG=chrome-os-partner:51537
TEST=emerge-kevin coreboot

Change-Id: I1a1ab237f891f06affb74817b5cae1a034a9760e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 37afce0f94435ffef8bdd74b4251430f11ec22f4
Original-Change-Id: Ia94985f56e424d049fdcc5be86c696577d52a07c
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/333255
Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/14714
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09 08:44:19 +02:00
Vadim Bendebury 92c2f5e38b rockchip: rk3399: add gpio driver
Reuse the common gpio driver and implement some stubs
in gpio.h.

RK3288 has one pmu gpio while RK3399 have two.

Please refer to TRM V0.3 Part2 Chapter 11 for GPIO section.

BRANCH=none
BUG=chrome-os-partner:51537
TEST=emerge-kevin coreboot

Change-Id: I041865ce269b0ae1f6a07e6c37d53d565a37c5ef
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d416ba0ce6a1ff2cf52f6b83ade601d93b40ffeb
Original-Change-Id: I1d213a91ea508997b876441250743671204d7c53
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/332560
Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/14713
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09 08:43:54 +02:00
Shunqian Zheng 015ae11bf6 rockchip: refactor gpio driver
The gpio of rockchip SoCs(rk3288 & rk3399) are the same IP,
moving the gpio code of rk3288 to common then can be reused on rk3399.

BRANCH=none
BUG=chrome-os-partner:51537
TEST=build and boot into chromeos on veyron_jerry

Change-Id: I10a4b9d32afe60fd52512f2ad0007e9d2785033b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1c0c4b4b999790b0be7b0eeb70d2a7a86158f779
Original-Change-Id: If13b7760108831d81e8e8c950cdf61724d497b17
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/339846
Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/14712
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09 08:43:28 +02:00
huang lin 4f17374dfd rockchip: rk3399: add i2c clock driver
This patch add i2c clock driver and reuse the common
rockchip i2c driver.

The i2c0,4,8 src clock from ppll, while i2c1,2,3,5,6,7 from gpll.

Please refer to TRM V0.3 Part1 Page 142 for i2c clock setting.

BRANCH=none
BUG=chrome-os-partner:51537
TEST=emerge-kevin coreboot

Change-Id: I91822e483244d71798a1c68f14ba0a84f405a665
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 270118e44d159f6a27812fa234b34fe7ac54cbe4
Original-Change-Id: Iea5f4a93cf173e1278166dcb04e19a4ef6c4af04
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/338948
Reviewed-on: https://review.coreboot.org/14711
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09 08:43:07 +02:00
Shunqian Zheng 347c83cfc9 rockchip: rk3399: add spi clock driver
This patch implements spi clock driver and initialize
SPI flash rom for the baseboard gru.

There are 6 on-chip SPI controllers inside RK3399. For
SPI3, it's source clk from ppll, while the others from gpll.

Please refer to CRU session of TRM for detail.

BRANCH=none
BUG=chrome-os-partner:51537
TEST=emerge-kevin coreboot

Change-Id: I597ae2cc8ba1bfaefdfbf6116027d009daa8e049
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4c6a9b0aedd427727ed4f4a821c5c54fb3a174b9
Original-Change-Id: I68ad859bf4fc5dacaaee5a2cd33418c729cf39b8
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/338946
Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/14710
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09 08:42:43 +02:00
Shunqian Zheng a1f873f069 google/gru: enable uart2 if configured
This patch select gpio pins for UART2 which is the default
debug port of rk3399.

Please refer to TRM V0.3 Part1 Page 325,395 for GRF details.

BRANCH=none
BUG=chrome-os-partner:51537
TEST=check logs from console manually

Change-Id: I91eeadd543e7e895c3972d8dd7a2195c9d78968b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0c51955e18d4ff9cd3208697666af4fa77046e0f
Original-Change-Id: I960178628f4020a59d100f2f0b2a6be487892549
Original-Signed-off-by: hunag lin <hl@rock-chips.com>
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/338945
Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/14709
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09 08:42:24 +02:00
Lin Huang fe7aa2096d rockchip: rk3399: enable mmu
This patch initialize MMU and config mmu ranges for rk3399.

During the bootblock phase, mark the max dram size supported(4GiB)
as device memory because the mmio space start at 0xF8000000, and
_sram as secure memory.
After ddr setup in romstage, remark whole dram as cached memory
except the _dma_coherent range.

BRANCH=none
BUG=chrome-os-partner:51537
TEST=emerge-kevin coreboot

Change-Id: I0cd4abb8c30b73d87d8ba6f964edd42bdf4813fb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fc22ab0c16d8107c217db1629286d5ff1c4bc5b3
Original-Change-Id: I66bfde396036d7a66b29517937a28f0767635066
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/332387
Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/14708
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09 08:42:04 +02:00
Shunqian Zheng ce60d5a139 rockchip: rk3399: add functions to configure ddrc freq
This patch list four frequencies for ddr controller,
200MHz, 300MHz, 666MHz and 800MHz and configure
each freq by setting the DPLL dividers.

By default, the clk_ddrc is from DPLL and equals to DPLL,
so here we only need to set the DPLL clock.

BRANCH=none
BUG=chrome-os-partner:51537
TEST=emerge-kevin coreboot

Change-Id: Ifabe85b5dc95e3c8e3e9cbf946e12e8b06b881cf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 18ec4f7d8738472fbadd60fa3c8f810f5347ffa2
Original-Change-Id: I448057542c3885068ddffa5b37d0341ee3ec04b1
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/340184
Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/14707
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09 08:41:41 +02:00
Lin Huang a1f82a3498 rockchip: rk3399: support basic clock driver
This patch initialize the PLL clocks and add function to
configure cpu freq. Right now, we set the little cpu freq to 600MHz.

In coreboot, we currently care about these four PLLs,
o. APLL for cpu clk, where A stands for AXI,
o. CPLL and GPLL are the generic PLL mainly for peripheral clk,
o. PPLL is only PMU clk.

For the peripheral clocks, there are thress clocks named as,
 aclk_perihp,
 aclk_perilp0,
 hclk_perilp1,
where the 'h' and 'l' letters refer to High and Low speed.
As the diagram below, the aclk_perihp always be the parent of
more higher speed peripheral devices like pcie, and
hclk_perilp1 for spi, i2c, aclk_perilp0 for crypto.
These three clocks can choose parent from GPLL or CPLL freely,
in this patch, they are all sourced from GPLL.

GPLL(594M)/CPLL(384M)                      APLL(600M for little core)
   |                                           |
   `-- aclk_perihp                             `-- clk_core(600M == APLL)
   |       |                                           |
   |       `-- periph_aclk(148.5M)                     `-- atclk_core(300M)
   |       `-- periph_hclk(148.5M)                     `-- aclkm_core(300M)
   |       `-- periph_pclk(37.125M)                    `-- pclk_dbg_core(100M)
   |
   `-- hclk_perilp1
   |       |
   |       `-- periph_hclk(99M)            PPLL(594M)
   |       `-- periph_pclk(49.5M)              |
   |                                           `-- pmu_pclk(99M)
   `-- aclk_perilp0
           |
           `-- periph_aclk(99M)
           `-- periph_hclk(99M)
           `-- periph_pclk(49.5M)

BRANCH=none
BUG=chrome-os-partner:51537
TEST=emerge-kevin coreboot

Change-Id: I1c46ff17e6b466529244afb41d7fd4abbcfd3da4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9f0d31177336a3450577950426f9cc9d56e2254c
Original-Change-Id: I4ad00df3e406bd0a7576287d6e62b8993a8c2d02
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/332386
Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/14706
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09 08:41:21 +02:00
Vadim Bendebury b38895ea38 rockchip: rk3399: use static pointers to regs as they compile to faster code
Quoting an earlier review comment, using static structures pointers in
the include file "should allow the compiler to optimize accesses
better than defining it in a separate compilation unit (by being able
to constant fold stuff like &rk3399_pmusgrf->field into a single
address, rather than loading the symbol, loading an offset constant
and adding)".

Any decent compiler linker system nowadays would consolidate this
definition in any case.

BRANCH=none
BUG=chrome-os-partner:51537
TEST=with the rest of the patches applied Kevin successfully boots
     Linux kernel.

Change-Id: Ibb576c7691a30f2f429651fcca133bd72710c13b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 89b6f22e37f733667156f15afb8c27d8a9f07512
Original-Change-Id: Ice8d6d766a91e7f4fce553378a23b9ca593d12dd
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/339869
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/14705
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09 08:40:59 +02:00
Lin Huang f5702e70d6 rockchip: rk3399: add the GRF header file
The GRF(general register file) of rk3399 is divided into two sections,
o. GRF, used for general non-secure system
o. PMUGRF, used for always-on syosyem

This patch defines the registers used for iomux/gpio/system control.

BRANCH=none
BUG=none
TEST=emerge-kevin coreboot

Change-Id: I3239793523e0f55f6661ef029c3dac9970990fb8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 897d01573ea2bbe2b3091358ec3c9728ee82f8ec
Original-Change-Id: I4c228ddb60c9c4056de50312dc269227fac9a7fa
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/332388
Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/14704
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09 08:40:36 +02:00
Shunqian Zheng 2d3570adfc rockchip: rk3399: add simplest sdram to fix compiling error
This patch is only to make building happy, the real sdram driver
comes later.

BRANCH=none
BUG=none
TEST=emerge-kevin coreboot

Change-Id: I4123c3a6627d7264c615fefbb89e16c4dfb9a423
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5b992a7895a72c83f57228d3abd1ae37d55e7e7b
Original-Change-Id: Ie340877e828ae760169ccfa9a7099e7472d2fc26
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/338944
Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/14703
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09 08:40:17 +02:00
Daisuke Nojiri 212eb16795 google/veyron_romy: Increase RO CBFS size by 512 Kb
This change increases the size of RO CBFS by 512 Kb to accommodate new
images added to the INSERT screen.

BUG=chromium:602147
BRANCH=tot
TEST=emerge-veyron_romy chromeos-bootimage
CQ-DEPEND=CL:338152,CL:338027

Change-Id: I37cd0a9486f46d02cbc64af60336290fbbf486a8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4692cad8fc939202af2e3de709c2835a854e64b2
Original-Change-Id: I2f117247b2971a6f5576f60cdd53624ad6867e78
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/338095
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/14702
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09 08:39:21 +02:00
Patrick Georgi d3ae4f1364 rockchip/rk*: replace UART special snowflake with standard driver
The standard uart8250mem_32 driver is now usable on ARM, so use it.

BUG=none
BRANCH=none
TEST=see that serial firmware builds still log on serial in all stages
on veyron_minnie. Also verified that a 9600 baud console is functional.

Change-Id: I653b70a0d51a8d136e1da17537988f5b33c7a160
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fa27c60fd38002775072d11fca431d4788b4d1d7
Original-Change-Id: I047d74ac2d5c311f303955e62391114e16ec087a
Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/337551
Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/14319
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09 08:38:25 +02:00
henryc.chen 53e78539de soc/mediatek/mt8173: mt6391: vcore sleep voltage should be 0.7V
Vcore voltage should be 0.7V during system suspend. Because data sheet of mt6391
was not correct, need to config to 0x0 instead of 0x1.

QI_VCORE_VSLEEP
00: 0.7V
01: 0.6V
10: 0.65V
11: 0.75V

BUG=chrome-os-partner:52719
TEST=powerd_dbus_suspend

Change-Id: Ie504ebfb7cafae85bbba7919fce1578bbfbfafb7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cf15f5b63fac8968216772a8b37d2fe122414e24
Original-Change-Id: Ide53eca328c28007e2181497c888724c8a91ae93
Original-Signed-off-by: henryc.chen <henryc.chen@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/340540
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/14696
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09 08:36:57 +02:00
PH Hsu b7041a7ee2 google/oak: Add Samsung K4E6E304EB 4G LPDDR3 SDRAM for elm-rev1 SKU2
BUG=none
BRANCH=none
TEST=emerge-elm coreboot

Change-Id: Ib40076f2bb1516fe222e52e18592c15073c9d288
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 84d188543a9e949f7bf792ba704263a0bf97aa51
Original-Change-Id: I43ea6f07f5e337ca3bc5c5c4b3d56c89e5e0ca98
Original-Signed-off-by: PH Hsu <ph.hsu@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/338212
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/14695
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09 08:36:07 +02:00
Yidi Lin 1efc72affa google/oak: elm: Do not control SPI_LEVEL_ENABLE after elm-rev1
SPI level shifter is controlled by SRCLKENA0 after elm-rev1.
We don't need to configure it in the bootloader.

BUG=chrome-os-partner:51725
TEST=emerge-elm coreboot

Change-Id: I01ec00965b87ae370b72d3c0521fb37268714cf8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3234065e33c46bc2d67a96939422d318919d5e7a
Original-Change-Id: Iafed0cd7562eb5921af6b17f73a067d469143e02
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/337421
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/14694
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09 08:35:39 +02:00
Yidi Lin 374c50e876 google/oak: Configure MAINBOARD_PART_NUMBER by the board name
BRANCH=none
BUG=none
TEST=check CONFIG_MAINBOARD_PART_NUMBER value in the coreboot.config

Change-Id: Iefae44f4cd16d0e749f5b88d80ef6e5c23498c6d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 99b26f5a68054619c519c945172e56c10f353558
Original-Change-Id: I51c47d114049caf04ccb491096b39696e6af2ab3
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/339800
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/14693
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09 08:34:19 +02:00
Yidi Lin 19318ddab5 google/oak: elm: Update the differences between oak-rev6 and elm-rev0
- Remove the deprecated revison settings.
- Change LID pin to SPI_CK.
- Add i2c bus number and i2c slave address for elm.
- Skip the pin configurations(ALC5514 and USB OC pins) belonging to Oak.
- Add Hynix 4GB DRAM config

BRANCH=none
BUG=chrome-os-partner:51725
TEST=boot to kernel on elm-rev0

Change-Id: Ifaedd115c84d095ee289b576ff76af6b0aa3e545
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2ed4543cdc7e84a0463b73dda96027270ec30272
Original-Change-Id: Id957374d7a67b8c72df1d07a6cecc1064d4e0356
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/332733
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/14692
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09 08:33:29 +02:00
Julius Werner 9a57095bd2 google/oak: Add derivative board Elm
This patch adds a new mainboard Google/Elm as a derivative of
Google/Oak, using the same code sharing technique for derivative boards
that was pioneered with Google/Veyron*. For now, there are no
firmware-relevant fundamental differences between the two boards.

In addition, introduce a board-specific Kconfig for the "board ID
adjustment" to represent the fact that the Elm board ID space mirrors
the Oak board ID space with an offset of 6, meaning Elm rev0 is
equivalent to Oak rev6, and future board changes will be made on both
boards to maintain this stride (at least virtually... not all of those
revisions will necessarily get built). This should make it much easier
to keep the code that handles revision differences somewhat clean.
(That's the theory, anyway... whether it will work out remains to be
seen.)

BRANCH=None
BUG=None
TEST=Booted Elm image with hardcoded board ID 0 on Oak rev6.

Change-Id: If540aea862b746cf4986a74482ae1764c104fb73
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 53cd85c94945ab0bf14cb88a98e66723fc4483de
Original-Change-Id: Ib05fc81dc4f4308d99e34fce74c6db8b323785da
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/332276
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14691
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09 08:32:47 +02:00
Jitao Shi 8ea218b2cb google/oak: configure display
BRANCH=none
BUG=chrome-os-partner:43706
TEST=saw bootloader screen on rev4 and rev5

Change-Id: I844fed6f63467ad04d17115934a1e4724cc0b671
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2e9d57a42402631923c96e70bc2eff5c135de2fc
Original-Change-Id: I748b0eac9a0aab1d38d5d44a1a50dc33d5375379
Original-Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/331813
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/14690
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09 08:32:24 +02:00
Jitao Shi 4a04a7bf10 mediatek/mt8173: Add display driver
BRANCH=none
BUG=none
TEST=saw bootloader screen on rev4 and rev5 with CL:331813

Change-Id: Ibb01cf251276d2c059739f10e166fefd0de35460
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8d52a4c486b75b99dc25657ccb6ed90f671c26d6
Original-Change-Id: I4efe439d52b5a5516145960bcffb340152bfba53
Original-Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/331812
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/14689
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09 08:31:49 +02:00
Gwendal Grignou 866cc3d662 ec/google/chromeec/acpi: Add GOOG0004 to load cros_ec_lpc dynamically.
Add a GOOG0004 object that will be used to load cros_ec_lpc.

BUG=chromium:516122
BRANCH=none
TEST=Compile. Work in cyan branch.

Change-Id: Id8d9487ea6f376728eaa57728baceda7e5f6b2b9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6380104986d2740a14fc74161fec9f2994d2affc
Original-Change-Id: I682d68e0858327ec7c0fbd0924dd9f99527d4df0
Original-Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/342363
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/14686
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09 08:31:15 +02:00
Patrick Georgi 5dc87fe470 libpayload/arm64: Mark existing framebuffer as DMAable
If a framebuffer is already configured by coreboot, libpayload's
MMU tables didn't mark its memory DMAable (unlike when libpayload
set up its own framebuffer memory).

BRANCH=none
BUG=chrome-os-partner:52826
TEST=depthcharge's recovery screen is not corrupted anymore on kevin

Change-Id: I228a861b3fdcf1298a3cfa0a054214c78ed55e70
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 889e8358a0f2f504abd9910549aa68f3992bb4e8
Original-Change-Id: I7ba79151ccc1eb605f82e1869a74b539a6be5e99
Original-Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/341092
Reviewed-on: https://review.coreboot.org/14685
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09 08:30:56 +02:00
Varadarajan Narayanan 934c683933 spi: Add support for Winbond W25Q256
BUG=chrome-os-partner:49249
TEST=None. Initial code not sure if it will even compile
BRANCH=none

Change-Id: Ifde289ec004f5d54d5df32011c87e49470e2bb5d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 613b5ae45f7b8325863d8be492a451e6d076e293
Original-Change-Id: I93386e058a60b5c9b61d89607cf8c6e0de6a21ca
Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/334522
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://review.coreboot.org/14666
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09 08:30:22 +02:00
Varadarajan Narayanan 8e0ffe2088 libpayload: xhci: Set MPS based on speed
BUG=chrome-os-partner:49249
TEST=Compiles and boots and detect USB storage
BRANCH=none

Change-Id: I9007399e1f785e6f1d2258225e3f7cc602053aed
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1db43f53973d2124e41186777caa829aa346ace3
Original-Change-Id: I943d19a3a7d785bd075073b57ba6388662d7df90
Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/333311
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14659
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09 08:29:57 +02:00
Subrata Banik 9a8b67d0af soc/intel/skylake: Enable another VR mailbox command for certain boards
Command List:
Send command for PS4 exit fails

BUG=chrome-os-partner:52355
BRANCH=glados
TEST=Build and boot lars and verify no hang during active idle

CQ-DEPEND=CL:*257305

Change-Id: I9ffae71b1a38433ffc48ee7be7e2a13e69ad5b87
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 96f00e2d153f92339c378ce256eb7ce6824e3368
Original-Change-Id: I320ae154f3f7145811b57258ddb61b3beb584273
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/341330
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14688
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09 08:28:57 +02:00
Duncan Laurie e09b5f2d4f soc/intel/skylake: Output more ME status information
Output a few more status bits from HFS/HFS2 and add
some interesting bits from HFS3.

BUG=chrome-os-partner:52662
BRANCH=glados
TEST=boot on chell and verify ME status output

Change-Id: I989b680f203678dbe28559e858faf8b4e0837481
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8ea34ab019da3fff965102bcef5158ddcc154728
Original-Change-Id: Iff977c8d85b4d4dfa00b5b19bc29d11813a99b9f
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/340390
Original-Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-on: https://review.coreboot.org/14687
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@google.com>
2016-05-09 08:28:37 +02:00
Paul Kocialkowski d2ea674635 libpayload: Add nyan config
This adds a nyan libpayload config, that should fit all nyan devices.

Change-Id: I6b86a03054a7625534fd38ee6a21d3b91fb43589
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/14473
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09 07:49:57 +02:00
Paul Kocialkowski 8957dd6b52 tegra124: Align the framebuffer's bytes-per-line to 32
It turns out that tegra124 needs the framebuffer's bytes-per-line to be
aligned to 32 for proper display. This behaviour was default before
moving to edid_set_framebuffer_bits_per_pixel.

This fixes display on nyan_big.

Change-Id: Ie81b395fca23f3648ea7cd1df51152faea864c9a
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/14564
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09 07:49:05 +02:00
Paul Kocialkowski 0dcd41739f tegra132, tegra210: Align the framebuffer's bytes-per-line to 64
It turns out that tegra132 and tegra 210 need the framebuffer's
bytes-per-line to be aligned to 64 for proper display. This behaviour
was default before moving to edid_set_framebuffer_bits_per_pixel.

Change-Id: I46dadcf36e1c50e9649121ee6fa9cdf6134a531e
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/14734
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09 07:48:56 +02:00
Paul Kocialkowski 536f5a7eb9 tegra132, tegra210: Fix "becasue" typo in comments
This renames "becasue" occurrences to "because".

Change-Id: I7862ce6a865cb1525ca1cef69c2eb1e90cc76a9d
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/14735
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-05-09 07:45:18 +02:00
Patrick Georgi 30554c8416 3rdparty/arm-trusted-firmware: update to current master
It includes support for rk3399.

Change-Id: I326ef3dc3021313ee852395c302c076b3e3c8c5e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14732
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09 06:50:07 +02:00
Varadarajan Narayanan 0067a426e7 arch/armv7: Fix end index calculation in mmu_config_range_kb
BUG=chrome-os-partner:49249
TEST=None. Initial code not sure if it will even compile
BRANCH=none

Change-Id: Ib0fccfe2d103710c006cb3950c65b11b8d596912
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9be5f58bb89ec43d4eb264c94c3f745dcade35dd
Original-Change-Id: If50efb55d4974dfcab07d3ae6488c2413b505a1f
Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/333301
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/14657
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins)
2016-05-09 06:44:32 +02:00
Paul Menzel e8e219d63d siemens/mc_tcu3: Fix spelling of *set up*
The verb *set up* is written with a space [1]. So correct that in the
function descriptions.

[1] http://www.merriam-webster.com/dictionary/set%20up

Change-Id: Icf5aa7eca2c379fdf7ff1935d71efc347f5ce6fa
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/14701
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09 05:30:48 +02:00
Paul Menzel 7bb37ef068 siemens/mc_tcu3: Add blank lines for better legibility
Change-Id: I6d1200dd59e53ca892594c1fce784639a9817550
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/14700
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09 05:30:05 +02:00
Paul Menzel 7802119005 siemens/mc_tcu3: Remove unneeded variable assignment
Assigning the value `1` to `status` in the default branch of the switch
statement is not needed, as the stored value is overwritten before it
can be used.

Change-Id: I532b0e217ff4ed315cd30b08d339c755c6df7539
Found-by: Coverity, CID 1355008: Code maintainability issues (UNUSED_VALUE))
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/14699
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09 05:28:12 +02:00
Furquan Shaikh 1e162bf8bd lib/prog_loaders: Allow platforms to skip stage cache
Before multi-CBFS support was added, x86 platforms cached their
ramstage in TSEG so that it could be re-used on the resume
path. However, more resources/assets are being put in cbfs that are
utilized during ramstage. Just caching ramstage does not mean that
correct cbfs region is used for all the data. Thus, provide an option
to allow platforms to skip caching any component for resume.

Change-Id: I0e957a6b859cc7d700aaff67209a17c6558be5de
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/14636
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-05-09 05:02:22 +02:00
Furquan Shaikh 94b18a1757 xip: Do not pass --xip for early stages if CAR supports code execution
On modern x86 platforms like apollolake, pre-RAM stages verstage and
romstage run within the cache-as-ram region. Thus, we do not need to
pass in the --xip parameter to cbfstool while adding these
stages. Introduce a new Kconfig variable NO_XIP_EARLY_STAGES which is
default false for all x86 platforms. Apollolake selects this option
since it supports code execution with CAR.

Change-Id: I2848046472f40f09ce7fc230c258b0389851b2ea
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/14623
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-09 05:01:58 +02:00
Stefan Reinauer 2e78aa5a78 util/sconfig: Fix warnings
and re-generate _shipped files

Change-Id: I7a18824d64d3f6212e8566695376bf97e2196ee2
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14733
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2016-05-08 21:37:36 +02:00
Stefan Reinauer 66fbeaec98 intel/pineview: Don't try to store 34 bits in 32
Mask out the bit that doesn't fit in 32bits, so gcc 6.1 is happy

Change-Id: I13e2b41742206b8d86b90314b80cc324c00ae637
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14639
Reviewed-by: Damien Zammit <damien@zamaudio.com>
Tested-by: build bot (Jenkins)
2016-05-08 21:36:32 +02:00
Patrick Georgi 2a6f251f4d parade/ps8640: Initialize edid_size
decode_edid either gets EDID_LENGTH bytes or (in the extended case),
2*EDID_LENGTH.
See that this is reflected in its size argument.

Change-Id: If6c76358db4e9ee01c2bd2dbdd5948c61b7aa5bc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14698
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-08 08:11:26 +02:00
David Hendricks 292be87205 board_status: Allow for parsing longopts
This converts the argument parsing to allow us to add longopts
using GNU getopt(1).

Shortopts should be reserved for general parameters. Longopts can be
used to tweak specific behaviors. For example, we might wish to add
options to set SSH port, timeout, and authentication parameters
with "--ssh-port", "--ssh-timeout", "--ssh-identity", etc.

Change-Id: Idee5579079dbbb7296ad98f5d6025b01aab55452
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://review.coreboot.org/14523
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2016-05-07 03:15:12 +02:00
Stefan Reinauer fe0609dc3e google/foster: Configure audio codec pads
Otherwise, newer GCCs will insist that they get deleted.

Change-Id: Ida45b7d193366f5e611a32632ba610193451b082
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14619
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-07 00:40:46 +02:00
Stefan Reinauer 617536e580 amd/gx2 + amd/lx: Fix shift overflow issue
gcc 6.1 complains that SMM_OFFSET << 8 is larger than the register
it is assigned to (rightly so):

src/northbridge/amd/gx2/northbridgeinit.c:196:23: error: result of
    '1077936128 << 8' requires 40 bits to represent, but 'int' only
    has 32 bits [-Werror=shift-overflow=]
  msr.lo = (SMM_OFFSET << 8) & 0xfff00000;
                       ^~

Change-Id: Ib0d669268202d222574abee335a6a65c8a255cc7
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14617
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-06 19:04:51 +02:00
Stefan Reinauer 24850ccf9b rtc: Do checksum check for all bytes
Due to missing braces (that went undetected because of the
indentation), I584189d9fcf7c9b831d9c020ee7ed59bb5ae08e8
CMOS: add set_option() only takes the last changed byte into regard
when determining whether the checksum needs to be updated.

This bug went undetected for 5 years.

Change-Id: I47cedc801a60959386dfdcda3a13b8e3162a7ecb
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14616
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-06 19:03:41 +02:00
Andrey Petrov d5a6eb44ca drivers/intel/fsp2_0: Update to FSP draft 9
Recent FSP draft slightly changed FSP_INFO_HEADER structure. This
change keeps FSP driver code in sync with header changes.

Change-Id: I3536f766a312b9eb73ab8940d91dc9b9dfa347f1
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14614
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-06 19:00:23 +02:00
Alexandru Gagniuc 851ef96f4e ec/google/chromeec/ec_lpc: Declare used IO ports as a resource
Chrome EC uses IO ports 0x800 -> 0x9ff to communicate over LPC;
however, those ports were not declared as a resource. This had two
major downsides:
* It allowed the allocator to assign said ports to other devices
* It required manually open up an IO window in the LPC bridge.
The LPC bridge on many chromeec boards had to be painstakingly
adjusted to meet these constraints.

The advantage of declaring the resources upfront is that the lpc
bridge can now scan its child resources and automatically open up
IO windows, as requested by its LPC children devices.

Change-Id: I35c4e48dddb7300674d7a9858b590c1f20e3b0e3
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Reviewed-on: https://review.coreboot.org/14585
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-05-06 18:59:00 +02:00