Commit graph

460 commits

Author SHA1 Message Date
Kyösti Mälkki
e405c27294 lenovo/pmh7: Remove use of __PRE_RAM__ and __SMM__
Change-Id: Ib74c5c8cb9197fa06b2972cb96337fedd7f85b5b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-08-20 08:41:33 +00:00
Kyösti Mälkki
cd2aa47a34 devicetree: Remove duplicate chip_ops declarations
These are only referenced inside auto-generated static.c
files, and util/sconfig also generates the declarations
automatically from source file pathnames.

Change-Id: Id324790755095c36fbeb73a4d8f9d01cdf6409cb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34979
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-20 01:31:44 +00:00
Kyösti Mälkki
b93f86601c ec/google/chromeec: Use MAYBE_STATIC
Change-Id: I4c6238b0e5f41fcc667baf6b486c7fff4c90a7cb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34944
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-19 00:04:55 +00:00
Elyes HAOUAS
77f778c0c3 ec/google/wilco: Hide wilco symbols when unused
This cleans up .config file from unused wilco symbols.

Change-Id: I813d3fe57b97e2c1ba67e1e3674de256c2529029
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34539
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-25 16:46:17 +00:00
Duncan Laurie
cacecefb27 ec/google/chromeec: Pass reference of object to BBST() method
The BBST() method writes an updated status flag mask that is intended
to be stored back in the battery object.  This value needs to be
passed as a reference to an object to prevent it from being evaluated
at the time the method is loaded or it will not actually update the
BSTP value in the battery device.

This was tested by instrumenting the _BST method in the primary
battery and ensuring the value can be updated by the BBST method.

Change-Id: Ia8e207a2990059a60d96d8e0f3ed3c16a55c50f4
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-18 16:24:44 +00:00
Kyösti Mälkki
9265f89f4e arch/x86: Avoid HAVE_SMI_HANDLER conditional with smm-class
Build of the entire smm-class is skipped if we have
HAVE_SMI_HANDLER=n.

Change-Id: I10b4300ddd18b1673c404b45fd9642488ab3186c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34125
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-09 12:43:35 +00:00
Elyes HAOUAS
b874ef4925 src/ec: Use 'include <stdlib.h>' when appropriate
Change-Id: Ifdb2dee08da45d698174583ee5ed44bf5a0243ff
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-06-22 17:54:31 +00:00
Elyes HAOUAS
1ba0da17c8 ec/kontron/kempld/kempld_i2c.c: Remove unneeded 'else'
'else' is not needed after a 'break' or 'return'.

Change-Id: I0843bebe48e4b91fc76c440ae33bbca838621de9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Vlado Cibic
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-06-21 08:32:32 +00:00
Elyes HAOUAS
b53427156c ec/google/chromeec/ec_lpc: Remove unneeded 'else'
'else' is not needed after a 'break' or 'return'.

Change-Id: I98d0ab0d139186b312e8c1086c475ba6ef0b7d3b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-06-21 08:32:08 +00:00
Duncan Laurie
6ff848aaf8 ec/google/wilco: Read back from EC RAM after S0ix entry
We are seeing an EC interrupt after setting the EC RAM offset that
indicates that the EC should transition to S0ix mode and this is
preventing the kernel from going into S0ix on the first try.

As a workaround if we read back from the EC RAM while still in the
_DSM handler it seems to prevent this problem.

BUG=b:130644677
BRANCH=sarien
TEST=ensure s0ix entry works on the first try with sarien

Change-Id: Id607c4c2b14b79d0cd1bcea0c2032be2f2c0c141
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33455
Reviewed-by: Shaunak Saha <shaunak.saha@intel.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-13 21:14:08 +00:00
Duncan Laurie
c145e54f69 ec/google/wilco: Add UCSI support
This change adds support for the UCSI specification in order to
provide information about the Type-C port and an interface to
perform power and data role swap.

This change is split across the DSDT and SSDT, with the shared
memory and operation region declared in the SSDT after being
allocated in CBMEM.

The OS will fill in the registers in the system memory region and
then call the _DSM method wtih a read or write argument.  The DSM
method will copy the required registers to/from the system memory
and the EC and perform the write or read action.

Responses from the EC will generate a new SCI with event code 0x79
which will notify this UCSI ACPI device and the OS driver will take
action to read status from the EC.

BUG=b:131083691

Change-Id: I438a2bdfaf6720acd8354e0339dcef2844b63a4e
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-06-07 20:51:16 +00:00
Evgeny Zinoviev
60a0a3d629 ec/lenovo/h8: Fix method name in ACPI code
Fix a typo.

Change-Id: I2ab624eccd9bad36908df7fd739828e9ed8a4f62
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-06-03 10:10:21 +00:00
Elyes HAOUAS
5fd93e0582 src/{ec,vendorcode}: Add missing 'include <types.h>
<types.h> is supposed to provide <stdint.h> and <stddef.h>.
So when <types.h> is included, <stdint.h> and/or <stddef.h> is removed.

Change-Id: I1eb4163fb36a47b584f1fc9dd3c012e2930e9866
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-05-29 20:28:07 +00:00
Duncan Laurie
35f9507b08 ec/google/wilco: Fix radio control command
This command is working as written, but it is not actually correct
as to what the format of the command should be.  Fix this and add
define the other radios.  There is no change in the command send to
the EC.

Change-Id: Ia551b08561b673d27bec2f900d97b746699b30c4
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2019-05-24 16:43:57 +00:00
Keith Short
f41afde6c2 ec/google/wilco: set diagnostic LEDs on boot failure
On Wilco devices, if any of the coreboot stages fails with a fatal
error, set the diagnostic LEDs with the Wilco EC.  The last saved
post code is used to determine the error code sent to the EC.

BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms
TEST=Remove DIMM module, confirm diagnostic LED pattern for memory
failure (2 amber, 4 white).
TEST=Forced a fatal error in both bootblock and verstage to confirm
diagnostic LEDs during these stages. This works on cold-boots only. Bug
b:132622888 tracks the mailbox failures on warm boots.

Change-Id: If865ab8203f89e499130f4677fec166b40d80174
Signed-off-by: Keith Short <keithshort@chromium.org>
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-05-22 20:01:25 +00:00
Keith Short
8ef6732b94 ec/google/wilco: Add support for KB_ERR_CODE to Wilco EC
Adds support for the KB_ERR_CODE command on the Wilco EC. This command
is used to drive diagnostic LEDs on the platform after a failed boot.
This change also adds the Wilco EC mailbox command support to bootblock
and verstage so that those stages can use the KB_ERR_CODE command.

BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms

Change-Id: I96d17baf57694e4e01c676d80c606f67054cd0c3
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32776
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-20 14:48:10 +00:00
Elyes HAOUAS
60ab1d8c52 src/ec/lenovo/h8/acpi: Serialize Control Method
IASL reports warning 'Control Method should be made Serialized'.

Change-Id: I034f2c00e912e8f9ef87b9918de1db06fade38b9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-13 09:26:58 +00:00
Patrick Rudolph
2521211753 ec/lenovo/h8: Add VBOOT board support
Use Fn-Key as recovery mode switch.

Tested using Icb7b263ed86551cc53e1db7babccaca6b3ae2fe6.

Change-Id: I2c682431b3f09839db265259205104bd9ef4abfc
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-05-08 10:27:36 +00:00
Patrick Rudolph
2dc00fab7c ec/lenovo/h8: Add function to query sense state
* Add function to wait for sense registers to become valid.
* Add function to retrieve Fn-Key state.

Tested on Lenovo T500:
* It takes about 700msec for the registers to become valid.

Tested on Lenovo T520:
* It takes less than 150msec for the registers to become valid.

Change-Id: Ie27e2881a256c4efb3def11f05070c446db6e5fc
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29204
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-08 10:26:35 +00:00
Duncan Laurie
b34de93153 ec/google/wilco: Support board_id with EC provided ID
The EC can return a board ID value similar to the Chrome EC.
In order to use this for the board version returned by SMBIOS
this commit implements the board_id() function for mainboards
that use this EC.

BUG=b:123261132
TEST=Check /sys/class/dmi/id/board_version to see that it
is reflecting the value that the EC provides.

Change-Id: I3fbe0dc886701f37d2424fe7a2867fd860fa1ec0
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32276
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-18 23:43:06 +00:00
Duncan Laurie
1c968c135c ec/google/wilco: Send "logo displayed" progress code
This progress code enables keyboard backlight control that
otherwise would only work 30 seconds after boot.  This code
is already defined but it was not being sent by coreboot.
It is run in the "post device" step between the other defined
progress codes.

BUG=b:130754032

Change-Id: Ica6c622e568cb236c17bf3edb6639d0177510846
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-04-18 23:42:26 +00:00
Elyes HAOUAS
bf0970e762 src: Use include <delay.h> when appropriate
Change-Id: I23bc0191ca8fcd88364e5c08be7c90195019e399
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: David Guckian
2019-04-06 16:09:12 +00:00
Elyes HAOUAS
eb789f0b79 src: Use include <reset.h> when appropriate
Change-Id: I3b852cae4ef84d257bf1e5486447583bdd16b441
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29301
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-29 20:00:20 +00:00
Duncan Laurie
0f57a2bb97 ec/google/wilco: Add ACPI _BIX method for battery
I added a method to fill out the _BIX package structure but never
hooked it up to the expected _BIX method that the OS uses.

This change adds _BIX method and uses the existing method to fill
it out.  It also adds ^ before the _UID in _BIF to match _BIX as
the _UID is one level above the method.

Change-Id: I0de91369b6780fd9432990732c1078a73f6a3419
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-03-28 19:18:05 +00:00
Duncan Laurie
31354676d0 ec/google/wilco: Add a romstage init function to send progress code
When using FSP with debug enabled it takes too long to get to ramstage
and send the first progress code to the EC.  The same thing has been
reported to happen when 2x16GB memory is installed.

BUG=b:127875364
TEST=boot with FSP debug and ensure EC does not try to turn off the
system while it is still booting.

Change-Id: I5676354f5e53540273a9029411507f91864735a1
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-03-28 19:17:43 +00:00
Duncan Laurie
5a38572fd9 Revert "UPSTREAM: ec/google/wilco: Enable software sync for VBOOT"
This reverts commit 51169b7dda4a1978d622e329a1c40e384471c165.

I was not ready to enable this option yet, until it is enabled
in depthcharge it needs to stay off in coreboot or depthcharge
will attempt to do software sync without a proper driver.

Change-Id: I4840812d0541f822502cfc5c66bed27edf4d2ecc
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32007
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-21 03:43:18 +00:00
Duncan Laurie
32346f0aa2 ec/google/wilco: Add function to indicate if EC uses signed FW
This will be used to distinguish the mainboard SKU so that the
correct EC firmware can be bundled with the board.

This is read from EC RAM so it can be used by an ACPI method in
the future.

BUG=b:119490232

Change-Id: I71b8017fc4b88e793dfe709e1cb1ab0f0bcdc4fa
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-21 03:42:57 +00:00
Duncan Laurie
19a37d6420 ec/google/wilco: Enable software sync for VBOOT
Enable software sync by default if VBOOT is enabled.
The slow update option is also needed, but this is moving
to depthcharge so it is not defined here.

Change-Id: I046661fae7315f84e96293532b4e1568558df962
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31920
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-18 09:14:43 +00:00
Duncan Laurie
a436877573 ec/google/wilco: Fix handling of commands that do not respond
If the command does not respond the driver should not wait for
it to complete before returning.

Tested with SMI debug enabled to ensure that the final command
does not report a failure.

Change-Id: I7c1bfa19a92e8332ac1aa6ff95f94ff4cbdf789d
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31919
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-18 09:14:36 +00:00
Elyes HAOUAS
74aa99a543 src: Drop unused '#include <halt.h>'
Change-Id: Ie7afe77053a21bcf6a1bf314570f897d1791a620
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-03-16 11:46:58 +00:00
Duncan Laurie
90a96c77a9 ec/google/wilco: Clear S0ix support bit at boot
To ensure the power button functions as expected in firmware ensure
that the EC is not in "S0ix supported OS" mode and expecting the
power button to be handled by the virtual button interface.

BUG=b:128409889
TEST=Verify that the power button works at the developer screen
when the system is rebooted from within Chrome OS.  Also ensure
that it works when external warm reset signal is asserted by H1.

Change-Id: Ic323515e3b8be08bac4f0f82e25f2f78c2f22833
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-15 15:31:59 +00:00
Jett Rink
a29d866f1c ec/google/wilco: coalesce tent mode to tablet mode
Both tent mode (0x01) and tablet mode (0x02) should be considered tablet
mode by ChromeOS.

BRANCH=none
BUG=b:122052438
TEST=ChromeOS enters tablet mode when lid angle exceeds 180

Change-Id: I89ba8141350fc628c8cff89d5f33aa47c6ae6afe
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-15 13:12:52 +00:00
Julius Werner
cd49cce7b7 coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
This patch is a raw application of

 find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'

Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-08 08:33:24 +00:00
Alexey Kharlamov
93d6ba0889 ec/lenovo/h8: Implement ACPI methods to set battery thresholds
There are two known reverse-engineered ways to manage battery
thresholds.
This patch implements them and adds a way to enable them for
different mainboards.

Tested on W530 with 4.18.3-gentoo kernel and X220 with 4.20.11.
Works fine with new Linux userspace API for controlling battery
thresholds, available since 4.17.
(/sys/class/power_supply/BAT0/charge_(start|stop)_threshold).

The new API is supported by TLP (you might need to set NATACPI_ENABLE=1
in /etc/tlp.conf).

tpacpi-bat works fine too.

Signed-off-by: Alexey Kharlamov <der@2-47.ru>
Signed-off-by: Evgeny Zinoviev <me@ch1p.com>

Change-Id: I2a90f9e9b32462b8a5e9bc8d3087ae0fea563ea5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/23178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-03-06 20:00:00 +00:00
Kyösti Mälkki
3855c01e0a device/pnp: Add header files for PNP ops
Change-Id: Ifda495420cfb121ad32920bb9f1cbdeef41f6d3a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31698
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-04 15:58:55 +00:00
Kyösti Mälkki
3695593794 Fix indirect include for endianess
The function (preprocessor macro) we need is defined
in <endian.h> not <swab.h>.

Change-Id: I3a86c7050bf853e3a56a15421132240e19f40912
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31704
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-04 15:58:16 +00:00
Kyösti Mälkki
065857ee7f arch/io.h: Drop unnecessary include
Change-Id: I91158452680586ac676ea11c8589062880a31f91
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31692
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-04 15:08:03 +00:00
YH Lin
40f65425e4 ec/google/chromeec: fix the error status passing
Various instances of google_chromeec_command() can return non-zero number
(both positive and negative) to indicate error -- fixing cbi_get_uint32()
and cbi_get_string() so they follow the same convention.

BUG=b:123676982
BRANCH=kukui
TEST=build with kukui/flapjack configurations
Signed-off-by: YH Lin <yueherngl@google.com>
Change-Id: I7f0a8a61d01d942cba57036a17dd527fdbbf940c
Reviewed-on: https://review.coreboot.org/c/31585
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-27 11:08:18 +00:00
Daisuke Nojiri
7bbed26ca9 ec/google/chromeec: Clarify return value of google_chromeec_command
This patch clarifies the definition of google_chromeec_command.

Currently absence of the definition isn't causing any problem because
wrapper APIs check 'ret != 0' or wrapper APIs check 'ret < 0' for an
interface which returns only negative error codes.

However, there is a chance that a new wrapper API will be addedl which
check 'ret < 0' to catch errors, assuming other interfaces behave the same.
Or existing wrapper APIs will be broken as soon as they're compiled for
another interface.

BUG=chromium:935038
TEST=none

Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: I2ce7109b5f2a1d5294f167719730bc1f039ba03f
Reviewed-on: https://review.coreboot.org/c/31613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-02-26 11:19:14 +00:00
Duncan Laurie
a213ed659a ec/google/wilco: Fix ACPI power status events
This change fixes the power status events for AC and battery
events from the EC.  The register that was being used is not
returning the expected information.

BUG=b:125472740
TEST=enable ACPI debug in the kernel and verify that AC and
battery insert/remove are detected properly.

Change-Id: I15f71fcf0ca6aa9438e951865787c9fc273792d8
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-25 11:17:23 +00:00
Michael Bacarella
8ab1752070 ec/lenovo/h8/Kconfig: increase ps2 kbd timeout from 3000 to 5000ms
On my Thinkpad T420 the default 3000ms SeaBIOS timeout is too short,
it takes nearly 5000ms for my keyboard to become ready.

Timing out before it's ready leads to pretty bad behavior: I cannot use
my keyboard at all to control SeaBIOS, nor the subsequent GRUB instance.
Linux is fine though, possibly because it does its own keyboard init.

Signed-off-by: Michael Bacarella <michael.bacarella@gmail.com>
Change-Id: Id1681bf3921c8b5dc124d4c4e9072f146f84f3a2
Reviewed-on: https://review.coreboot.org/c/31279
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-11 12:24:22 +00:00
Edward Hill
f14445c145 mb/google/kahlee: Use GPIO_10 for EC_SYNC_IRQ
Use AGPIO 10 as the EC sync interrupt for MKBP events for sensor data.

On this platform, interrupts are routed via the GPIO controller so need to be
registered using GpioInt instead of Interrupt.

BUG=b:123750725
BRANCH=grunt
TEST=MKBP events still received (with matching EC and kernel changes)

Change-Id: If499d24511bbaa7054207b7e0b98445723332c4f
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Enrico Granata <egranata@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-02-11 12:23:05 +00:00
Duncan Laurie
4a2558b6d8 ec/google/wilco: Add virtual button support
Add an ACPI device that is compatible with the Intel Virtual
Button kernel driver for reporting tablet mode state and various
virtual button events that may come from the EC.

This driver is used in Windows and in the Linux kernel at
drivers/platform/x86/intel-vbtn.c

Because of a check in the kernel driver it expects the board to
define the SMBIOS enclosure type as convertible for the check at
driver load time for tablet/laptop and dock/undock to work.

The virtual tablet mode button will proxy the tablet mode state
sent from the Sensor Hub to a SW_TABLET_MODE event in the kernel.

The virtual power button is used during S0ix for the EC to wake
the system with an SCI.  There are separate press and release
events which are sent for completeness, although the kernel driver
will ignore the release event.

BUG=b:73137291
TEST=Test that the power button can wake the system from S0ix.
Also verify that the device is reported as laptop mode at boot.

Change-Id: I0d5dc985a3cfb1d01ff164c4e67f17e6b1cdd619
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31208
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-05 16:03:37 +00:00
Duncan Laurie
aaac678e80 ec/google/wilco: Add ACPI device for event interface
Add a separate ACPI device for the Wilco EC event interface so that the
OS drivers can bind to it separately.  Since the event handling is all
done with ACPI and not mailbox calls this will be implemented as a
standard acpi_driver in the kernel.

BUG=b:119046283
TEST=veriy device exists in DSDT

Change-Id: I5259a926fb6d5faea835bcdefa12f0184c5adf4a
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31204
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-04 19:21:01 +00:00
Duncan Laurie
286a0ab143 ec/google/wilco: Add S0ix support handlers
1) In the EC _REG method set the flag indicating S0ix support in the OS.

2) Add a function that can be called by the LPI _DSM method to indicate
to the EC that the OS is entering or exiting S0ix.

BUG=b:73137291

Change-Id: Iddc33a08542a6657694c47a9fda1b02dd39d89f7
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31094
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Shaunak Saha <shaunak.saha@intel.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-04 19:20:40 +00:00
You-Cheng Syu
76c7688f63 ec/google/chromeec: Add boardid.c to verstage
Modifiy Makefile so that we can get board ID in verstage.

BRANCH=none
BUG=b:117916698
TEST=manually

Change-Id: Idcdb6e07f565c937185cab811abac0ce47e5e3a7
Signed-off-by: You-Cheng Syu <youcheng@google.com>
Reviewed-on: https://review.coreboot.org/c/31006
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-01-30 11:02:18 +00:00
Lijian Zhao
a31872c615 ec/google/wilco: Turn on wake up from lid
Send required EC command to enable ACPI S3 wake up from lid switch.

BUG=b:120748824
TEST=Put Sarien system into S3 and then wake up from lid switch
successful.

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I13f3469847b0886147b8b624311a1ece796f847b
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/30824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-01-24 22:03:32 +00:00
Nico Huber
016ef9e9bc ec/kontron: Add support for Kontron kempld
A programmable logic device used by Kontron as EC on their COM express
modules. The name `kempld` is taken from Linux kernel sources, as is the
I2C driver. The meaning of the acronym is unclear, probably: Kontron
Embedded Module PLD.

Change-Id: If9a0826c4a8f5c8cd573610c2d10561334258b36
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/29476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-01-24 13:56:25 +00:00
Matt DeVillier
680ed1f632 ec/chromeec: fix LPC read/write for MEC devices
Commit 8cf8aa2 [ec/google/chromeec: Use common MEC interface]
changed the return mechanism for the checksum on reads/writes
for MEC devices, but incorrectly handled the passed-in csum
parameter by not dereferencing. This led to the returned csum
value always being zero, which causes all EC commands with non-
NULL data_in to fail with a checksum error.

Fix this by storing the returned checksum in a temp variable,
and only assigning to csum when the pointer isn't NULL;

Test: build/boot google/chell, verify EC hello command succeeds,
keyboard backlight turned on at boot.

Change-Id: I7122c3fdc5a19f87f12975ee448728cf29948436
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-12-28 12:24:52 +00:00
Nathaniel Roach
4f4322dd68 lenovo/h8,thinkpads: Re-do USB Always On
Re-write the UAO handling code as it had stopped working (#171)
  (the flag was not getting read from the RTC properly in SMM)

Remove the SMM code as it's not needed (but EC flag won't be set
  upon entering S3 now)
Set the EC flags on boot the same way other flags are set
Document bitwise operators for clarity
Propagate changes to other Thinkpads
  (updated X201 to have 2 bits for the flag as it only had 1)

Per Nicola Corna's previous commits, 0x0d is set for "AC only"
  "AC only" does exhibit different behaviour - the USB port is
  turned on a few seconds after entering S3, rather than < 1 sec,
  regardless of AC status

Tested on X220

Change-Id: If812cd1ef8fb1a24d7fadbe834f574b40cbcd56a
Signed-off-by: Nathaniel Roach <nroach44@gmail.com>
Reviewed-on: https://review.coreboot.org/c/29565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-12-06 11:59:22 +00:00