This is a temporary workaround for a bug that breaks graphics due to
some power management issue.
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie4c8ff8e827901112fd8b2e993898006bc133241
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52141
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
pcie_rst isn't working correctly, so use the AUX resets to reset the
PCIe devices before training.
BUG=b:182202136
TEST=See PCIe devices train & enumerate
Change-Id: I6db21c79dcbd40c7a8c3f01c60b02882a3851278
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This patch adds the functionality to write the DXIO and DDI descriptors
to the UPD data structure to the SoC code and adds the
mainboard_get_dxio_ddi_descriptors function to each mainboard using the
Cezanne SoC that gets called to get the descriptors from the board code.
Change-Id: I1cb36addcf0202cd56ce99e610a13d6d230bc981
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51948
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
GPIOs should be configured in ramstage even if they are configured in an
earlier stage.
BUG=b:182211161
TEST=builds
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I07d5c46d6ea6dc2bc9ab265d0c01772d653884cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
On VCCin there was an oscillation which occurred just as the kernel
started (kernel starting... message). On some devices, this behavior
seems even worse. In previous platforms VCCin toggled for a few ms
and then was stable. For volteer, this happens at the same point in
time for around 40ms. However, it starts oscillating again later in
the boot sequence. Once at the root shell, it seems to oscillate
indefinitely at around 100-200Hz (very variable though). To fix this
we need to control the deep C-state voltage slew rate.We have options
for controlling the deep C-state voltage slew rate through FSP UPDs.
This patch expose the following FSP UPD interface into coreboot:
- AcousticNoiseMitigation
- FastPkgCRampDisable
- SlowSlewRate
We are setting SlowSlewRate for all volteer boards to 2 which is Fast/8.
TGL has a single VR domain(Vccin). Hence, the chip config is updated to
allow mainboards to set a single value instead of an array and FSP UPDs
are accordingly set.
BUG=b:153015585
BRANCH=firmware-volteer-13672.B
TEST= Measure the change in noise level by changing the UPD values.
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Change-Id: Ica7f1f29995df33bdebb1fd55169cdb36f329ff8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This reverts commit 52e6194558.
Reason for revert: Graphics actually works now. I should have abandoned this CL.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I83aac3a2c616bb434706f23e36549760bc764080
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
TPM_INIT is disabled by default. This prevents TPM to be operational
when VBOOT is disabled.
Remove the TPM_INIT disable.
BUG=N/A
TEST=tested on facebook monolith with VBOOT disabled.
Change-Id: I84d525a18c84643903922fef0a11dcf98abbbe4d
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Make sure the standard for the board options are set when VBOOT is
enabled.
BUG=N/A
TEST=tested on facebook monolith
Change-Id: I9749eeeffbd26e7c5caaeb7c0407a765cf093337
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52053
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Enable Bayhub SD card reader power-saving mode for Lindar and Lillipup.
BUG=b:173676531
TEST=Boot to OS and test with SD card function.
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I923d6e1beacd007c0e501f39c1f434c3e1085b9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This changes updates the iDisp-Link T-mode to 8T required for ADL-M.
The update is made because the HW on ADL now supports 8T mode.
BUG=None
TEST= build and boot ADL-M RVP and verify HDMI/DP audio playback.
Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com>
Change-Id: I9d0bf7dc76348f7e184e8496f042badc30bf3211
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51353
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
1. Configure Power Enable, Reset and Clock GPIO for both camera
2. Use same ASL code as ADL-P RVP
Configure RST, PWR_EN and IMGCLKOUT signals for WFC and UFC
TEST=Build, Boot and Verify streaming in both Camera
Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com>
Change-Id: I70636eaa8d9bdf23d649e811b3ff4f33b1bc604e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50265
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Config ANX7625 line data end same time on all line.
BUG=b:173603645
BRANCH=kukui
TEST=Display is normal on Kukui
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Change-Id: Ia1dc217138a98a79ef2f31225b52ba2b1aaf8672
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Just do it already.
The two SCSI-specific options for p2b-{ls,ds} will be wired up in a
followup. They will be ignored by boards without the hardware.
Change-Id: Ia43d502219d7c23d21f49d651113e3d653c6e9f4
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This is locking up the OS. For now this will unblock booting.
BUG=b:183971103
TEST=Boot guybrush to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Id2b96eedf38c9038169407418c6d36f13299fb62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
The define for color keyboard setting has never been used, as it was
added as a Kconfig selection when ec/system76/ec was introduced.
Change-Id: Iec9134e226382d32783342ef1d37c6f6f6caeb6e
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The define for color keyboard setting has never been used, as it was
added as a Kconfig selection when ec/system76/ec was introduced.
Change-Id: I6c8f17b398fb4645feb830c2ad28ac98fb744280
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The define for color keyboard setting has never been used, as it was
added as a Kconfig selection when ec/system76/ec was introduced.
Change-Id: Ib83d4510c14ddf083660e42175ab093403792cac
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Current get panel_id is over sku_id() >> 4, but sku_id is combined with
wfc_id/lcm_id/sku_id, so the panel_id value is wfc_id << 4 | lcm_id()
in fact. When wfc_id is not 0, the panel_id will be wrong. So only get
the low 4 bits for the panel_id.
BUG=b:183779755
BRANCH=kukui
TEST=emerge-kukui
Change-Id: I63e0c8a2719462a9b979afe52a27c78b9fc804e8
Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The EDID and initial code are provided by STA (the vendor).
BUG=b:183969078
TEST=Boots on Chromebook Katsu and displayed developer firmware screen
successfully.
Signed-off-by: Sunway <lisunwei@huaqin.corp-partner.google.com>
Change-Id: I54e72c072b47d2be264ed7f0700812a6c704a104
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51918
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
All known on-chip PCI devices are disabled in the chipset devicetree.
So they are removed from the mainboard devicetree.
BUG=N/A
TEST=tested on facebook monolith
Change-Id: Ie67cd8afc9ea92e9fd7caed4338cb25a68d94cb1
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52018
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
The romstage does not fit in RO_SECTION.
Increase the CBFS size in RO_SECTION.
BUG = N/A
TEST = Boot Facebook FBG1701 with VBOOT enabled.
Change-Id: I2f1020acb3ec99d4cddbaa05b0998fe32b470d3e
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52026
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Replace the mainboard-specific code for "POST complete" signalling with
devicetree entries for using the newly introduced IPMI driver
functionality.
Test: Boot the machine via the BMC web interface and check that sensors
get read correctly by the IPMI firmware when the payload starts.
Change-Id: I7503dec4e72810db8dfe74f72638b466a3d66748
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48671
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On OCP Tioga Pass the pad GPP_B20 is used as output for signalling "POST
complete" to the BMC. According to the schematics and the code in
`ramstage.c`, the signal is active-low. There is an external pull-up
resistor.
To make the signalling work as it should, set the initial output value
to `high`.
Change-Id: I82fbda1caba9163ba3b2e38f494a0cefa27e657f
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48670
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The recent refactor of console UART GPIOs to mainboard's bootblock
caused brya boards to lose the first ~5 lines of the logs from
bootblock. Rename bootblock_mainboard_init to
bootblock_mainboard_early_init so that the UART pads will be ready
by the time the console is initialized.
BUG=b:184319828
TEST=First lines from report_platform.c are now seen in UART output
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I4a4fadcc091bf9b1c9894f9afaf42baff63c73a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
To pack a struct, the `__packed` attribute must come after the `struct`
keyword. Moreover, unions cannot be packed (structs inside unions can,
though). Correct uses of `__packed` so that EEPROM structs get packed.
Change-Id: I39d2c9ebc370605d5623b134189aa95a074ec7c3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: <wouter.eckhardt@prodrive-technologies.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Background story (I think that's what great in opensource -
ppl leave there part of their lives): ;-)
While trying to fix audio jack not working with coreboot and
Windows 10 with some help from hell__ and nico_h on IRC nico_h
discovered that t420 and t430 hda_verb.c are the same:
<nico_h> oddly, in coreboot source T420 and T430 have the same
numbers for very different codecs... I suspect copy-pasta
Difference between /sys/class/sound/cardX/hwCXDY/init_pin_config
in vendor BIOS helped with the updated config. Connecting audio
jack now works flawless both in Linux and Windows.
Audio-related keyboard buttons: volup, voldown, mute works fine
both in Linux (Debian-based) and Windows 10. mutemic button works
(tested ie. with xev) but both in Linux and Windows 10 wont light
up or makes any effect.
+-----------------------------------+
| init_pin_config dump from: |
+----= VENDOR =---+---= coreboot =--+
| 0x19 0x04211040 | 0x19 0x04211040 |
| 0x1a 0x61a19050 | 0x1a 0x61a19050 |
| 0x1b 0x04a11060 | 0x1b 0x04a11060 |
| 0x1c 0x6121401f | 0x1c 0x6121401f |
| 0x1d 0x40f001f0 | 0x1d 0x40f001f0 |
| 0x1e 0x40f001f0 | 0x1e 0x40f001f0 |
| 0x1f 0x90170110 | 0x1f 0x90170110 |
| 0x20 0x40f001f0 | 0x20 0x40f001f0 |
| 0x22 0x40f001f0 | 0x22 0x40f001f0 |
| 0x23 0x90a60170 | 0x23 0x90a60170 |
+-----------------+-----------------+
Tested-by: Piotr Szymaniak
Signed-off-by: Piotr Szymaniak <szarpaj@grubelek.pl>
Change-Id: Ie5eba84e5ea590b7db00e189cd68e714bee7e410
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51612
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable I2C2 in devicetree and fill ACPI information for Codec and
Speaker amplifiers. Pass correct IRQ GPIO for headset jack.
BUG=None
BRANCH=None
TEST=Ensure that the Codec and Speaker Amplifiers are detected in
i2cdetect.
Change-Id: I1ae52a8bbaa0181c906cd14a94de22e0250ed4c1
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52046
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure the BT disable GPIO to logic low in order to enable Bluetooth.
Add USB ACPI configuration for BT device.
BUG=b:182201890
TEST=Build and boot to OS.
Change-Id: I647c301e2db6d4a7c5c8cb31cbc47a44cba5e734
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51963
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Configure camera power GPIO to high
BUG=b:182207799
TEST=Build and boot to OS then checked camera device existence with lsusb
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Change-Id: Ie894167e3c4f8efdb3710599c6ff3a9fc975adb6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bhanu Prakash Maiya <bhanumaiya@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Initialize all eSPI signals including PCIE_RST0_L early for EC
communication.
- Set PCIE_RST0_L to a GPIO and set it high to release the bus. This is
a temporary workaround until PCIE_RST_L comes up on its own.
- Make sure all GPIO muxes initialized early are re-initialized.
BUG=b:183340503
TEST=Boot Guybrush
Change-Id: I512cb8b435dc8412cd46189e741ad94e5a24699e
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51675
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Mancomb does not have a dedicated SCI pin so it uses VW.
BUG=b:182211161
TEST=builds
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Id315ab448209d9c93494f7689361e45f8a6ed001
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51627
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
