Commit Graph

38266 Commits

Author SHA1 Message Date
John Su e59f70a4d9 mb/google/dedede/variants/madoo: Increase TCC offset from 5 to 10
Increase TCC offset value from 5 to 10 for Thermal Control Circuit (TCC)
activation.

BUG=b:171531244
TEST=build and verify by thermal team

Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: Ic2822b059f166779e1f0bcf92e753dad1078783c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47691
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Ben Kao <ben.kao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20 23:08:21 +00:00
Angel Pons 96a06dd464 nb/intel/sandybridge: Rename loop variable
The `discover_edges_real` function actually tests a range of values for
DQS PI and evaluates how the system responds. Rename the loop variable.

Change-Id: I67390ba315d618d153f91c0e8a81db04ec8f63e1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47606
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20 22:07:56 +00:00
Martin Roth cdd7d18120 mb/google/zork: Remove 50ms WIFI delay
As a part of trying to get our boot time as low as possible, any delays
in the code should try to be refactored out.  This removes the 50ms
delay in the WIFI sequence by enabling power and putting the wifi module
into reset in bootblock, then bringing it out of reset in ramstage.
This is significantly longer than the 50ms requirement.  The reset GPIO
was already being set high in ramstage, so that code didn't need to be
added.

BUG=b:171513520
TEST=Boot on boards with different module types, WIFI works on both.
BRANCH=Zork

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I211d3da338ad368d1f011f03cf7d05121c057075
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-20 19:30:48 +00:00
Johnny Lin 5b47d77047 intel/fsp2_0: Add soc_validate_fsp_version for FSP version check
Only need to check this once so check it at romstage where
the console is usually ready. Also define union fsp_revision
to avoid code duplication.

Change-Id: I628014e05bd567462f50af2633fbf48f3dc412bc
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2020-11-20 18:58:54 +00:00
Wisley Chen 982f64d1b7 mb/google/volteer/var/elemi: Update gpio
1. Config EN_PP3300_SSD (GPP_B2) to gpo
2. EMMC_CLKREQ_ODL(GPP_C1) change to GPP_H11
3. WLAN_PERST_L (GPP_H10) change to GPP_H10

BUG=b:172630765, b:171467336
BRANCH=volteer
TEST=emerge-volteer coreboot chromeos-bootimage and boot into emmc
Change-Id: I9d112373c4ecd2cea5ce3d2d47b190c061d50da6
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47705
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20 16:34:49 +00:00
Wisley Chen e928391f74 mb/google/volteer/var/elemi: enable Genesys Logic GL9763E
Enable Genesys GL9763E as PCI-to-eMMC bridge.

BUG=b:171467336
BRANCH=volteer
TEST=emerge-volteer coreboot

Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Change-Id: I858c12151df5b6fc19132869317edfa1b090335d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47040
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-20 16:34:35 +00:00
Paul Menzel bb1ada6d3a mb/asus/f2a85-m_pro: Enable PCIe bridge 00:15.2 in AGESA
Currently, the PCIe bridge 00:15.2 is not detected by coreboot, causing
the connected network device also to be missing.

This is caused by not configuring the third of the four PCIe General
Purpose Ports (GPP) of the AMD Fusion Controller Hub (FCH), which can be
exposed as one to four PCIe devices.

So, enable it in AGESA but disable enumeration in coreboot. Otherwise,
the serial console stops working in romstage after

    […]
    PCI: 00:15.1 bridge ctrl <- 0013
    PCI: 00:15.1 cmd <- 06
    PCI: 00:15.2 bridge ctrl <- 0013
    PCI: 00:15.2 cmd <- 07

and the system hangs in the payload (SeaBIOS banner is shown on VGA
attached monitor).

TEST=Serial console and payload works, and Linux 5.10-rc2 configures
     PCIe bridge. Output of `lspci -t`:

    -[0000:00]-+-00.0
               +-00.2
               +-01.0
               +-01.1
               +-10.0
               +-10.1
               +-11.0
               +-12.0
               +-12.2
               +-13.0
               +-13.2
               +-14.0
               +-14.2
               +-14.3
               +-14.4-[01]--
               +-14.5
               +-15.0-[02]--
               +-15.1-[03]----00.0
               +-15.2-[04]----00.0
               +-18.0
               +-18.1
               +-18.2
               +-18.3
               +-18.4
               \-18.5

Change-Id: Ia1d60a212b0d249c7d8b3f8ec16baf5e93c985da
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46527
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20 16:01:16 +00:00
Maxim Polyakov 33f4ec8217 Makefile.inc: Add CARRIER_DIR to component discovery
The idea is to split the “mainboard” category into “variants” and
“carrierboards”, in the case when we use the COMe module together
with the Carrier Board instead of a single monolithic motherboard.
Previously, the “variants” category defined the type of motherboard,
which has a number of differences from the base one, for example, it
differed in the size or type of memory, and in the configuration of
the interfaces. Thus, there is no need to create a separate directory
in src/mainboard for a board that is similar in configuration to the
base board. But for a COMe module, “variants” contains different
variants of only this module, and the entire Carrier Board configuration
is allocated to a separate category - “carrierboards”, and each of the
variants can be used with one of the many boards in “carrierboards”.

For example, in the case of the Kontron mAL10 COMe module, variant
refers to the COMe-mAL10 or COMe-m4AL10 module type. They differ in the
type of memory (DDR3L or DDR4), and maybe they differ in some chips (see
more in https://www.kontron.com/products). However, all variants contain
the same type of processor/SoC.

The "carrierboards" directory can be able contain both the Kontron's
Evalution carrier boards (such as Eval Carrier2 T10 and COMe
Ref.Carrier-i T10  TNI) and third party vendor backplanes that are
compatible with the COMe modules from “variants”.

Thus, the src/mainboard/<module-name> directory contains the common
configuration code for all variants from src/mainboard/<module-name>/
variants, which can be supplemented/redefined with a configuration from
src/mainboard/<module-name>/carrierboard/<vendor-carrierboard-name>.

This architectural solution will be able to systematize and simplify
understanding of the code structure for COMe modules and will allow
vendors to add/maintain their code in a separate directory.

This work is also the first step towards to union of all carrierboards
into the global category in src/carrierboard on a par with all boards
from src/mainboard.

The patch takes this into account in the build system and adds
CARRIER_DIR component to use the “carrierboards” category, as it has
done for VARIANT_DIR.

TEST = Build ROM image for Kontron mAL10 COMe module together with T10
TNI carrier board (https://review.coreboot.org/c/coreboot/+/39133).

Change-Id: Ic6b2f8994b1293ae6f5bda8c9cc95128ba0abf7a
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42609
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20 15:37:58 +00:00
Felix Singer 8db0a22677 vc/intel/fsp2/denverton_ns: Remove unused files
The Denverton-NS SoC uses the header files from the FSP git repository.
Therefore, remove these from coreboot source.

Change-Id: Ib22d3f5e5ce83eb83bf589ea8bba7b55ebe44ea8
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47754
Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20 15:25:11 +00:00
Angel Pons 5c186c6777 Documentation/releases: Update for 4.13
Fill in some blanks for 4.13, mark it done, add template for 4.14.
Also update the list of vboot supported boards.

Change-Id: Ie593efe515136a3b06620db6f0dbe3da00df7e9b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-20 12:01:35 +00:00
Felix Singer d959a20114 mb/clevo/kbl-u: Add Clevo N130WU/N131WU
Working:
- TianoCore
- NVMe, SATA3
- USB2, USB3
- Thunderbolt
- Graphics (GOP and libgfxinit)
- Sound
- Webcam
- WLAN, LAN, Bluetooth, LTE
- Keyboard, touchpad
- TPM
- flashrom support; reading / flashing from Linux
- ACPI S3

WIP:
- Documentation

Not working:
- EC ACPI (e.g. Fn keys, battery and power information)

Boots Arch Linux (Linux 5.8.12) successfully.

Change-Id: I364f5849ef88f43b85efbd7a635a27e54d08c513
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/28640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-11-20 11:57:11 +00:00
Arthur Heymans 3622c0bf10 soc/intel/xeon_sp/cpx: Modify PCH_IOAPIC_BUS_NUMBER
The PCH IOAPIC is not PCI discoverable.
Linux checks the BDF set in DMAR against the PCI class if it is a PIC,
which 00:1F.0 for instance isn't.

The SINIT ACM on the other hand bails out with ERROR CLASS:0xA, MAJOR
3, MINOR 7 if the BUS number is 0.

Change-Id: I9b8d35a66762247fde698e459e30ce4c8a2c7eb0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2020-11-20 10:18:57 +00:00
Arthur Heymans 3d802535cb soc/intel/xeon_sp: Set coreboot defined IOAPIC and HPET BDF
Don't rely on the FSP-S setting the HPET and IOAPIC BDF. This makes
coreboot in control of these settings.

Change-Id: I937ebf05533019cb1a2be771ef3b9193a458dddf
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2020-11-20 10:18:46 +00:00
Arthur Heymans 6e425e1275 soc/intel/xeon_sp: Use common P2SB functions to generate HPET IOAPIC
Change-Id: I700df8fe5243db46fa8458757b4e5596c4b9f404
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2020-11-20 10:18:34 +00:00
Arthur Heymans 054026cdb8 soc/intel/apollolake: use P2SB function to generate DMAR IOAPIC
Change-Id: If088d5bf701310e54b14965145229627f3a50417
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2020-11-20 10:18:25 +00:00
Arthur Heymans a1f65bed10 soc/intel/common/block/p2sb: Add ioapic BDF functions
This allows to get/set the IOAPIC bus device function.

Change-Id: Ib5bb409efbcbc5729cf0e996655c7ac3f6a78223
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47534
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20 10:18:12 +00:00
Arthur Heymans 695dd2977b soc/intel/xeon_sp: Use common P2SB functions to generate HPET DMAR
This makes coreboot more robust as it does not need to rely on syncing
values set by FSP and coreboot.

Change-Id: I2d954acdb939e7cb92d44b434ae628d7d935d776
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47533
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20 10:17:56 +00:00
Arthur Heymans 281868e55f soc/intel/apollolake: use P2SB function to generate DMAR HPET
Change-Id: I68f63c79d04cb2cddb92c9f6385459723f8858bd
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47532
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20 10:17:33 +00:00
Arthur Heymans f629f7b78b soc/intel/common/block/p2sb: Add hpet BDF functions
This allows to get/set the HPET bus device function.

Change-Id: I8d72da8bc392aa144d167d31cde30cc71cd1396e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47531
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20 10:17:22 +00:00
Arthur Heymans a8798a3179 soc/intel/common/p2sb: Add helper function to determine p2sb state
Change-Id: I1d6f9c18160806e289e98c2fa5d290c61434112f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47530
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20 10:13:31 +00:00
Frans Hendriks 7ba970aa78 drivers/intel/fsp1_1/cache_as_ram.S: Use _car_stack area for stack
Top of Temp RAM is used as bootloader stack, which is the
_car_region_end area. This area is not equal to CAR stack area as
defined in car.ld file.

Use _ecar_stack (end of CAR stack) as starting stack location.

Tested VBOOT, Vendorboot security and no security on Facebook FBG1701.

Change-Id: I16b077f60560de334361b1f0d3758ab1a5cbe895
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47737
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20 09:21:45 +00:00
Yidi Lin 2832d11dd1 mediatek/mt8192: memlayout: Add DRAM DMA region
SPM DMA hardware requires a non-cacheable buffer to load SPM
firmware.

TEST=verified with SPM WIP patch.
     SPM PC stays at 0x3f4 after SPM firmware is loaded.

Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: If6e803da23126419a96ffc0337d35edd0e181871
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-11-20 08:40:58 +00:00
Po Xu f06dd678e6 soc/mediatek/mt8192: Enable MT8192 auxadc driver
Enable reading from auxadc on MediaTek 8192 platform.

Reference datasheet: RH-A-2020-0070, v1.0

Signed-off-by: Po Xu <jg_poxu@mediatek.com>
Change-Id: Ic4c965fc3571637d882eb297e405a5d9e6f77dd3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-11-20 08:40:35 +00:00
Po Xu 3f11803075 soc/mediatek: Move auxadc driver from MT8183 to common
The auxadc (auxiliary analogue-to-digital conversion) is a unit
to identify the plugged peripherals or measure the temperature
or voltages.

The MT8183 auxadc driver can be shared by multiple MediaTek SoCs
so we should move it to the common folder.

Signed-off-by: Po Xu <jg_poxu@mediatek.com>
Change-Id: Id4553e99c3578fa40e28b19a6e010b52650ba41e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-11-20 08:40:19 +00:00
Maulik V Vaghela 0fd62f5b79 vc/google/chromeos/sar: Make "SAR not found" log a debug message
coreboot might not store wifi SAR values in VPD and may store it in
CBFS. Logging the message with 'error' severity may interfere
with automated test tool.

Lowering severity to BIOS_DEBUG avoids this issue.

BUG=b:171931401
BRANCH=None
TEST=Severity of message is reduced and we don't see it as an error

Change-Id: I5c122a57cfe92b27e0291933618ca13d8e1889ba
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-11-20 08:36:26 +00:00
Tim Chu 957a36397a vc/intel/fsp/fsp2_0/cpx_sp: Expose RasModesEnabled field in
SystemMemoryMapHob

This field from SystemMemoryMapHob can be used to define error
correction type in SMBIOS type 16.

Tested=On OCP Delta Lake, the value is expected.

Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I0009a287a64f16e926f682e389af3248aeb85bdf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47505
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20 00:51:03 +00:00
Arthur Heymans 051ee4e3ad soc/intel/xeon_sp: Lock down DMICTL
This is required for CBnT.

Change-Id: I290742c163f5f067c8d529ddca8e2d8572ab6e6a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47449
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20 00:47:05 +00:00
Arthur Heymans 0f91e9ce5f soc/intel/xeon_sp/cpx: Lock down P2SB SBI
This is required for CBnT.

Change-Id: Idfd5c01003e0d307631e5c6895ac02e89a9aff08
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46499
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20 00:46:29 +00:00
Julien Viard de Galbert a56e467287 configs: Add a sample config for scaleway tagada
Signed-off-by: Julien Viard de Galbert <julien@vdg.name>
Change-Id: I39fd9aabe7285d39e1883622ee9d6a60c6651b6e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-20 00:45:37 +00:00
Arthur Heymans c660600e42 soc/intel/xeon_sp/{skx,cpx}: Add txt_get_chipset_dpr callback
Change-Id: Id824324325d05b52fb2b9ced04fd3539cc37bd55
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46555
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20 00:44:30 +00:00
Julien Viard de Galbert c28f0e0802 mb/scaleway/tagada: GPIO on M.2 PCIe/SATA configure FSP HSIO lanes
Change-Id: Ic3ed97fc2b54d4974ec0b41b9f207fe3d49d2cce
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/25436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-20 00:43:58 +00:00
Julien Viard de Galbert 3065157da8 soc/intel/denverton_ns: Initialize thermal configuration
Change-Id: I7e1b924154256f8f82ded3d0fa155b3e836d9375
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/25439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-20 00:43:10 +00:00
Julien Viard de Galbert 69c57e19da soc/intel/denverton_ns: Enable MC Exception
Change-Id: I9773c61d06bb6c68612e498a35b5ad22cd5a8a6e
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/25434
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-20 00:42:46 +00:00
Julien Viard de Galbert 1c33f740c4 src/soc/intel/denverton_ns: Use improvement in coreboot since 4.9
- enable microcode in cbfs (won't boot without microcode)
 - force num fit entry to 1 to avoid crash in cbfstool/fit.c
 - re-enable FSP-CAR (tested to boot, while I couldn't boot with NEM)
 - enable io driver for uart in legacy mode (ie emulating legacy port by
   configuring the pci to legacy io address and hiding the pci device)

Signed-off-by: Julien Viard de Galbert <julien@vdg.name>
Change-Id: Ibc5ce91118c6052af23642fb3461f574cd888dea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
2020-11-20 00:42:38 +00:00
Angel Pons 50a6fe73c6 nb/intel/sandybridge: Remove unnecessary per-rank loops
The IOSAV_By_BW_MASK_ch registers are not per-rank. To preserve original
behavior, use a for-populated-channels loop instead of for-all-channels.

Tested on Asus P8H61-M PRO, still boots.

Change-Id: I6db35c41cd05420ceaeda93255f5ed73598a5bdd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-20 00:37:42 +00:00
Angel Pons 4c79f93082 nb/intel/sandybridge: Rename `discover_edges` functions
These are simply read MPR training, using the MPR pattern mode in MR3.

Change-Id: Icdc60572e0ee0b59dcb5dee1e1aceccfda79f029
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-20 00:37:27 +00:00
Angel Pons a93f46ebc0 nb/intel/sandybridge: Restore nominal Vref for current channel
After aggressive read training, program nominal Vref for the current
channel, not only channel 0. This simple mistake can easily degrade
memory margins, especially when running at high speed (overclocking).

Tested on Asus P8H61-M PRO, still boots.

Change-Id: I12630fe33c5c786c8ec131c45c27180c3887d354
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-11-20 00:36:06 +00:00
Angel Pons 011661cbfb nb/intel/sandybridge: Rename `timC_discovery` and related
This function simply determines the best delay for the TX DQ PIs.

Change-Id: If44c4f661d8c81fe41532ce2bfe3718392b9fe94
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-20 00:35:36 +00:00
Angel Pons 3d3bf484f5 nb/intel/sandybridge: Introduce `ddr3_mirror_mrreg` helper
Write training needs to update mode register 1, but `write_mrreg` will
clobber the IOSAV sequence. Reference code uses one four-subsequence to
unset Qoff in MR1, run the test, and finally set Qoff again. This will
be implemented in future changes, and will use the newly-added helper.

Change-Id: I06a06a7bdd43dbde34af4ea2f90e00873eefe599
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-20 00:34:17 +00:00
Angel Pons cf5dd49d3c nb/intel/sandybridge: Replace and-zero with assignment
The intent here is to clear the register, so a simple write will work.

Change-Id: I547805059e911942ac2cac7bd2165af23d926a2b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-20 00:33:39 +00:00
Angel Pons 60971dcd01 nb/intel/sandybridge: Introduce `find_predefined_pattern` function
Also fuse two per-channel loops together.

Tested on Asus P8H61-M PRO, still boots.

Change-Id: Iacc66f4364290a66d60d483055abef6e98223d16
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-20 00:33:30 +00:00
Angel Pons f305339d67 nb/intel/sandybridge: Rename receive enable functions
Give these functions more meaningful names.

Change-Id: I6b308120d4185a3bc448213a925d5cee0d4d8bd9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-20 00:32:17 +00:00
Angel Pons 12bd8ab2f9 nb/intel/sandybridge: Rework timA minmax code
There's no need to use `struct timA_minmax`, since most cases only care
about the difference between logic delay deltas. The final step does use
the minimum logic delay across all lanes, but it's a special case.

Tested on Asus P8H61-M PRO, still boots.

Change-Id: I1da95520ac915ab003e1a839685cbf5f1970eb6a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-20 00:31:19 +00:00
Duncan Laurie bd04995cdf mb/google/volteer: Add keyboard layout to fw_config
A new field was defined for different keyboard layouts, so add this field
to the list and provide the two options that were defined.

Change-Id: Ic357446725e34221040705929d54cbce94c5ab8b
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-20 00:28:02 +00:00
Duncan Laurie 3b70ad8ecf soc/intel/common: Use per-soc definition for BAR sizes
The various platform BARs are not always the same size across different
SOCs, so use the defined size rather than a hardcoded value.

This results in the following change on TGL which increased the MCHBAR
size to 128K:

-system 00:00: [mem 0xfedc0000-0xfeddffff] has been reserved
+system 00:00: [mem 0xfedc0000-0xfedc7fff] has been reserved

And fixes the following error output from the kernel:

resource sanity check: requesting [mem 0xfedc0000-0xfedcdfff],
  which spans more than pnp 00:00 [mem 0xfedc0000-0xfedc7fff]

Change-Id: I82796c2fc81dec883f3c69ae7bdcedc7d3f16c64
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-11-20 00:27:21 +00:00
Duncan Laurie 15ca9034b3 soc/intel/common/block/cse: Clear post code before reset
To avoid "unknown post code 0x55" entries in the event log on cold boot
clear the post code before doing the CSE initiated reset.

Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: I68078c04230dbc24f9cc63b1ef5c435055aa1186
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-20 00:27:13 +00:00
Duncan Laurie 2b3de787a4 mb/google/volteer/variants: Set TCSS PCIe RP0 to hidden by default
Set the default state of the TCSS PCIe RP0 to hidden so that coreboot
does not allocate resources to this hotplug root port.  The default
behavior on the reference design is that there is only one USB4 port
attached to port C1 while port C0 is only a USB3 port.

Meanwhile the Voxel and Terrador variants do have USB4 on both C0 and
C1 ports, so these boards change the default to 'on' so that coreboot
does allocate resources for the hotplug port.

BUG=b:159143739
BRANCH=volteer
TEST=build volteer and voxel and check the resulting static.c to
ensure the device is hidden or not.  Also boot with the two different
configurations and ensure resources are assigned or not.  Finally
check that S0ix still functions with the C0 port set to 'hidden'
after authorizing a PCIe tunnel on port C1.

Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: I8bb05ae8cd14412854212b7ed189cfa43d602c1d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47198
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20 00:27:04 +00:00
Duncan Laurie 7f6a484511 sconfig: Apply 'hidden' state from override tree
In order to allow override trees to hide/unhide a device copy
the hidden state to the base device.  This allows a sequence
of states like:

chipset.cb: mark device 'off' by default
devicetree.cb: mark device 'hidden' (to skip resource allocation)
overridetree.cb: mark device 'on' for device present on a variant

BUG=b:159143739
BRANCH=volteer
TEST=build volteer variants with TCSS RP0 either hidden or on
and check the resulting static.c to see if the hidden bit is
set appropriately.

Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: Iebe5f6d2fd93fbcc4329875565c2ebf4823da59b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47197
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20 00:26:11 +00:00
Duncan Laurie 98a9f1f61d mb/google/volteer: Set up SATAXPCIE1 IOSSTATE based on detected device
There is an issue with the storage device being mis-detected on exit
from S0ix which is causing the root device to disappear if the power
is actually turned off via RTD3.

To work around this read the RX state of the pin and apply the IOSSTATE
setting to drive a 0 or 1 back to the internal controller.  This will
ensure the device is detected the same on resume as on initial boot.

BUG=b:171993054
TEST=boot on volteer with PCIe NVMe and SATA SSD installed in the M.2
slot and ensure this pin is configured appropriately.  Additionally
test with PCIe RTD3 enabled to ensure suspend/resume works reliably.

Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: I85542151eebd0ca411e2c70d8267a8498becee78
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-20 00:25:46 +00:00
Duncan Laurie 7d97136749 soc/intel/tigerlake: Enable GPIO IOSTANDBY configuration
Enable SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY so the pads can be
configured with non-zero IOSSTATE values.

BUG=b:171993054

Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: I1f895dbdbb71a353a98272db6dc70b54e8e172a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47254
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20 00:25:37 +00:00