Load VBIOS in pci set_resources to PCI_VGA_RAM_IMAGE_START (0xc0000)
since pci_dev_init() will not load it in GOP case (VGA_ROM_RUN is not
set). Add Cezanne GFX PID.
BUG=b:171234996
BRANCH=Zork
Change-Id: I4a6fea9b6cd60c862e15ed2ed539869c0f9bd363
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Configure early GPIOs in verstage if it is run in PSP otherwise
configure them in bootblock.
BUG=b:181961514, b:180721208
TEST=builds
Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: Ib9410089592776ffe198901f2de914fd04bdbade
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The `q35-alpine.cfg` adds a lot of PCIe devices to resemble the
topology inside an Intel Alpine Ridge Thunderbolt controller.
By no means could this be detected as such a controller. But
having a real-world example of such a topology can help to
test the allocator and other algorithms on a deeper tree.
It adds two levels of PCIe switches (`alpine-root` and
`alpine-1`), and two endpoints (a `pci-testdev` and an xHCI
controller).
It can be added to the default `q35-base.cfg` config, e.g.
with:
$ make qemu QEMU_EXTRA_CFGS=util/qemu/q35-alpine.cfg
Change-Id: Ieab09c5b67a5aafa986e7d68a6c1a974530408b0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51329
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This UPD will be used to pass VBIOS buffer pointer to FSP PEI GOP
driver.
BUG=b:171234996
BRANCH=Zork
Change-Id: I0c5d4a9d96e5c3d47e262072b689ed62e59129b3
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49866
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
gpe_configure_sci has a size_t type parameter, so we need to include
types.h instead of stdint.h here.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2879d5cf27c432871a2b9c5c90bdd539b97f9d3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
CB:49896 added support in `intel_microcode_find()` to cache the found
microcode for faster subsequent accesses. This works okay when the
function succeeds in finding the microcode on BSP. However, if for any
reason, `cpu_microcode_blob.bin` does not contain a valid microcode
for the given processor, then the logic ends up attempting to find
microcode again and again every time it is called (because
`ucode_updates` is set to NULL on failed find, thus retriggering the
whole find sequence every time). This leads to a weird race condition
when multiple APs are running in parallel and executing this
function.
A snippet of the issues observed in the scenario described above:
```
...
microcode: Update skipped, already up-to-date
...
Microcode header corrupted!
...
```
1. AP reports that microcode update is being skipped since the current
version matches the version in CBFS (even though there is no matching
microcode update in CBFS).
2. AP reports microcode header is corrupted because it thinks that the
data size reported in the microcode is larger than the file read from
CBFS.
Above issues occur because each time an AP calls
`intel_microcode_find()`, it might end up seeing some intermittent
state of `ucode_updates` and taking incorrect action.
This change fixes this race condition by separating the logic for
finding microcode into an internal function `find_cbfs_microcode()`
and maintaining the caching logic in `intel_microcode_find()` using a
boolean flag `microcode_checked`.
BUG=b:182232187
TEST=Verified that `intel_microcode_find()` no longer makes repeated
attempts to find microcode from CBFS if it failed the first time.
Change-Id: I8600c830ba029e5cb9c0d7e0f1af18d87c61ad3a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51371
Reviewed-by: Patrick Rudolph
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
1. Follow GT7375P Programming Guide_Rev.0.6 to increase
reset delay to 180ms.
2. Add TOUCH_RPT_EN pin(GPP_A11) control to fix TOUCH_RPT_EN pin
keep high after system suspend.
BUG=b:181711141
TEST=Build and boot boten to OS.
Confirm TOUCH_RPT_EN pin keep low after system suspend.
Change-Id: I98efbe68dab538906802647582eba0e068d9c11f
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51254
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure I2C bus 5 high and low time for p-sensor device.
BUG=b:181727056
TEST=Measured the I2C bus frequency reduce to 387 KHz.
Change-Id: I4b6d78d84b8ea145093f52bbb13684e2c6aa979c
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Function is identical for all mainboards, so factor it out.
Change-Id: Ibe08fa7ae19bfc238d09158309f0a9fdb31ad21c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50028
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Suffix `SPIBAR_HWSEQ_XFER_TIMEOUT` with its units, use lowercase for hex
values and rename BIOS_CONTROL macros, as the register is not in SPIBAR.
Change-Id: I3bc1f5a5ebc4c562536829e63550c0b562b67874
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
UART pad configuration should not be done in common code, because that
may cause short circuits, when the user sets a wrong UART index.
Since all boards do pad setup on their own now, finally drop the pad
configuration from SoC common code.
Change-Id: Id03719eb8bd0414083148471ed05dea62a895126
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
UART pad configuration should not be done in common code, because that
may cause short circuits, when the user sets a wrong UART index. Thus,
add the corresponding pads to the early UART gpio table for the board as
a first step. Common UART pad config code then gets dropped in CB:48829.
Also switch to `bootblock_mainboard_early_init` to configure the pads in
early bootblock before console initialization, to make the console work
as early as possible. The board does not do any other gpio configuration
in bootblock, so this should not influence behaviour in a negative way
(e.g. breaking overrides).
Change-Id: I55815a824ea3a77e6e603ba4beb17457f37c48f5
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This patch adds the changes to enable the TCSS.
BUG=b:175808146
TEST= Boot shadowmountain board, Test the functionality of the Type-C
ports on both the mainboard and daughterboard by plugging in the Type-C
devices and verified the devices are detected via EC console and in the
OS.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: Ieaf1170ca718a14d24b773a4a85516e0bbfbb569
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51026
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since we have the SMN access block now, rename the SMU mailbox interface
registers to clarify that those are in the SMN register space.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic5b7093f99eabd3c29610072b186ed156f335bd8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The SMU mailbox interface gets accessed over the SMN register space, so
factor out those access functions into a separate common code SMN access
building block.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iabac181972c02ae641da99f47b2aa9aa28dae333
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Configuring touch controllers to use edge-triggered interrupts is not
recommended as it is very easy to lose an edge when kernel drivers
disable the interrupt for one reason or another, and recovering from
this condition requires workarounds in the kernel.
Unfortunately the example setting up a touchpad used edge-triggered
interrupts, and this set up has been propagating through the boards.
Let's switch the example to use level interrupts instead.
Change-Id: I4dc8b91ed070ce117553b00a087ad709aeaf16af
Signed-off-by: Dmitry Torokhov <dtor@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This mainboard uses a Comet Lake SoC and mixed-topology DDR4 memory.
Drop LPDDR-specific DQ and DQS mappings and comment about Cannon Lake.
Change-Id: Icb986d1c074e64b3cfad3897b69d35d108f64bff
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
EFI_PEI_MP_SERVICES_STARTUP_ALL_APS passes in a boolean flag singlethread
which indicates whether the work should be scheduled in a serially on all APs
or in parallel. Current implementation of this function mp_startup_all_aps
always schedules work in parallel on all APs. This implementation ensures
mp_startup_all_aps honors to run serialized request.
BUG=b:169114674
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Change-Id: I4d85dd2ce9115f0186790c62c8dcc75f12412e92
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51085
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a helper function mp_run_on_all_aps, it allows running a given
func on all APs excluding the BSP, with an added provision to run
func in serial manner per AP.
BUG=b:169114674
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Change-Id: I74ee8168eb6380e346590f2575350e0a6b73856e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51271
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Even though the implementation is different on Stoneyridge compared to
Picasso and Cezanne, the function prototypes are identical, so move them
to the AMD SoC common reset header file.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8d3a3a9ea568ea18658c49612efabdbe36d5f957
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Convert the lines starts with whitespace with tab as applicable.
TEST=Built google/brya0 and ADLRVP with BUILD_TIMELESS=1: no changes.
Change-Id: Ibd11ad12caa1be866a851a8cd4bd23349e8ffbbe
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51375
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Define the 26th bit of the fw_config for the regular touchpad
and numpad touchpad selection.
REGULAR_TOUCHPAD: 1
NUMPAD_TOUCHPAD: 0
BUG=b:174964012
BRANCH=zork
TEST=build pass
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: Ie2055d6bb45a64bc0e59209cecc0f8a31c0f3718
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
The VGA BIOS for AMD Padmelon and Google Zork are stored in `amd_blobs`.
Do not force inclusion of VGA BIOS when `USE_AMD_BLOBS` is not enabled.
Change-Id: I206e8fadc14ec0d9b162dc4d72813fdd3d43958b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
PSP_SHAREDMEM_BASE made the assumption that _psp_sharedmem_dram would
only match once. With CB:49332 there are now two symbols, and it was
grabbing the wrong one.
This change makes it so we match the exact symbol. It also switches to
using awk to simplify the code.
The bootblock.elf target that is added to the list of prerequisites also
creates the bootblock.map file that gets used to extract the base
address of the _psp_sharedmem_dram symbol.
BUG=b:181354692
TEST=Boot zork past bootblock
Fixes: 82d16b150c ("memlayout: Store region sizes as separate symbols")
Suggested-by: Julius Werner <jwerner@chromium.org>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I79675bd73f964282b54bca858830e26de64037c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Some of the previous binaries were incorrect and should not be used
for Majolica because they are templates instead of APCBs specifically
built for the board. This APCB update also places the UMA region under
4G and size 32 MB which is essential for video output.
TEST=Boot with UEFI BIOS and verify we can get to OS. Also verify memory
region size, base and alignment.
Change-Id: Id797e2ad5bd67815c09752aedc19dad7dcf8ad12
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Nikolai Vyssotski