Commit Graph

28412 Commits

Author SHA1 Message Date
Kyösti Mälkki 17387f67ad intel/spi: Fix use of __SIMPLE_DEVICE__
Fix cases of using ENV_SMM where __SIMPLE_DEVICE__
should be used instead.

Change-Id: I385c82767a87ff7a47466a200488fae9fc8b863d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31629
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2019-02-28 09:55:42 +00:00
Maulik V Vaghela db9e9ac30d soc/intel/cannonlake: Add PCH series check for CML LP PCH
TEST=Verify PM_STS1 value is is not 0xFF.

Change-Id: I932585f6e7525830bd57ecfc372bf3120e7cca66
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/31434
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-28 09:26:01 +00:00
Subrata Banik ba8af5807c soc/intel/cannonlake: Add Comet Lake U SA 2+2 Device ID
This patch adds CML-U 2+2 SA DID into systemagent.c and report
platform.

Change-Id: I2e882a560dd0a1e96d6e1405735c6f7389c0db5a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31638
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-28 02:22:11 +00:00
Subrata Banik e87bdbba29 soc/intel/skylake: Remove redundant PM emulation timer macros
This patch removes duplicate pm timer emulation macros from soc
directory and makes use from common code msr.h

Change-Id: I6ec347e7464f785862e855817ec8308e3d207bb1
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31610
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-28 02:21:44 +00:00
Martin Roth 3361120bc8 util/abuild: Set fatal asserts when running scanbuild
Because coreboot's asserts aren't fatal by default, scan-build finds
problems in code that is actually protected by an assert.  This
change fixes that and allows us to add asserts to protect
against other failures.

Change-Id: I9fa605d6309bb40a9cef33b434c9256bf731f457
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/31650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-02-27 19:33:43 +00:00
YH Lin 97278939ff flapjack: use sku_id 0 for un-provisioned board
Instead of using 2, 0 is now used for non-CBI provisioned board or
corrupted CBI board to confrom to the sku encoding.

BUG=b:123676982
BRANCH=kukui
TEST=test with un-provisioned board to verify the sku_id.

Signed-off-by: YH Lin <yueherngl@google.com>
Change-Id: I66f29f8a46cd774b40354def7d3623ec44cb96ce
Reviewed-on: https://review.coreboot.org/c/31623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-02-27 11:10:49 +00:00
Kyösti Mälkki e613d704d1 console: Split loglevel for fast and slow
For fast CBMEM console use minimum BIOS_DEBUG level.
For other consoles, Kconfig and/or nvram settings
apply.

Change-Id: Iff56a0a3182f258200cac80e013957d598cc2130
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-02-27 11:10:00 +00:00
Kyösti Mälkki 7132f259bf console: Refactor printk() varargs prototypes
Change-Id: I816641c2223c3079ad9c95c1380d4b250898ef93
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-02-27 11:09:31 +00:00
YH Lin 40f65425e4 ec/google/chromeec: fix the error status passing
Various instances of google_chromeec_command() can return non-zero number
(both positive and negative) to indicate error -- fixing cbi_get_uint32()
and cbi_get_string() so they follow the same convention.

BUG=b:123676982
BRANCH=kukui
TEST=build with kukui/flapjack configurations
Signed-off-by: YH Lin <yueherngl@google.com>
Change-Id: I7f0a8a61d01d942cba57036a17dd527fdbbf940c
Reviewed-on: https://review.coreboot.org/c/31585
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-27 11:08:18 +00:00
Tim Wawrzynczak b47c633c31 rtc: Fix rtc_calc_weekday
This function appeared previously unused (called only from rtc_display, also unused),
but it returned an incorrect weekday.  Change the algorithm to use Zeller's Rule, a
well-known algorithm for calculuating weekdays.

Change-Id: Ibce6822942f8d9d9f39c2b6065cd785dca9e8e09
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-02-27 11:07:11 +00:00
Rizwan Qureshi ec645cb086 mb/google/hatch: Initialize GPIO_PCH_WP early in boot
Initialize GPIO_PCH_WP early in boot. Update cros_gpios[] array with
GPIO_PCH_WP information. Also, Configure recovery mode GPIO as virtual
since hatch does not have one.

BUG=b:125943273

Change-Id: I0b7e6dbf9229941aca4952965fb54f07457dccae
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/31599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-27 11:05:38 +00:00
Rizwan Qureshi ba482d3972 mb/google/hatch: Select SD_PWR_EN Active high config
Hatch implements active high SD_PWR_EN and requires a workaround
in _PS0 and _PS3 control methods to make sure SD_PWR_EN stays low
in D3. Select MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE to enable the same.

BUG=b:123350329

Change-Id: I96ab9660eb50100207fe9a237f5924b65eae0928
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/31446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-27 11:05:26 +00:00
Rizwan Qureshi 8aadab7e96 soc/intel/cannonlake: Add a config for configuring SD_VDD1_PWR_EN#
SD controller in CNL-PCH provides a ability to configure the behavior of
SD_VDD1_PWR_EN# as an active high or low signal. FSP provides an UPD
"SdCardPowerEnableActiveHigh" to control the same.

However, for platforms using SD_VDD1_PWR_EN# as active high, the SDXC
card connector is always powered and may impact system power. This is because
SD_VDD1_PWR_EN# does not de-assert during SDXC D3 or when SD card is not
inserted.

Workaround is to change the pad ownership of SD_VDD1_PWR_EN to GPIO and
force the TX buffer to low in _PS3. And restore the pad mode to native
function in _PS0.

Hence add a Kconfig option to update the UPD, which the board can select
based on how the SD_VDD1_PWR_EN is implemented on it. And, the workaround
gets applied based on this config.

BUG=b:123350329

Change-Id: Iee262d7ecdf8c31362aec3d95dd9b3e8359e0c25
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/31445
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-27 11:05:13 +00:00
Rizwan Qureshi e64c25ca1a soc/intel/cannonlake: Add ASL functions to manipulate RX/TX buffers
Add a function in gpio ASL library to enable/disable pad Rx/Tx Buffers.

BUG=b:123350329

Change-Id: I6c40d79debb61b0c4e96e485b410d446b77d9cf6
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/31619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-27 11:04:40 +00:00
Rizwan Qureshi 51749b2766 mb/google/hatch: update SD card detect GPIO
SD_CD# in Cannonlake PCH is also wired to an internal virtual GPIO,
expose that GPIO for kernel to configure card detect IRQ.

BUG=b:123350329

Change-Id: I566cc2eb11dc257366897a1efba905b8ddcf493d
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/31553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-27 11:04:29 +00:00
Matt DeVillier ce529b6318 mb/google/cyan: fix RAM training on edgar variant
Adapted from Chromium commit 5351dc0d
[Edgar: To set the RX ODT limit and dram geometry with RAMID detection]

Several cyan variants require memory init parameters be passed to FSP 
for handling of specific Micron modules; without these, RAM init will
fail when loading training data from the MRC cache, and boot will halt.
This was missed when I upstreamed edgar along with the other cyan
variants, so add the required memory init parameters for edgar as per
its source Chromium branch.

Test: build/boot on edgar board with affected Micron memory 
modules, verify boot successful with populated MRC cache.

Change-Id: I6a2bc30b54ff1a17c854a90dfcb2308d27ee2be7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31615
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-27 11:04:00 +00:00
Patrick Rudolph 2201da3a8b soc/cavium/cn81xx: Drop VBOOT_RETURN_FROM_VERSTAGE
To support measured boot, drop VBOOT_RETURN_FROM_VERSTAGE.
The SoC has enough CAR space to support a separate verstage.

Tested on OpenCellular Elgon.

Change-Id: I18022000f6f05df89d3037896ef627070bfcca06
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/31568
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-27 11:03:07 +00:00
Furquan Shaikh ac8c60e011 soc/intel/cannonlake: Disable ACPI mode as part of pmc_soc_init
PMC initialization on Cannon Lake happens earlier in the boot sequence
than other SoCs because FSP-Silicon init hides PMC from PCI bus. As
ACPI disabling was done as part of PMC init, it was being called
earlier than what other SoCs do. This resulted in a different order of
events for some drivers e.g. ChromeOS EC. In case of ChromeOS EC, it
ended up clearing EC events (which happens as part of ACPI disabling
in SMM) before logging any events of interest that happen during
mainboard initialization.

This change moves the call to disable ACPI to pmc_soc_init just like
other SoCs to keep the order of events more aligned.

BUG=b:126016602
TEST=Verified that EC panic event gets logged to eventlog correctly.

Change-Id: Ib73883424a8dfd315893ca712ca86c7c08cee551
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/31614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-02-27 03:52:02 +00:00
Elyes HAOUAS b134368942 ACPI: Fix error on asl_compiler_revision format
dmesg report wrong asl compiler version as this value wasn't
in hexadecimal:
FACP 0x00000000CFB5D6C0 0000F4 (v04 COREv4 COREBOOT 00000000 CORE 01341407)
DSDT 0x00000000CFB5B280 002436 (v02 COREv4 COREBOOT 20190112 INTL 20190215)

This error was introduced on change-Id: I91b54b43c8b

Tested on 945G-M4 board, dmesg now report the right value:
FACP 0x00000000CFB5D6C0 0000F4 (v04 COREv4 COREBOOT 00000000 CORE 20190215)
DSDT 0x00000000CFB5B280 002436 (v02 COREv4 COREBOOT 20190112 INTL 20190215)

Change-Id: I5494bb1e7af17eba0c2da8a0c2eb9e40ffd8d065
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31612
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-26 21:44:01 +00:00
Lukasz Siudut 2352a507af Add missing u8 eos[2] declaration to struct smbios_type38
Each smbios entry should be followed with two null bytes. In other
structures it's done by adding `u8 eos[2]` extra bytes at the end, it
was omitted in type38 (IPMI) though. This change fixes this - tables
decodes nicely:

```
IPMI Device Information
        Interface Type: KCS (Keyboard Control Style)
        Specification Version: 2.0
        I2C Slave Address: 0x10
        NV Storage Device: Not Present
        Base Address: 0x0000000000000CA2 (I/O)
        Register Spacing: 32-bit Boundaries
```

Signed-off-by: Lukasz Siudut <lsiudut@fb.com>
Change-Id: I8efea9612448f48e23e7b2226aea2a9f3bc21824
Reviewed-on: https://review.coreboot.org/c/31482
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-26 21:41:20 +00:00
Richard Spiegel 3986d39471 soc/amd: Remove defined but unwritten functions
There are functions defined on headers with no code written for. They
probably existed earlier, were removed and forgot in the headers. Remove
functions from headers if there's no actual code written for.

BUG=b:123564495
TEST=Build grunt.

Change-Id: Ia6a12e22a0944351c455dc2c3b534f09a258bd7b
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/31507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-02-26 20:50:59 +00:00
Angel Pons a86e401c0e mb/gigabyte/ga-h61m-s2pv: fix cosmetic things
Remove unneeded options, note where usbdebug is, reorder devicetree and
clean up dsdt.

Tested, board still boots.

Change-Id: Ice0eff7b9829816aff4d334f4ac4a2fb435a2fb0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-02-26 18:49:02 +00:00
Elyes HAOUAS f8f2e8c39e ACPI: Fill asl_compiler_revision field left empty
Change-Id: I1075e872e5cb1990bd330b88bb03322ab9338e86
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-02-26 17:53:31 +00:00
Daisuke Nojiri 7bbed26ca9 ec/google/chromeec: Clarify return value of google_chromeec_command
This patch clarifies the definition of google_chromeec_command.

Currently absence of the definition isn't causing any problem because
wrapper APIs check 'ret != 0' or wrapper APIs check 'ret < 0' for an
interface which returns only negative error codes.

However, there is a chance that a new wrapper API will be addedl which
check 'ret < 0' to catch errors, assuming other interfaces behave the same.
Or existing wrapper APIs will be broken as soon as they're compiled for
another interface.

BUG=chromium:935038
TEST=none

Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: I2ce7109b5f2a1d5294f167719730bc1f039ba03f
Reviewed-on: https://review.coreboot.org/c/31613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-02-26 11:19:14 +00:00
YH Lin 967edec254 flapjack: get sku_id from ec (cbi)
On flapjack, retrieve the board information via CBI interface.

Also reserving 0x2 sku_id for the case of un-provisioned board as this is the id
used prior to the readiness of cbi.

BUG=b:123676982
BRANCH=kukui
TEST=provisioned cbi info and verify the sku_id.

Signed-off-by: YH Lin <yueherngl@google.com>
Change-Id: Iad7a52df38e2045abbdded8ba0a1f1544de961fc
Reviewed-on: https://review.coreboot.org/c/31586
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-26 11:18:40 +00:00
Patrick Rudolph 6220f8d833 soc/cavium/cn81xx: Enable RNG for DRAM init
The Cavium DRAM init might use the RNG for pattern generation.
Initialize it before running DRAM init.

Tested on OpenCellular Elgon.
The RNG generates non identical numbers.

Change-Id: I886f920e9941793fb76b56cc5a24a42e23b082e0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/31567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-02-26 11:18:18 +00:00
Qii Wang d569845964 mediatek/mt8183: Modify I2C source clock
This patch change i2c source clock to TOPCKGEN.

BUG=b:80501386
BRANCH=none
TEST=Boot correctly on kukui.

Change-Id: I49e0acda22dba449d0873a95ba5fae79a9cef569
Signed-off-by: Qii Wang <qii.wang@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/31519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-02-26 11:15:41 +00:00
Rizwan Qureshi 747154074c soc/intel/cannonlake: Update GPIO definitions for Virtual GPIO
Denote appropriate reserved groups as virtual GPIOs in Cannonlake LP/H SoC.

Change-Id: I4da161b91f83749b0ae29b387b5c99c1c3f706d8
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/31552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-26 11:15:05 +00:00
Werner Zeh db561e6e39 acpi: Sort the reported APIC-IDs in the MADT table
coreboot performs MP-Init in a parallel way. That leads to the fact
that the order, in which the CPUs are woken up, can vary from boot to
boot. The creation of the MADT table just parses the devicetree and
takes the CPUs reported there as it is for creating the single local
APIC entries. Therefore, the OS will see different order of CPUs.
There are CPUs out there (like Apollo Lake for example) which have
shared caches on core-level and if the order is random this can end up
in assigning cores to different tasks or even OSes (in a virtual
environment) which uses the same cache. This in turn will produce
performance penalties across these distributed tasks/OSes.

Though there is a way to discover the core- and cache-topology it will
in the end be necessary to take the APIC-ID into account. To simplify
it, one can achieve the same output by sorting the APIC-IDs in an
ascending order. This will lead to the fact that CPUs that share a given
cache will be reported right next to each other in the MADT.

Change-Id: Ida74f9f00a4e2a03107a2124014403de60462735
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/31545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-02-26 11:14:49 +00:00
Werner Zeh bd660e2338 commonlib: Add Bubble sort algorithm
Add an implementation for Bubble sort. For now, only integers can be
sorted in an ascending or descending order. It can be later simply
extended to cover other datasets like strings if needed.

The reasons for choosing bubble sort are:
* it is a simple algorithm
* bubble sort is stable, i.e. it does not exchange entries which are not
  needed to be sorted as they are already in order

Change-Id: I2c5e0b5685a907243b58ebe6682078272d316bf6
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/31544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-02-26 11:14:41 +00:00
Matt DeVillier 38b6ccfed9 payloads/tianocore: default to MrChromebox's working branch
Rather than attempt to maintain patches against upstream Tianocore, use
MrChromebox's coreboot framebuffer branch as the default build target.

Rework the Makefile to default to MrChromebox's coreboot_fb branch, but
also allow for aribitrary commits from upstream Tianocore to be used
as build targets.

Ensure the branch is synced on each build, as long as working directory
is clean, and that switching between commits or trees is handled sanely.

Eliminate TIANOCORE_MASTER as a selectable build target, since unpatched
it is unlikely to boot on any device. It can easily be specified via
the 'revision' option if desired.

Test: build for the default stable target, for upstream/master
as the specified revision, and for an arbitrary valid commit hash.

Change-Id: I4a83db3cd64c7d5b652c6e95780d10051f143e88
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-02-26 11:13:11 +00:00
Ronak Kanabar da7ffb48b2 soc/intel/common: Include cometlake PCH IDs
Add cometlake specific PCH IDs

Change-Id: I18dda48cee29213aa66c0ccddf3da31f0f489d2f
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/31234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-26 02:17:25 +00:00
Philipp Deppenwiese 66f9a09916 security/vboot: Add measured boot mode
* Introduce a measured boot mode into vboot.
* Add hook for stage measurements in prog_loader and cbfs.
* Implement and hook-up CRTM in vboot and check for suspend.

Change-Id: I339a2f1051e44f36aba9f99828f130592a09355e
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-25 22:29:16 +00:00
Patrick Rudolph bacd57dfaf cpu/x86/smm: Add qemu's SMM-Revision Level
The SMI handler on qemu returned early, due to missing SMM-Revision
Level support.

Add the ID qemu uses, which is AMD64 compatible for qemu-system-x86_64.

Fixes booting tianocore payload with SMM variable store on qemu.

Change-Id: I978b94150cfc49a39c2a0818eb14a649850e451d
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/31594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-02-25 11:21:53 +00:00
Mike Banon 749fe1eef9 src/device/Kconfig: Change default VESA mode from 117h to 118h
Change default VESA/native framebuffer mode (needed for bootsplash and
graphical framebuffer console) from 117h (1024x768 64k-color (5:6:5))
to 118h (1024x768 16.8M-color (8:8:8)) mode.

This provides console output at Lenovo G505S even if e.g. GRUB is the
payload, while it is unlikely to cause any downsides for the other
boards.

Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: Ia348199bbd430532b1399706dd84490c9680b5f5
Reviewed-on: https://review.coreboot.org/c/31595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-02-25 11:21:19 +00:00
Elyes HAOUAS e2af9b8481 ACPI: Enum only used ACPI tables
enum contained redundant names and wasn't exhaustive anyway.

Change-Id: I4d74ff61c555c5953932efbd7edccfd3157cb5be
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-02-25 11:20:35 +00:00
Damien Zammit f0a9128424 intelmetool: Use GPLv2+ where possible
Upstream intelmetool is out of date; I suggest I archive it
instead of trying to merge coreboot's changes into it.

However I would like to preserve the licensing of files in the tool
as GPLv2+ where possible instead of GPLv2-only.

Change-Id: I47b1ff2734f54c65f4214b39244bd868ef44b83c
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/c/31587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-02-25 11:19:37 +00:00
Patrick Rudolph b94ecc4e69 soc/cavium/common: Make ecam0_get_bar_val common
Move ecam0_get_bar_val into the common folder and make it public.
Compile it for romstage and ramstage.

To be used by romstage PCI code.
Tested on OpenCellular Elgon.

Change-Id: I18b1ede56795bf8c1f9476592291b8ea610eccd4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/31566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-02-25 11:18:32 +00:00
Elyes HAOUAS 99850600d0 sb/amd/hudson/acpi: Fix illegal object references
Issue spotted using IASL 20190215 on mainboard GIZMOSPHERE_GIZMO2:
"Object is created temporarily in another method and cannot be accessed"

Change-Id: I1e4ca2c765083db3a27e415d3a69bef0912a606b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31554
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-02-25 11:17:54 +00:00
Duncan Laurie a213ed659a ec/google/wilco: Fix ACPI power status events
This change fixes the power status events for AC and battery
events from the EC.  The register that was being used is not
returning the expected information.

BUG=b:125472740
TEST=enable ACPI debug in the kernel and verify that AC and
battery insert/remove are detected properly.

Change-Id: I15f71fcf0ca6aa9438e951865787c9fc273792d8
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-25 11:17:23 +00:00
Kyösti Mälkki 47b9e457fa AGESA vendorcode: Define libagesa rule just once
No reason to keep this rule in per-family directory.

Change-Id: I6bfc9a277674077774c4cb398f8add5e4fa99c69
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31509
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-25 11:16:52 +00:00
Kyösti Mälkki 423d03c163 soc/amd/common: Fix AmdLateRunApTask()
Third parameter ConfigPtr of the callout is of type
AP_EXE_PARAMS and needs to be passed back to AGESA
with AmdLateRunApTask() call.

Change-Id: I1dad64b955b53bd19363737665235f95aa3d451e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/27277
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-25 11:16:27 +00:00
Werner Zeh d35a4811db vendorcode/siemens: Cache currently opened hwi file name
On every call of hwilib_find_blocks() the CBFS file will be mapped and
the contents are parsed to get the offsets for every single block. This
is not needed if the CBFS file name is the same for the different calls.

This patch adds a storage for the currently opened CBFS file name in
CAR_GLOBAL and checks on each call if the file to open is already open.
If yes, the file will not be mapped again which saves execution time.

Test=Booted mc_tcu3, mc_bdx1 and mc_apl1 and verified that hwinfo.hex
is only mapped once across several following hwilib_find_blocks() calls.
In addition a test was done to ensure that files with different names
get mapped correctly.

Change-Id: Id69e0f6c914c2b8e4551fd8a4fb7d452d176afb3
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/31518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-02-25 05:39:45 +00:00
Patrick Rudolph 87abccdd89 mb/emulation/qemu: Fix fw_cfg file loading
The change bcd84fe "mb/emulation/qemu-i440fx: change file handling"
introduced a regression where it loads only 4 bytes of the
ACPI and SMBIOS table, instead of the whole table.

Load the whole ACPI and SMBIOS table.

Tested on Qemu using GNU/Linux.

Change-Id: Ibacbf7caab9be5f181c12e9dd39a2893b13cf6c9
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/31593
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-24 11:57:25 +00:00
Ronak Kanabar f606a2f5e6 soc/intel/common: Include cometlake SA IDs
Add cometlake specific SA IDs

Change-Id: I1fbbab8a7797b36a9eacbd1c6a0644466f2fe6b1
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/31226
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2019-02-24 04:49:37 +00:00
Ronak Kanabar 128bb2a7ca soc/intel/common: Include cometlake CPU IDs
Add cometlake specific CPU IDs

Change-Id: I75d5b82524c9df1402abf6659d62dbc716c28c30
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/31143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2019-02-24 04:49:25 +00:00
Elyes HAOUAS d8e55350f1 arch/x86/smbios.c: Remove duplicated 'processor_upgrade'
Change-Id: I3500a648631c91f3a0812c7e661440743ed6a1e1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-02-23 14:44:18 +00:00
Maulik V Vaghela 3647e5c151 drivers/intel/fsp2_0: Update dependency of USE_FSP_REPO
USE_FSP_REPO used to rely on SOC_INTEL_COMMON_CANNONLAKE_BASE which was
getting selected for cometlake soc also. Since FSP is not yet upstreamed
for cometlake, compilation was failing due to FSP was not found.

So limiting USE_FSP_REPO option to coffeelake and whiskeylake soc only
and excluding for cometlake.

Change-Id: I5e5d5a9fdf3f5d3e79922e97719e8491aa514cef
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/31530
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2019-02-23 14:25:31 +00:00
Subrata Banik ab9f64d011 soc/intel/cannonlake: Make few more whitespace proper in MCH name
CB:31547 fixes few whitespace error. Here is few more whitespace clean up.

Change-Id: I69c12a5da4feb48b2bc23874332ab341a559f6e6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-02-23 04:45:46 +00:00
Kyösti Mälkki b92853ed56 arch/arm64: Add PCI config support in romstage
Change-Id: I9cc3dc51764f24b986434080f480932dceb8d133
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-02-22 19:32:36 +00:00