Commit Graph

34894 Commits

Author SHA1 Message Date
Elyes HAOUAS ae22fe293f sb/intel/i82801gx: Use macro instead of numbers
Change-Id: Ide6516937ea79c35cd54127ed2823352a1cac6d4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41611
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-26 15:12:19 +00:00
Elyes HAOUAS 2f2191a3d0 sb/intel/i82801dx: Fix 16-bit read/write PCI_COMMAND register
Change-Id: Ie27054ded47b91a27036b5b4a21ab69b387239dc
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-05-26 15:11:47 +00:00
Elyes HAOUAS 5ac723e5a4 nb/intel: Fix 16-bit read/write PCI_COMMAND register
Change-Id: I7c7fb10308a6fcd1ead292c53ed03ddc693f6f15
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-05-26 15:11:33 +00:00
Srinidhi N Kaushik b30fe36734 soc/intel/tigerlake: Remove MIPI clock setting from devicetree
In Tiger Lake we have support for enabling MIPI clocks at runtime in
ACPI. Hence remove setting pch_islclk from devcietree and chip.h.
Also update functions which reference pch_isclk.

BUG=b:148884060
Branch=None
Test=build and boot volteer and verify camera functionality

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I6b3399172c43b4afa4267873ddd8ccf8d417ca16
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41570
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-26 15:11:03 +00:00
Wonkyu Kim b4d7116a74 soc/intel/tigerlake: Delete unused configuration
Delete below configuration
- Heci3Enabled: deprecated,
  see https://review.coreboot.org/cgit/coreboot.git/tree/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h#n442
- PchIshEnable: don't need as it's handled by devicetree dev on/off,
  see https://review.coreboot.org/cgit/coreboot.git/tree/src/soc/intel/tigerlake/romstage/fsp_params.c#n87

BUG🅱️151166877
BRANCH=none
TEST=Build and boot to OS

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: If96cc7db7118dd6c2ac02aab3bb0c96763ffc722
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-05-26 15:10:57 +00:00
Wonkyu Kim 165efa1b86 soc/intel/tigerlake: Disable VMD
It's already disabled by FSP default but disable VMD by devicetree
to remove dependency with FSP default setting.

BUG=None
Branch=None
Test=Build TGLRVP and boot up and check FSP log for checking VMD is
disabled.

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ief81fe481b94abed9754881cf1f454999fafa52e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41061
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-26 15:09:50 +00:00
Jonathan Zhang f381d97856 drivers/intel/fsp2_0: print soc specific GUID extension hobs
Some SoC specific hobs are of HOB_TYPE_GUID_EXTENSION.

Call SoC specific soc_display_hob() to display the content as necessary.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Ib4e4abe2d89b04504d1988d8d3c2fde268b5345a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-26 15:09:25 +00:00
Sumeet R Pawnikar 2adb50d32e apollolake: update processor power limits configuration
Update processor power limit configuration parameters based on
common code base support for Intel Apollo Lake SoC based platforms.

BRANCH=None
BUG=None
TEST=Built and tested on octopus system

Change-Id: I609744d165a53c8f91e42a67da1b972de00076a5
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41233
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-26 15:09:09 +00:00
Furquan Shaikh a54bfd5e95 Update vboot submodule to upstream master (commit hash c531000)
This change updates vboot submodule from commit hash 3aab301:
vboot: Convert reboot-related errors to vboot2-style

to commit hash c531000:
vboot: Add recovery reason code for CSE Lite SKU errors

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ifbf5a09e6602c3f6833e6e8fbbd3cee3f60f1b47
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-26 15:07:52 +00:00
John Zhao f5b33c0016 mb/google/volteer: Enable D3HotEnable and D3ColdEnable for Volteer
This explicitly enables both of TCSS D3HotEnable and D3ColdEnable
from Volteer devicetree.cb setting.

BUG=🅱️146624360
TEST=Built and booted on Volteer.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I1a168ad87169c0f6633704c55c9293aa25710188
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-05-26 15:07:24 +00:00
John Zhao 3c8cb24fc3 mb/intel/tglrvp: Enable D3HotEnable and D3ColdEnable for tglrvp
This explicitly enables both of TCSS D3HotEnable and D3ColdEnable
from tglrvp devicetree.cb setting.

BUG=🅱️146624360
TEST=Built and booted on tglrvp.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I3b77fe15bd67e513f193f704030a98241e058437
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41554
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-05-26 15:07:21 +00:00
John Zhao 8aac881fe8 soc/intel/tigerlake: Add FSP UPD D3HotEnable and D3ColdEnable
This adds FSP UPD D3HotEnable and D3ColdEnable for configuration.
D3Hot low power mode support is for TCSS xhci, xdci, TBT PCIe root
ports and DMA controllers. D3Cold is lower mode for TBT PCIe root
ports and DMA controllers with D3Hot->D3Cold transition.

BUG=🅱️146624360
TEST=Built and booted on Volteer.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I6782cde6a1bfe13f46e75db8c85537c6d62f5d41
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-05-26 15:07:07 +00:00
Shelley Chen 1408798637 Mushu: Enable PCIe 1d.4 to enable dgpu
BUG=b:147249494,b:147249494
BRANCH=None
TEST=boot up mushu
     check cbmem -1 to make sure PCIe 1d.4 is enabled

Change-Id: I36404217f0ecffb0cce1105e76f507c9062df053
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41564
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-26 15:06:38 +00:00
William Wei d9cd064ac6 mb/google/volteer: Enable ELAN trackpad wake suspend function
BUG=b:156990317
TEST=emerge-volteer coreboot chromeos-bootimage
Boot to kernel and check the ELAN trackpad can wake up unit from suspend.

Signed-off-by: William Wei <wenxu.wei@bitland.corp-partner.google.com>
Change-Id: If4bea8a9742f7533be2e51b855cc39ca77d73608
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-26 15:05:48 +00:00
Elyes HAOUAS 4751390b61 soc/intel/skylake/acpi/smbus.asl: Fix typo in comment
Change-Id: I2d0c90afe8acf8405da2cb6444e47dc98ad8cc9b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40691
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-26 15:05:18 +00:00
Kyösti Mälkki fcbbb91116 Remove MAYBE_STATIC_BSS and ENV_STAGE_HAS_BSS_SECTION
After removal of CAR_MIGRATION there are no more reasons
to carry around ENV_STAGE_HAS_BSS_SECTION=n case.

Replace 'MAYBE_STATIC_BSS' with 'static' and remove explicit
zero-initializers.

Change-Id: I14dd9f52da5b06f0116bd97496cf794e5e71bc37
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-26 15:04:08 +00:00
Yu-Ping Wu 1c3faabf24 libpayload/cbgfx: Remove gap between adjacent boxes
When drawing two adjacent boxes with draw_box(), there will be a gap
between them. This is due to the truncation in integer division when
calculating the bottom right coordinate of the box.

In this patch, the relative bottom right coordinate is calculated before
transforming to an absolute one. The same issue is also fixed for
draw_rounded_box().

Also check validity of 'pos_rel' and 'dim_rel' arguments for
draw_rounded_box().

BRANCH=none
BUG=chromium:1082593
TEST=emerge-nami libpayload

Change-Id: I073cf8ec6eb3952a0dcb417b4c3c3c7047567837
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-05-26 15:03:59 +00:00
Sumeet R Pawnikar 309ccf74dd cannonlake: update processor power limits configuration
Update processor power limit configuration parameters based on
common code base support for Intel Cannonlake SoC based platforms.

BRANCH=None
BUG=None
TEST=Built and tested on drallion system

Change-Id: Iac6e6f81343fcd769619e9d7ac339430966834f6
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41235
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-05-26 15:02:54 +00:00
John Zhao 7d054bd38f soc/intel/tigerlake: Fix wrong operation region for CPU to PCH method
CPU to PCH method refers to PCH ACPI operation region which was wrongly
defined as SystemMemory and PCH_PWRM_BASE_ADDRESS. Change the operation
region to be SystemIO and ACPI_BASE_ADDRESS.

BUG=b:156530805
TEST=Built and booted to kernel.

Signed-off-by: John zhao <john.zhao@intel.com>
Change-Id: Ifa291a993ec23e1e4dfad8f6cdfabc80b824d20c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-05-26 15:02:16 +00:00
Christian Walter e6e9fa6ef9 soc/intel/cannonlake: Add VrPowerDeliveryDesign to chip options
Intel introduced the UPD VrPowerDeliveryDesign with Cannon Lake. The
BIOS needs to program VrPowerDeliverDesign configuration per platform
according to the platform capabilities to avoid incorrect
electrial/power parameters. This is only added for Cannon Lake.

Refer to document 599797 for more details.

Change-Id: I89b8dceb40fa6a9dc67b218e91bf728ff928b5a0
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41081
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-26 15:01:29 +00:00
Nico Huber 9ea70c02cd intel/cannonlake: Implement PCIe RP devicetree update
Some existing devicetrees were manually adapted to anticipate
root-port switching. Now, their PCI-device on/off settings should
just reflect the `PcieRpEnable` state and configuration happens
on the PCI function that was assigned at reset.

Change-Id: I4d76f38c222b74053c6a2f80b492d4660ab4db6d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-26 15:01:00 +00:00
Elyes HAOUAS 95dcf29b2f drivers/intel/fsp2_0: Remove unused 'include <memrange.h>'
Change-Id: Ic3eb8fca22e73a0d485a6c1bf35c33b1fc606e4a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41488
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-26 14:59:30 +00:00
Elyes HAOUAS 38b58d4f51 mb/google/foster: Remove unused 'include <memrange.h>
Change-Id: Ic26d03d0e695ce0823332d4c6430186c7bfbeac1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-26 14:59:20 +00:00
Elyes HAOUAS bfc255a121 src/sb: Use 'print("%s...", __func__)'
Change-Id: Ie0d845d3e501ed5ebeef1997944445d31768e410
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39373
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-26 14:58:51 +00:00
Elyes HAOUAS a1b19de447 Documentation/acpi: Fix the path to variants/hatch/overridetree.cb
Change-Id: I7c3fd942318f28b4714bc7c2a47bedf85f7923ed
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-26 14:58:35 +00:00
Raul E Rangel 93b62e6170 soc/amd/picasso: Give the mainboard the ability to modify the MADT table
By default legacy ISA IRQs use edge triggering. Depending on what
devices are used the IRQ types might need to be changed. We add a
setting to the device tree to allow the mainboard to configure the IRS
IRQs.

BUG=b:145102877
TEST=Booted trembyle and was able to use the keyboard.

Change-Id: Ie95e8cc7ca835fb60bee8f10d5f28def6c2801dc
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2033493
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41577
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-26 14:37:22 +00:00
Angel Pons a0bf2d6cf5 superio/ite/Makefile.inc: Add it8613e
This Super I/O was not being built at all. Correct that.

Change-Id: Id053fa919cac7b2df6a6fc45aae5e34a0dc8c0ae
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-05-26 13:03:50 +00:00
Angel Pons ec6e03e4d8 AGESA f14/f15tn/f16kb: Deduplicate RAM settings
On AGESA f14/f15tn, various RAM-related options were defined in an enum.
However, the preprocessor mess can't compare enum values. To make AGESA
build, each board redefined them as macros, shadowing the enum elements.
Clean this up by replacing the enums with macros in AGESA headers, and
delete the now-redundant redefinitions from all the mainboards.

Note that AGESA f16kb already uses macros, but each mainboard still had
commented-out definitions. Remove them as well, as they are unnecessary.

TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb
mainboards result in identical coreboot binaries.

Change-Id: Ie1085539013d3ae0363b1596fa48555300e45172
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41666
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-26 11:47:19 +00:00
Angel Pons 6482916111 AGESA f16kb: Factor out default MTRR settings
All AGESA f16kb boards use the same MTRR values. Factor them out,
while still allowing a board to override them via BLDCFG.

TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb
mainboards result in identical coreboot binaries.

Change-Id: I236e9d45505e92027acc3ba5ff496f5e2f09b9f3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
2020-05-26 11:47:02 +00:00
Angel Pons 7ee8e7f129 AGESA f15tn: Factor out default MTRR settings
All AGESA f15tn boards use the same MTRR values. Factor them out,
while still allowing a board to override them via BLDCFG.

TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb
mainboards result in identical coreboot binaries.

Change-Id: I90c95493de1bb5b8f32c06b9575fef3aa7aca031
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
2020-05-26 11:46:47 +00:00
Angel Pons 7e577ad22f AGESA f14/f15tn/f16kb: Factor out memory settings
We use the same values everywhere, so we might as well factor them out.

TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb
mainboards result in identical coreboot binaries.

Change-Id: Ie6f166034d5d642dff37730a8d83264fb2e019b4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2020-05-26 11:46:21 +00:00
Angel Pons 5f82370d7b AGESA f14/f15tn/f16kb: Factor out PCI MMIO base/size
We set BLDCFG_PCI_MMIO_BASE and BLDCFG_PCI_MMIO_SIZE to the same values
everywhere, so we might as well factor them out. As we have equivalent
Kconfig options in coreboot, also deprecate overriding them via BLDCFG.

TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb
mainboards result in identical coreboot binaries.

Change-Id: I7244c39d2c2aa02a3a9092ddae98e4ac9da89107
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
2020-05-26 11:46:09 +00:00
Angel Pons 41b820cbd6 AGESA f14: Factor out default MTRR settings
All AGESA f14 boards use the same MTRR values. Factor them out, while
still allowing a board to override them via BLDCFG.

TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb
mainboards result in identical coreboot binaries.

Change-Id: Id980e4671e51fe800188f0a84768a307c8965886
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
2020-05-26 11:45:24 +00:00
Angel Pons 0c983df7ca AGESA f14 boards: Drop useless family definitions
AGESA f14 only uses INSTALL_FAMILY_14_SUPPORT. Drop the rest.

TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb
mainboards result in identical coreboot binaries.

Change-Id: I2fc6ba94cde66a238da9705fc42330b9e7682800
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41593
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-26 11:37:39 +00:00
Angel Pons 033ea49bef AGESA f14 boards: Drop useless socket definitions
AGESA f14 only uses INSTALL_FT1_SOCKET_SUPPORT. Drop the rest.

TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb
mainboards result in identical coreboot binaries.

Change-Id: I48efa7496c8101115b4735a99c8c472ac65c0523
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41592
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-26 11:36:38 +00:00
Angel Pons c072e794e6 AGESA f14/f15tn/f16kb: Factor out AGESA_VERSION_STRING
We use the same AGESA version numbers on all but one mainboard, so we
might as well factor them out. The only exception is asrock/e350m1,
which has the f15tn/f16kb version number even though it actually uses
AGESA f14. To preserve reproducibility, do not change it in this commit.

TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb
mainboards result in identical coreboot binaries.

Change-Id: I0dad2352ccda454d5545f17228d52e4ff4f23f20
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41591
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-26 11:36:07 +00:00
Angel Pons f689d2ee19 AGESA f14/f15tn/f16kb: Factor out AGESA_PACKAGE_STRING
We use the same value everywhere, so factor it out. Note that the field
where this value ends up in was doubled in size for AGESA fam16kb, but
we did not update the definition to fill in the additional space. We are
not changing it in this commit so as to preserve binary reproducibility.
In any case, add a FIXME explaining why this value may not be correct.

TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb
mainboards result in identical coreboot binaries.

Change-Id: Ied118d534ee1e9728db843944d1e042760b4f32c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41590
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2020-05-26 11:35:40 +00:00
Angel Pons 66ee42daba mb/*/*/buildOpts.c: Clean up whitespace
Drop multiple blank lines and use one space inside C-style comments.

TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb
mainboards result in identical coreboot binaries.

Change-Id: Ibe1f279dd22ae7657ea7b7766f88004dbf4dceb5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2020-05-26 11:32:13 +00:00
Angel Pons 927f6ae84a mb/*/*/buildOpts.c: Drop BLDCFG_IR_PIN_CONTROL
This does not exist anywhere in the entire coreboot tree. Drop it.

TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb
mainboards result in identical coreboot binaries.

Change-Id: I80320a20f4b44896e72d701a1d98786cb3a93dcc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2020-05-26 11:31:57 +00:00
Patrick Rudolph 477b4f8886 mb/lenovo/t410: Set default CBFS size
Set the default CBFS size to cover the whole BIOS region.

Change-Id: If719a9cd2897d933df53bd423e71503b832411fe
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40776
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-05-26 09:30:51 +00:00
Pandya, Varshit B 39ea0eab41 mb/intel/jasperlake_rvp: Add world facing camera support
1. Configure GPIOs as per schematics
2. Add 1 Ports and 1 Endpoints
3. Add support for OTVI5675

WFC is on I2C5 with VCM support and using 2 data-lanes

BUG=None
BRANCH=None
TEST=Build and Boot jslrvp board and able to capture image
using world facing camera.

Change-Id: I07ae9e3473c16bde8eb1597460e70cc478357b98
Signed-off-by: Pandya, Varshit B <varshit.b.pandya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2020-05-26 08:41:42 +00:00
Ronak Kanabar 641221c0a1 soc/intel/jasperlake: correct IRQ routing Jasper Lake
Current Interrupt setting use 2nd parameters as device function number.
Correct as interrupt pin number according to _PRT package format.
{Address, pin, Source, Source index}

Reference:
- ACPI spec 6.2.13 _PRT

BUG=None
BRANCH=None
TEST=Build and boot JSLRVP Verify Interrupt mappings are same as PCI
INTR(0x3C) register and no interrupt storm is seen

Change-Id: I21462c6befea310a49eecf9ad1b5c8770eccd5bd
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41404
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-26 05:55:30 +00:00
Da Lao 56f5cc7ee3 ec/lenovo/h8: Config the ec hardware ids for newer thinkpads
Currently coreboot is using the ec hardware id IBM0068 for all
thinkpads, but for newer thinkpads the id maybe LEN0068 or LEN0268.
On Windows, the Lenovo Vantage app can't get battery details when using
IBM0068. This patch config this id by motherboard. The hardware IDs for
the following models can be found by searching for disassembled
dsdt.asl on vendor BIOS:
(But this info is not easy to find online. So I only changed some of
the thinkpads.)

T420:
https://github.com/tluck/Lenovo-T420-Clover/blob/master/EFI/CLOVER/ACPI/1600x900-EDID/DSDT.edid-2e2-hs.dsl
LEN0068

T430:
https://github.com/ThiagoSchetini/macosx-thinkpad-t430/blob/master/vanilla%20ACPI%20dsl's/DSDT.dsl
LEN0068

T520: Confirmed by Patrick Rudolph
LEN0068

W520: Confirmed by Patrick Rudolph
LEN0068

T530: Confirmed by Prasun Gera
LEN0068

W530: https://bugzilla.kernel.org/show_bug.cgi?id=66731
LEN0068

X230/X230T:
https://github.com/tuandzung/ThinkPad-X230-macOS-10.12.x/blob/master/DSDT/DSDT.dsl
LEN0068

T440p: https://github.com/doudou/t440p/blob/master/acpi/2.30/dsdt.dsl
LEN0068

Signed-off-by: Da Lao <dalao@tutanota.com>
Change-Id: I797080ec8ba7ce39d47fe587319f8f32d6938875
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-05-26 04:41:43 +00:00
Jacob Garber 10999ea628 drivers: Use SPDX identifiers
Convert the remaining files in src/drivers to use SPDX identifiers.

int15.h and default_brightness_levels.asl did not have license headers,
but they were both copied from other GPL2 files, so they should be under
the GPL2 as well.

ne2k.c and drm_dp_helper.h are licensed under custom BSD-like licenses
that do not have an SPDX equivalent, so they are added as exceptions
to the license header lint.

Change-Id: I87fb1c637b8d11b0463f7c19f70b847413e14aed
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-25 22:19:21 +00:00
Jacob Garber fa8f567f32 security/tpm: Use SPDX identifiers
Also adjust a few comments to follow the style guide.

Change-Id: I22001320f2ce1f0db348e0f7fabc5a65b50ba53e
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-25 22:18:13 +00:00
Felix Held e6fcfc2a48 vc/amd/fsp/picasso: add Picasso misc data HOB GUID and struct
BUG=b:153779573

Change-Id: I417ce34f2c302d61cfe94ff478f9022cae16f046
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41629
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-24 04:56:01 +00:00
Felix Held f309204c53 soc/amd/picasso/include/cpu: add Raven1 CPUID
Change-Id: Iaf848a68dc50c2af1e32b996f09296aaea935459
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41628
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-24 04:55:41 +00:00
Angel Pons acf80f287f mb/asrock/b85m_pro4/gma-mainboard.ads: Use GPL-2.0-or-later
Other files in the tree use such license. I first added this file.

Change-Id: I338654ec022bd6f2fa4a4381a8f27d024605e79d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41525
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-05-23 21:47:47 +00:00
Jacob Garber e61f149659 soc/intel/broadwell: Use SPDX identifier
Change-Id: Ifbab50ef42f0fe49dd3949db662b245c63522f2d
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41599
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-23 21:03:35 +00:00
Jacob Garber 005fe89daa Makefile: Use SPDX identifier
Change-Id: Ia05f2ecd31d0606dfe2bca843dbe6df2b8212a27
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41598
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-23 21:03:17 +00:00