They always require special care so that line breaks and variable names
are escaped properly. One loop can be removed entirely because install
accepts multiple files to install in a target directories, the other
loops were filled by find which can just call the commands on its own.
Change-Id: I9f9dddfe3f3ceceb6a0510d6dd862351e4b10210
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79523
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add touchscreen ILTK for craaskwell.
Refer to ILI2901A-A200 Data Sheet_V1.1_20231026.
BUG=b:308873706
TEST=build and check touchscreen function on craask
Change-Id: I6a68855b1659ff0c9cd33a0ec9acbd289f525a3d
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79735
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Create the dita variant of the taranza project by
copying the files to a new directory named for the variant.
BUG=b:317292413
BRANCH=dedede
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_DITA
Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: I843e33f30cd356e4f12330bdfe2d53a0b3920ef3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79655
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
This patch implements an API which relies on the
chromeos_get_factory_config() function to retrieve the factory
config value.
This information is useful to determine whether a ChromeOS device
is branded as a Chromebook Plus based on specific bit flags:
- Bit 4 (0x10): Indicates whether the device chassis has the
"chromebook-plus" branding.
- Bits 3-0 (0x1): Must be 0x1 to signify compliance with
Chromebook Plus hardware specifications.
BUG=b:317880956
TEST=Able to verify that google/screebo is branded as
Chromebook Plus.
Change-Id: Iebaed1c60e34af4cc36316f1f87a89df778b0857
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This code leverages the TPM vendor-specific function
tlcl_cr50_get_factory_config() to fetch the device's factory
configuration.
BUG=b:317880956
TEST=Able to retrieve the factory config from google/screebo.
Change-Id: I34f47c9a94972534cda656ef624ef12ed5ddeb06
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch enables retrieval of factory configuration data from
Google TPM devices (both Cr50 and Ti50).
This patch utilizes vendor-specific command
TPM2_CR50_SUB_CMD_GET_FACTORY_CONFIG (68).
The factory config space is a 64-bit, one-time programmable.
For the unprovisioned one, the read will be 0x0.
BUG=b:317880956
TEST=Able to retrieve the factory config from google/screebo.
Change-Id: Ifd0e850770152a03aa46d7f8bbb76f7520a59081
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79736
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The package 'bluezFull' got superseded by 'bluez'. So just remove the
related line since 'bluez' is the default.
Change-Id: Ibf72c37205017b27012064b311a9510136351c0f
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Following commands were used to test if everything builds:
* make crossgcc
* make clang
* make what-jenkins-does
Change-Id: I8d04c570f91215f534f173db2ae559b64b58012f
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
As a preparation for WiFi SAR table addition, adding hook for it.
BRANCH=nissa
BUG=b:315418153
TEST=emerge-nissa coreboot
Cq-Depend: chrome-internal:6790137
Change-Id: Idb200699bb8c8581b9512ec8ec9442f65f8822b3
Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Align the comments on the PIRQ table entries for the PCI bridge devices
to the external PCIe ports with the devicetrees of the different APU
boards.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id25ae8422c7c5c79dc8666a28a8219c77af324da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Add `VBOOT_X86_RSA_ACCELERATION' Kconfig option to enable SSE2
instruction set implementation of modulus exponentiation which is part
of the RSA signature verification process.
BUG=b:312709384
TEST=Able to use SSE2 accelerated implementation on rex0
Change-Id: Ib6e39eb9f592f36ad3dca76c8eaf2fe334704265
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79289
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use the `VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE' constant defined by
the vboot project instead of hard-coding the buffer size.
Change-Id: I6039fc7cf2439535ca88663806bdcf99ad5089b0
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Updating from commit id c0cb4bfa:
2023-12-08 signer: sign_android_image.sh should die when image repacking fails
to commit id 7c3b60bb:
2023-10-13 firmware/2lib: Use SSE2 to speed-up Montgomery multiplication
This brings in 3 new commits:
7c3b60bb firmware/2lib: Use SSE2 to speed-up Montgomery multiplication
8bb2f369 firmware: 2load_kernel: Set data_key allow_hwcrypto flag
2b183b58 vboot_reference: open drive rdonly when getting details
6ee22049 sign_official_build: switch from dgst to pkeyutl
da69cf46 Makefile: Add support for make 4.3
Also update the implementations of the vb2ex_hwcrypto_modexp() callback
to match the API changes made in vboot.
Change-Id: Ia6e535f4e49045e24ab005ccd7dcbbcf250f96ac
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
The FSP boot mode showing in serial log is a magic number.
In order to let user understand its meaning directly, add
the strings to describe the modes.
TEST=build, boot the device and check the logs:
without this change, the log is like:
[SPEW ] bootmode is set to: 2
with this change:
[SPEW ] bootmode is set to: 2 (boot assuming no config change)
Change-Id: I49a409edcde7f6ccb95eafb0b250f86329817cba
Signed-off-by: Marx Wang <marx.wang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Update definition to be more intuitive and extensible.
Port descriptors will be defined as individual entities and added
to the descriptor list as such.
BUG=b:281059446
TEST=builds
Change-Id: I23ddd11b7e4da35a0d81299aa648f928e81ea24e
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79626
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update definition to be more intuitive and extensible.
Port descriptors will be defined as individual entities and added
to the descriptor list as such.
BUG=b:281059446
TEST=builds
Change-Id: Ic5a06a7d1bdb9123a0a242a571f094ac3233d7b2
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79627
Reviewed-by: Tim Van Patten <timvp@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Eric Lai <ericllai@google.com>
When an if block has curly braces, the corresponding else block should
also have curly braces.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie1979873142469b1482097f9b4db487541a1b7a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Since we have chipset devicetrees for all SoCs that include this code in
the build, we can use the DEV_PTR macro instead of using
pcidev_path_on_root to get the device struct pointer. We can also use
the is_dev_enabled function instead of checking the value of the enabled
element of the device struct directly.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5dcd92399e2d3f304352f2170dd3ef8761e86541
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79672
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since we have chipset devicetrees for both SoCs supported by the
Stoneyridge code, we can use the DEV_PTR macro instead of using
pcidev_path_on_root to get the device struct pointer. We can also use
the is_dev_enabled function instead of checking the value of the enabled
element of the device struct directly.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifb787750ebc6aa2fef9d3be0e84e6afcffdc2ac1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79671
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Make it possible to enable C1e from the devicetree by adding
`c1e_enable`. C1e was disabled by ea2a38be32
for all RPL SOCs to reduce noise.
This will ensure that boards that disabled it based on CPUID are unchanged.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I758621393cb39345c2ba7b19a32872e84e1c5a19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77088
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Identify PCH type by LPC device ID. This allows to identify
the PCH without including northbridge headers.
Tested: Lenovo X220 still boots.
Change-Id: Ic3e15c1d8d4b1d1012d6204cc65de92d91431fbe
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79145
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This is a preparation to make the next patch result in identical images
for timeless builds and also aligns Zork's DSDT more with Guybrush's
DSDT.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I46835b404be13f150c68680afb3fcc78639e08f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79652
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
For RMT build, add kconfig option to enforce Plan Of Record
restriction on DDR5 frequency & voltage settings.
Change-Id: Ibfcaaf47fec3bd5d8a858309918b3af2f8d976e9
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Add and use defines for 6 series and 7 series PCH PCH IDs.
Change-Id: I4de37d5817766b9bc4f5c2d4d472d3c456b14b29
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79546
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use same indent levels for switch/case in order to comply with the
linter.
Change-Id: I64361262e5b16419351fa139c8fdf04c5c07662d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The master is deprecated in favor of the main.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I58001819079bc880e8cde1c3a6756ff6c8a1c016
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This southbridge can route POST codes written to port 0x80 to either
LPC or PCI, but currently always route them to LPC. Change it so that
POST codes are routed to PCI if CONFIG(POST_DEVICE_PCI_PCIE) is
selected, LPC otherwise.
Rename the static function because POST codes no longer always go to
LPC.
Change-Id: I455d7aff27154d6821e262a21248e8c7306e2d61
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
update DTT settings for thermal control,the values before
Sensor1 and Sensor2 were set too high. Modify the protection
temperature to better meet DUT requirements.
BUG=b:291217859
BRANCH=none
TEST=emerge-rex coreboot
Change-Id: I8abc866c0d05a2437c34198e6b8fb4a58c1cb829
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79683
Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This patch follows the BWG recommendation (doc 729123) by clearing
the SPI SYNC_SS bit before disabling the WPD bit in
SPI_BIOS_CONTROL. This prevents boot hangs due to a 3-strike error.
Unable to follow this guideline would result into boot hang
(3-strike error).
BRANCH=firmware-rex-15709.B
TEST=Able to build and boot google/rex.
Change-Id: I18dbbc92554d803eea38ceb0b936a9da9191cb11
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Previous sleep state showing in serial log is a magic number.
In order to let users understand its meanings directly, add
the strings to describe the modes.
TEST=build, boot the device and check the logs:
without this change, the log is like:
[DEBUG] prev_sleep_state 0
with this change:
[DEBUG] prev_sleep_state 0 (S0)
Change-Id: Iabe63610d3416b3b6e823746e3ccc5116fabb17d
Signed-off-by: Marx Wang <marx.wang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78999
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
According to datasheet, EN_TCHSCR_PWR high --> SOC_TCHSCR_RST_R_L high
should over 5ms. And current measure result is 200us.
Set EN_TCHSCR_PWR to output high in bootblock to make it meet datasheet
requirment.
Measurement result of EN_TCHSCR_PWR high --> SOC_TCHSCR_RST_R_L high:
Power on --> 31.7 ms
Resume --> 38.7 ms
BUG=b:314245238
TEST=Measure the sequence
Change-Id: I56e455a980b465f27794b30df058ec0944befc2e
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79571
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Meteor Lake CPUs physical address size is 46 if TME is disabled, 42 if
TME is enabled but Meteor Lake SoC physical address size is always
42.
BUG=b:314886709
TEST=MTRR are aligned between coreboot and FSP
Change-Id: Ic63c93cb15d2998e13d49a872f32d425237f528a
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79666
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The physical address size of the System-on-Chip (SoC) can be different
from the CPU physical address size. These two different physical
address sizes should be used for settings of their respective field.
For instance, the physical address size related to the CPU should be
used for MTRR programming while the physical address size of the SoC
should be used for MMIO resource allocation.
Typically, on Meteor Lake, the CPUs physical address size is 46 if TME
is disabled and 42 if TME is enabled but Meteor Lake SoC physical
address size is always 42. As a result, MTRRs should reflect the TME
status while coreboot MMIO resource allocator should always use
42 bits.
This commit introduces `SOC_PHYSICAL_ADDRESS_WIDTH' Kconfig to set the
physical address size of the SoC for those SoCs.
BUG=b:314886709
TEST=MTRR are aligned between coreboot and FSP
Change-Id: Icb76242718581357e5c62c2465690cf489cb1375
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79665
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add probe DB_C_A_LTE/DB_C_A for Type-C Port C1 (daughter board).
DB_A is only used for skus without Type-C Port C1.
BUG=b:316048649
TEST=emerge-nissa coreboot
Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Change-Id: Ifb702c497740953144b43c56653da16fade1053f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79629
Reviewed-by: Kyle Lin <kylelinck@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Some GPIOs were not configured correctly according to the HW
spreadsheet provided by the HW team.
* GPP_B5/GPP_B6 use NF1, not NF2
* GPP_B23 should use NF2, no GPI
* GPP_D11 should be set to NC
* GPP_E21/22 should be using NF (previous NC)
* GPP_F17 is a GPO
* GPP_F18 should be an interrupt, not a NF
BUG=b:300690448,b:316180020
BRANCH=NONE
TEST=emerge-brox coreboot
Change-Id: I9e1e62adb79bd7fdab935afdbf2d23f9061b88aa
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Did a pass through HW team's brox speadsheet and aligned the gpio.c
file with it. The changes in this CL are to fix the pad's reset field
as needed. See "Intel SoCs" section in
https://doc.coreboot.org/getting_started/gpio.html for reset
definitions.
BUG=b:300690448,b:316180020
BRANCH=NONE
TEST=emerge-brox coreboot
Change-Id: I4285136184c648adb9dc97748bd6b01cba3f8ddd
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Did a pass through HW team's brox speadsheet and aligned the gpio.c
file with it. The changes in this CL include fixing the pulls for
GPIOs as necessary, making sure that it matches what is in the HW
team's spreadsheet.
BUG=b:300690448
BRANCH=NONE
TEST=emerge-brox coreboot
Change-Id: Ie50cb3c6fc85f1633c1afd1330c0e040e04b0ec1
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79704
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Did a pass through HW team's brox speadsheet and aligned the gpio.c
file with it. The changes here include changing the pad config to NC
because it is not being used in ChromeOS.
BUG=b:300690448
BRANCH=NONE
TEST=emerge-brox coreboot
Change-Id: I15471e4d7ff25c858b05ef024f15ca7c0b9e598e
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79703
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
datasheet: https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20221129/DS-00562-GD25LQ255E-Rev1.1.pdf
BUG=b:311336475
BRANCH=firmware-rex-15709.B
TEST=Build AP-firmware and test on karis, system can boot to OS.
Change-Id: Id952ba3a4a45a51571d3735cf6b5764cece2c5e4
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79087
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Patrick Georgi