BIOS Vendor in SMBIOS Type 0 would be who built the firmware so create a
config string with default "coreboot" to make it changeable. Vendors
could update it by adding a Kconfig in the site-local directory.
Change-Id: I6dfcca338ffc48b150c966b9aefcefe928704d24
Signed-off-by: Yiwei Tang <tangyiwei.2022@bytedance.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75737
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
No matter what DRAM calibration is performed, DRAM scramble should be
enabled as long as MEDIATEK_DRAM_SCRAMBLE is set to y. Currently, DRAM
scramble is enabled only if full calibration is performed. Correct the
behavior by adding DRAMC_CONFIG_SCRAMBLE to the header config in fast
calibration flow.
BUG=b:285474337
TEST=Check the scramble feature is disabled on serial build
Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com>
Change-Id: I907bccd4e68e040179e1971db6bf7a57b88dec1b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75818
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Description of POST_EXIT_PCI_SCAN_BUS indicates the opposite of what
its name suggests. Secondly, POST_ENTER_PCI_SCAN_BUS and
POST_EXIT_PCI_SCAN_BUS have identical comments, which appears to be
a copy-paste issue.
Change the description accordingly.
Change-Id: Ifc920651255bacf033cac39f0208d817f9ee84fc
Signed-off-by: lilacious <yuchenhe126@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76047
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Zero-initialize the ivhd_hpet struct right at the beginning of the
ivhd_describe_hpet function to make sure that the whole struct is in a
defined state.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If4d3563c485eed4a7cb0526a62f7b6c80f763bfd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76074
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Allow the caller to specify the HID that gets written to the
ivrs_ivhd_f0_entry_t struct.
TEST=None
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I830f1fbbd535b100c88997ece10142a5d553950f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76073
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Zero-initialize the ivhd_f0 struct right at the beginning of the
ivhd_describe_f0_device function to make sure that the whole struct is
in a defined state.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia6750b58dacb9b9192ed21128eb6e3a4495b96d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
The eMMC entry in the IVRS table should only be generated if an eMMC
controller is present in the SoC.
Where the PCI_DEVFN(0x13, 1) is from is currently unclear to me. There
is no PCI device 0x13 on bus 0 and the eMMC controller is also an MMIO
device and not a PCI device, but this is what the reference code does.
My guess would be that it mainly needs to be a unique PCI device that
won't collide with any existing PCI device in the SoC. Add a comment
about this too.
TEST=None
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I00865cb7caf82547e89eb5e77817e3d8ca5d35dd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Commit d054bbd4f1 ("Makefile.inc: fix multiple jobs build issue")
added a dependency on $(obj)/fmap_config.h to all .c source files in all
stages, so it's not needed any more to add it as a dependency to files
that include fmap_config.h.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7b62917f32ae9f51f079b243a606e5db07ca9099
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76002
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Add JSL SKUs ID and add PLx from JSL PDG in project devicetree.
BUG=b:281479111
TEST=emerge-dedede coreboot and read correct value on dibbi
Signed-off-by: Chia-Ling Hou <chia-ling.hou@intel.com>
Change-Id: Ic086e32a2692f4f5f9b661585b216fa207fc56fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75679
Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com>
Reviewed-by: Super Ni <super.ni@intel.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Configures ISH related GPIO's based on FW_CONFIG obtained from CBI.
BUG=b:280329972,b:283023296
TEST= Set bit 21 of FW_CONFIG with CBI
Boot rex board
Check that ISH is enabled, loaded, and functional
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: I3f0f9a7c8318fa9ae59b6f613eafdacbfa07c749
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75525
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
The prefix POSTCODE makes it clear that the macro is a post code.
Hence, replace related macros starting with POST to POSTCODE and
also replace every instance the macros are invoked with the new
name.
The files was changed by running the following bash script from the
top level directory.
sed -i'' '30,${s/#define POST/#define POSTCODE/g;}' \
src/commonlib/include/commonlib/console/post_codes.h;
myArray=`grep -e "^#define POSTCODE_" \
src/commonlib/include/commonlib/console/post_codes.h | \
grep -v "POST_CODES_H" | tr '\t' ' ' | cut -d ' ' -f 2`;
for str in ${myArray[@]}; do
splitstr=`echo $str | cut -d '_' -f2-`
grep -r POST_$splitstr src | \
cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g";
grep -r "POST_$splitstr" util/cbfstool | \
cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g";
done
Change-Id: I25db79fa15f032c08678f66d86c10c928b7de9b8
Signed-off-by: lilacious <yuchenhe126@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Rename shared SRAM aliases for IOE and PMC to make them more readable.
pci device 13.3 is IOE shared sram, renamed to ioe_shared_sram.
pci device 14.2 is PMC shared sram, renamed to pmc_shared_sram.
Rename them in SOC code as well as mainboard to make sure the patch
builds for the relevant boards.
BUG=b:262501347
TEST=Able to build.
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Change-Id: I02a8cacc075f396549703d7a008382e76258f865
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75999
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The CNVi PCI device is required for the system to boot properly.
By ensuring that this device is enabled, we can prevent the below
error message from appearing and ensure that the system boots successfully.
BUG=b:274421383
TEST=Able to build and boot google/ovis without any error.
w/o this patch:
[ERROR] CNVi WiFi is enabled without CNVi being enabled
[ERROR] CNVi BT is enabled without CNVi being enabled
Change-Id: I4dbae14f0cfccf96a33437a0e2fdefb508209354
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
This patch introduces a newer config to store the CSE RW FW version into
the CBMEM. Prior to that CSE RW FW version was fetched unconditionally
and ended up increasing the boot time by 7ms to 20ms depending on the
SoC arch (including CSE arch).
The way to retrieve the CSE firmware version is by sending the HECI
command to read the CSE Boot Partition (BP) info. The cost of sending
HECI command to read the CSE FW version is between 7ms-20ms (depending
on the SoC architecture) hence,ensure this feature is platform specific
and only enabled for the platformthat would like to store the CSE version into the CBMEM.
TEST=Build and boot google/rex to avoid getting CSE RW FW version
to save 18ms of the boot time.
w/o this patch:
10:start of ramstage 722,215 (43)
17:starting LZ4 decompress (ignore for x86) 741,415 (19,200)
w/ this patch:
10:start of ramstage 722,257 (43)
17:starting LZ4 decompress (ignore for x86) 723,777 (1,520)
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I94f9f0f99706724c7d7e05668390f3deb603bd32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Add the HSPHY region required by INCLUDE_HSPHY_IN_FMAP option. It is
needed in case CSME/HECI is disabled or not visible to keep the
PCIe 5.0 root ports functional.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ic4793fc9457f58e914ef3e18cce1294f230462bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68988
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The patch adds a possibility to cache the PCIe 5.0 HSPHY firmware in
the SPI flash. New flashmap region is created for that purpose. The
goal of caching is to reduce the dependency on CSME and the HECI IP
LOAD command which may fail when the CSME is disabled, e.g. soft
disabled by HECI command or HAP disabled. This change allows to
keep PCIe 5.0 root ports functioning even if CSME/HECI is not
functional.
TEST=Boot Ubuntu 22.04 on MSI PRO Z690-A and notice PCIe 5.0 port
is functional after loading the HSPHY from cache.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I5a37f5b06706ff30d92f60f1bf5dc900edbde96f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68987
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Most arguments taken from the Kconfig help. RAM needs to be >= 531M,
as coreboot is linked to reside between 512M..531M.
Tested `make qemu` with QEMU 7.2.0.
Change-Id: Id7f23918a786bc126188d5caf285e9f532dbb0ed
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
When moving the code to allocate at the top level in commit 9260ea60bf
(allocator_v4: Use memranges only for toplevel), a call to restrict the
limit of the resource was dropped. Probably by accident in one of the
earliest rebases. Without this call to effective_limit(), 64-bit resour-
ces at the top level, i.e. PCI bus 0, were always placed above 4G. Even
when this was not requested with the IORESOURCE_ABOVE_4G flag.
Tested on kontron/ktqm77 where the issue could be reproduced with
x86_64. Without the fix, boot hangs when trying to access the GMA
MMIO registers of PCI 00:02.0, which were placed above 4G.
Change-Id: Ied3a0695ef5e91f092bf2d442c1c482057643483
Signed-off-by: Nico Huber <nico.h@gmx.de>
Found-by: 9elements QA
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76090
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch introduces CBMEM ID to store the MRC version (similar to
existing implementation that stores the FSP-M version inside CBMEM ID)
inside cbmem so the version information is available across the
different coreboot stages. For example:
* romstage: Use the CBMEM ID version information to check if the MRC
cache is valid and need to erase the MRC cache
* ramstage: Use the CBMEM ID to store the MRC cache into the
non-volatile space.
BUG=b:261689642
TEST=Able to build and boot google/rex and dump the MRC version as
below.
cbmem --list
CBMEM table of contents:
NAME ID START LENGTH
...
21. MRC VERSION 5f43524d 75ffeb60 00000004
...
localhost ~ # cbmem -r 5f43524d | hexdump
00000000 01 12 07 00
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I91f735239b33c6f8ba41c076048903e4b213c6a2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75921
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch uses the "generic" variable name as "version" while storing
the MRC cache data instead referring to the FSP-M version or MRC
version. Hence, updated all the instances of `fsp_version/fspm_version`
with `version`.
Also introduces the new option to the MRC cache
version that allows SoC users to store the MRC cache version based on
the supported EDK2 version. Intel FSP built with EDK2 version 202302
onwards has support to retrieve the MRC version by directly parsing
the binary.
Additionally, added the helper function `fsp_mrc_version()` and
corresponding header file to read the MRC version from the FSP binary.
BUG=b:261689642
TEST=Able to build and boot google/rex and google/omnigul.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ia8af53aed674ad4a3b426264706264df91d9c6b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75920
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
SMBIOS is not specific to architecture, and this is mostly a generic
implementation. Therefore, move it to common code, having
architecture-specific code define some functions to fill this data.
Change-Id: I030c853f83f8427da4a4c661b82a6487938b24e6
Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75886
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
In order to clean up the post code macros, move them to a separate
header away from unrelated code. The new header file is included in
the file where the post codes are moved out of, so that the current
state remains unchanged.
Change-Id: I28a932ce071488e90000e1bbd30b4d739a4bae43
Signed-off-by: lilacious <yuchenhe126@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Run with "-device pci-bridge,chassis_nr=1" argument to add a bridge and
see that it gets found and picked up by the resource allocator.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Iad5d87731066a4009d2c4930a01bc15543d9447a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75925
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
update_bridge_resource() already gets the type passed as part of
the resource.
Change-Id: I6b3c9809caecdd1bad5b98891a00c3392190a3e0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Inline functions that are only called once to improve readability. The
calling functions still have rather short bodies, and the reader won't
have to look down yet another layer to understand what they are doing.
Change-Id: Ib4aa5d61dfa88c804a1aaee028185e00c5fbb923
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Factor all the resource printing out into separate functions.
This results in one-liners in the actual program code which
hopefully will distract less during reading.
Change-Id: I766db379f3b62d641cb3c41ebe0394b60ba57f7a
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65421
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
During phase 1 of the resource allocation we gather all the size
requirements. Starting from the leafs of our devicetree, we cal-
culate the requirements per bus, until we reach the resource do-
main.
However, because alignment plays a role, we can't just accumulate
the sizes of all resources on a bus. Instead, we already sort all
the resources per bus to predict their relative placement, inclu-
ding alignment gaps. Then, phase 2 has to perform the final allo-
cations with the exact same relative placement.
This patch introduces a very simple mechanism to avoid repeating
all the calculations: In phase 1, we note the relative `base` of
each resource on a bus. And after we allocated all the resources
directly below the domain in phase 2, we add the absolute `base`
of bridge resources to the relative `base` of child resources.
This saves most of the computational complexity in phase 2. How-
ever, with a shallow devicetree with most devices directly below
the domain, this won't have a measurable impact.
Example after phase 1:
domain
|
`-- bridge #0
| res #0, base 0x000000 (relative),
| size 12M, align 8M
|
|-- device #0
| res #1, base 0x800000 (relative),
| size 4M, align 4M
|
`-- bridge #1
| res #2, base 0x000000 (relative),
| size 8M, align 8M
|
`-- device #1
res #3, base 0x000000 (relative),
size 8M, align 8M
After phase 2 allocation at the domain level (assuming res #0 got
0xa000000 assigned):
domain
|
`-- bridge #0
| res #0, base 0xa000000 (absolute),
| size 12M, align 8M
|
|-- device #0
| res #1, base 0x800000 (relative),
| size 4M, align 4M
|
`-- bridge #1
| res #2, base 0x000000 (relative),
| size 8M, align 8M
|
`-- device #1
res #3, base 0x000000 (relative),
size 8M, align 8M
Now, all we need to do is to add the `base` of bridge resources
recursively. Starting with resources on the bus below bridge #0:
domain
|
`-- bridge #0
| res #0, base 0xa000000 (absolute),
| size 12M, align 8M
|
|-- device #0
| res #1, base 0xa800000 (absolute),
| size 4M, align 4M
|
`-- bridge #1
| res #2, base 0xa000000 (absolute),
| size 8M, align 8M
|
`-- device #1
res #3, base 0x000000 (relative),
size 8M, align 8M
And finally for resources on the bus below bridge #1:
domain
|
`-- bridge #0
| res #0, base 0xa000000 (absolute),
| size 12M, align 8M
|
|-- device #0
| res #1, base 0xa800000 (absolute),
| size 4M, align 4M
|
`-- bridge #1
| res #2, base 0xa000000 (absolute),
| size 8M, align 8M
|
`-- device #1
res #3, base 0xa000000 (absolute),
size 8M, align 8M
Change-Id: I70c700318a85f6760f27597730bc9c9a86dbe6b3
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65420
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
We currently have two competing mechanisms to limit the placement of
resources:
1. the explicit `.limit` field of a resource, and
2. the IORESOURCE_ABOVE_4G flag.
This makes the resource allocator unnecessarily complex. Ideally, we
would always reduce the `.limit` field if we want to "pin" a specific
resource below 4G. However, as that's not done across the tree yet,
we will use the _absence_ of the IORESOURCE_ABOVE_4G flag as a hint
to implicitly lower the `limit` of a resource. In this patch, this
is done inside the effective_limit() function that hides the flag
from the rest of the allocator.
To automatically place resources above 4G if their limit allows it,
we have to allocate from top down. Hence, we disable the prompt for
RESOURCE_ALLOCATION_TOP_DOWN and turn it on by default. Platforms
that are incompatible should be fixed, but can also override the
default as a temporary measure.
One implication of the changes is that we act differently when a
cold-plugged device reports a prefetchable resource with 32-bit
limit. Before this change, we would fail to allocate the resource.
After this change, it forces everything on the same root port below
the 4G line.
A possible solution to get completely rid of the IORESOURCE_ABOVE_4G
flag would be rules to place resources of certain devices below 4G.
For instance, the primary VGA device and storage and HID devices
could be made available to a payload that can only address 32 bits.
For now, effective_limit() provides us enough abstraction as if the
`limit` would be the only variable to consider. With this, we get
rid of all the special handling of above 4G resources during phase 2
of the allocator. Which saves us about 20% of the code :D
An earlier version of this change (commit 117e436115) had to be
reverted because of missing resource reservations in platform code.
This is worked around now with commit ae81497cb6 (device/pci:
Limit default domain memory window).
Change-Id: Ia822f0ce648c7f7afc801d9cb00b6459fe7cebea
Signed-off-by: Nico Huber <nico.h@gmx.de>
Original-reviewed-on: https://review.coreboot.org/c/coreboot/+/65413
Original-reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reducing the polling time from 16ms to 2ms. Experimentally we
have determined that the link state normally takes approximately
3.5ms to update and therefore we were waiting longer than necessary.
TEST=build and confirm we are not waiting the extended period.
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Change-Id: I8fabb5ac46cae5c92d5b6f1dc0641a4d121c61dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76052
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reduce the delay between PEXVDD and NVVDD from 3ms to 2ms
during power down sequences. The hardware discharge is
aggressive enough that we can safely optimize this.
BUG=b:288267305
TEST=build and measured delay is acceptable
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Change-Id: I7c65301414044487e50bbbca618c4e602e571cfb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76051
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
When powering rails down, there is no value in waiting for the PG
signal to de-assert. Instead, shut the rails off as quickly as possible
while maintaining a controlled ordering.
BUG=b:288266850
TEST=build and measured delays are gone
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Change-Id: If31691a7d62b72661fcbacb34e90f3a6adec8134
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76050
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Pre-boot display is not POR for google/rex hence disable the config
ENABLE_TCSS_DISPLAY_DETECTION.
BUG=b:247670186
TEST=Build and boot to google/rex and make sure that display over TCSS
works in the OS
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Ib55e251a4620c7a375ee2f27763154c39207236e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
For Phoenix the lane numbers in the DXIO descriptor match the ones in
the schematic, so remove the corresponding text and the table from the
comment on the fsp_dxio_descriptor struct. Since there's no logical to
physical lane number remapping needed for the lanes in the Phoenix DXIO
descriptors, drop the 'logical' from the start_logical_lane and
end_logical_lane fields in the DXIO descriptor and rename those to
start_lane and end_lane.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I94664fd9d3807370b73f9fae8645d444e5faf7b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74223
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Since GPP_C03/GPP_04 are floating in HW design, we set HBR smbus pin
as NC, in case it prevents ese and cse from entering suspend.
BUG=b:283053968
TEST=Verified on screebo non-TBT SKU, suspend and resume works.
Change-Id: I401db32f0286de61ce3ab6c61de9528ec76cb51d
Signed-off-by: Simon Zhou <zhouguohui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75643
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Make the default MEDIATEK_DRAM_SCRAMBLE value overridable by adding a
prompt string.
BUG=b:285474337
TEST=build pass and check scramble feature is disabled on serial build
Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com>
Change-Id: I703ac9aa3ccc4dd9d0fef9949c6b0d49449971a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75815
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds the initial code for adlrvp_rpl variant board
which includes
1. Add overridetree.cb to corresponding variant directory
2. Update mainboard name in Kconfig and Kconfig.name
3. Add config option to select corresponding overridetree.cb
BUG=b:286030718
BRANCH=firmware-brya-14505.B
TEST=Able to build with the patch and boot the adlrvp_rpl platform
to ChromeOS on Windows SKU.
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: Ifb95ff705189863d23894769ff450f9528e73b14
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73962
Reviewed-by: Usha P <usha.p@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
USB type-A port with same PLD.token information as USB type-C port,
causes conflict while generating ACPI code for the EC CONN device.
Use a different PLD.token number for type-A port to fix the issue.
BUG=b:286328285
TEST=check ACPI can have right USB port in EC CON.
before patch:
Package (0x02)
{
"usb2-port",
\_SB.PCI0.XHCI.RHUB.HS01
},
Package (0x02)
{
"usb3-port",
\_SB.PCI0.TXHC.RHUB.SS01
},
after patch:
Package (0x02)
{
"usb2-port",
\_SB.PCI0.XHCI.RHUB.HS01
},
Package (0x02)
{
"usb3-port",
\_SB.PCI0.TXHC.RHUB.SS03
},
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: If3e76c11dd6808eee4c9c2f3f71604a60379b5a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75911
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
This patch renames config `SOC_INTEL_METEORLAKE_U_P` to
`SOC_INTEL_METEORLAKE_U_H` as per Intel Meteor Lake Processor EDS
version 1.3.1 (doc number: 640228).
With new branding, the MTL-U/H-Processor Line offered in a 1-chip platform that includes the Compute, SOC, GT, and IOE tile on the
same package.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I032be650bbfef0bf0ef86bb37417b1d854303501
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75931
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
DDR5 spd is not supported read by coreboot. But FSP can read it,
so print the memory information from smbios type17 dimm information.
TEST=check the coreboot log.
memory Channel-0-DIMM-0 type is DDR5
memory part number is MTC8C1084S1SC56BG1
memory max speed is 5600 MT/s
memory speed is 5200 MT/s
memory size is 16384 MiB
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I2b5ca1f4a59598531a6cba500672c2717f2a7b00
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75756
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
get_usb_port_references refer the PLD group. If the port assign cross
ports like mux[0] use USB3 and mux[1] use USB1, then we need set USB3
to group 1. Update the PLD panel to back as well.
BUG=b:286328285
TEST=check ACPI can have right USB port in EC CON.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I97517ecd4f8615af749fb6d007ded8e171796f7c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75912
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Using the boolean type and the true/false macros give the reader a
better understanding about the option. Thus, use the bool type for the
attribute and use the macros for assignments.
Skylake mainboards which use that option were changed by the following
command ran from the root directory.
socs="SOC_INTEL_(SKYLAKE|KABYLAKE|SKYLAKE_LGA1151_V2)" && \
option="s0ix_enable" && \
grep -Er "${socs}" src/mainboard | \
cut -d ':' -f 1 | \
awk -F '[/]' '{print $1"/"$2"/"$3"/"$4}' | \
xargs grep -r "${option}" | \
cut -d ':' -f 1 | \
xargs sed -i'' -e "s/${option}\".*\=.*\"1\"/${option}\" \= true/g"
Change-Id: I372dfb65e6bbfc79c3f036ce34bc399875d5ff16
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75871
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Hao Wang