Setting the PM_ESPI_CS_USE_DATA2 bit in PM_SPI_PAD_PU_PD results in the
eSPI transactions being sent via the SPI2 pins instead of the SPI1 pins.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iad8e3a48496a52c14c936ab77c75dc1b403f47bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The name looked a bit odd and the Cezanne PPR #56569 Rev 3.03 confirmed
that the native function names don't have the EMMC_ prefix.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I917c74afd98f2e2133e160d352f11f08c19a3ec6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This makes this header file consistent with the rest.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ice2872b4a24032d3a65777795943602cd2595de7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58864
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The HECI device needs to be enabled to send the commands to have the
CSME change between Soft Temporary Disable mode and Normal mode.
Change-Id: I668507e3b522137bcc827aa615dab1fccd1709a0
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Introduce the `AZALIA_VERB_12B` macro to encode HDA commands with 12-bit
verb identifiers and rewrite existing helper macros to use it.
Tested with BUILD_TIMELESS=1, Purism Librem Mini remains identical.
Change-Id: I5b2418f6d2faf6d5ab424949d18784ca6d519799
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
MT8186 requires writing speical value to mode register to clear
status register. The flow of clear status is different from other
platforms, so we override mtk_wdt_clr_status() for MT8186.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I290b69573a8e58db76814e16b5c17c23413f1108
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58835
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
mtk_wdt_clr_status is different for MT8186 and MT8195,
so we move this function to soc folder.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ia8697ffdca1e2d1443f2259713c4ab6fdf1b1a9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58834
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Somehow missed renaming those when creating the coreboot support for
Cezanne.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I13c28f67d32ba987987cfc2b45e248d535ccdca9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
When the mp_init_with_smm call returns a failure, coreboot can't just
continue with the initialization and boot process due to the system
being in a bad state. Ignoring the failure here would just cause the
boot process failing elsewhere where it may not be obvious that the
failed multi-processor initialization step was the root cause of that.
I'm not 100% sure if calling do_cold_reset or calling die_with_post_code
is the better option here. Calling do_cold_reset likely here would
likely result in a boot-failure loop, so I call die_with_post_code here.
BUG=b:193809448
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifeadffb3bae749c4bbd7ad2f3f395201e67d9e28
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The comments are not correct anymore. With AGESA there is no need to
synchronize TOM_MEMx msr's between AP's. It's also not the best place
to do so anyway.
Change-Id: Iecbe1553035680b7c3780338070b852606d74d15
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
AGESA sets up MTRRs so these functions are now unused.
Change-Id: Ic2bb36d72944ac86c75c163e130f1eb762a7ca37
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The line length is no longer limited to 80 characters, so there's no
need for that line break any more.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7a8fb472f00e039f25a71ee526a3dd0bc6c754f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Disable the PM ACPI timer during PMC init, when `USE_PM_ACPI_TIMER` is
disabled. This is done to bring SKL, CNL, DNV in line with the other
platforms, in order to transition handling of the PM timer from FSP to
coreboot in the follow-up changes.
Disabling is done in `finalize` since FSP makes use of the PMtimer.
Without PM Timer emulation disabling it too early would block.
Change-Id: If85c64ba578991a1b112ceac7dd10276b58b0900
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
Allow devicetree override to leave ac_loadline, dc_loadline and icc_max as default.
Test=Boot to OS
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I715345d5ea83aed9ee929b2a4e13921c9d8895b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
All supported AMD CPUs support getting the physical address size from cpuid so
there is no need for a Kconfig default value.
Change-Id: If6f9234e091f44a2a03012e7e14c380aefbe717e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58686
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This method will add a node to the end of the list.
BUG=b:179699789
TEST=Boot guybrush to the OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I1792e40f789e3ef16ceca65ce4cae946e08583d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Add new folder and basic drivers for Mediatek SoC 'MT8186'.
Difference of modules including in this patch between MT8186 and existing SoCs:
Timer:
Similar to MT8195, MT8186 uses v2 timer.
EMI/PLL/SPI:
Different from existing SoCs.
TEST=boot from SPI-NOR and show uart log on MT8186 EVB
BUG=b:200134633
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I579f79c15f4bf5e1daf6b35c70cfd00a985a0b81
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58640
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some enum variables of timer v2 are the same between MT8195 and MT8186,
so we move them to common timer_v2.h.
TEST=emerge-cherry coreboot
BUG=b:200134633
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I89891a19e622aa24783025e73c38c4ffa43aa166
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58829
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If ran with obj=/absolute path, then tests were failing to execute
because the recipe tried running `.//absolutepath/...run`.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I9c3638b1af7531dbe8e956dcbe168250a235ead4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
On mc_ehl1 there are three of the 6 PCIe clocks used to drive PCIe
devices. None of the used clock output is dedicated to a special device
(CLK0 drives several devices on the mainboard, CLK1 and CLK2 are
connected to a PCIe switch). Therefore do not use a port mapping of the
clocks to avoid a stopping clock once a device is missing and the
matching root port is disabled. Instead set the mapping to
'PCIE_CLK_FREE' to have a free running clock.
In addition, use the defined constant 'PCIE_CLK_NOTUSED' instead of the
value 0xFF to disable the CLKREQ-feature and unused clocks.
Change-Id: I2beea76ff8fefd79f476bef343d13495b45cdfcf
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58740
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Oryx Pro 6 has the same board layout as the next model in series,
Oryx Pro 7. The primary difference between the two is the dGPU (20
series to 30 series). Convert oryp6 to a variant setup in preparation
for adding the oryp7.
Change-Id: I976750c7724d23b303d0012f2d83c21a459e5eed
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57786
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Order functionally:
* first "all" and build-$tools
* followed by clean
* followed by the architecture targets
The order was chosen this way because the architecture targets are
the mostly likely to continue to grow.
While at it, also fix the build_nasm mention (it was build-nasm)
and add build_make.
Change-Id: Id58338a512d44111b41503d4c14c08be50d51cde
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58796
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PCI_DEVICE_ID_AMD_FAM17H_LPC and PCI_DEVICE_ID_AMD_FAM17H_SMBUS redefine
the same values that are already defined by PCI_DEVICE_ID_AMD_CZ_LPC and
PCI_DEVICE_ID_AMD_CZ_SMBUS, so drop PCI_DEVICE_ID_AMD_FAM17H_LPC and
PCI_DEVICE_ID_AMD_FAM17H_SMBUS. Also add some comments to the places in
the code where the defines are used to clarify which ID is used on which
hardware generation.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id0b3d7b5a886ccc76d82ada6be4145e85fd51ede
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Enable MKBP (Matrix Keyboard Protocol) interface for all volteer family
to use for buttons and switches. Disable TBMC (Tablet Mode Switch
device), as it is not needed anymore.
BUG=b:171365305
TEST=manual test on Volteer:
Volume Up/Down and Power buttons, Tablet Mode switch
Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I2bb2e895af17fa4280113e57e2b0ca780af8840e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Boris Mittelberg <bmbm@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
EC_IN_RW signal from EC GPIO is connected to GPIO E7 of SOC. This GPIO
can be used to check EC status
trusted (LOW: in RO) or untrusted (HIGH: in RW).
Branch=none
Bug=none
Test=Issue manual recovery and confirm DUT is entering recovery mode on
ADL-M RVP.
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: I20804db450ab0b3ebe19c51ba2b294a0137d81a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Update guybrush STT (Skin Temperature Tracking) configuration settings
to values provided by power team after tuning.
BUG=b:203123658
Change-Id: I14c69dbe044e4f3f2711be96e5ea80db0686b3eb
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Our boards do not boot if power_on_after_fail=Disable. Drop the option
and use the default of powering on.
Change-Id: Ia1857e52f838337048f79f8ca5c12d669cae321a
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
This change adds the cbfs_cache region into the x86 memlayout. The SoC
or mainboard can decide how big the region should be by specifying
CBFS_CACHE_SIZE.
BUG=b:179699789
TEST=Build guybrush and verify cbfs_cache region wasn't added.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I268b6bc10906932ee94f795684a28cfac247a68c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Addresses in AMD fw table with EFS gen2 are relative addresses, but
PSP doesn't accept relative addresses in update_psp_bios_dir().
Check for EFS gen2 and convert them as needed.
BUG=b:194263115
TEST=build and boot on guybrush and shuboz
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I95813beba7278480e6640599fcf7445923259361
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Felix Held