Commit Graph

23465 Commits

Author SHA1 Message Date
Richard Spiegel 67c2a7b487 soc/amd/common: Add DRAM clear option to northbridge.c
AmdInitPost() can be instructed to clear DRAM after a reset or to
preserve it. Use SetMemParams() to tell AGESA which action to take.

Note that any overrides from OemPostParams (OemCustomize.c) are not
affected by this change.

Change-Id: Ie18e7a265b6e0a00c0cc8912db6361087f772d2d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/21856
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-10 18:22:53 +00:00
Subrata Banik 185988234d soc/intel/cannonlake: Remove structure variable initialization with 0
Variable without an initializer will default to 0 hence no
need of an explicit initialization.

Change-Id: I208d5e475600b102cd3d972919b170c10c790b32
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22417
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-10 16:38:05 +00:00
Subrata Banik 05e06cd0be soc/intel/common: Fix CSE common code to accomodate Skylake/Kabylake
This patch ensures Skylake/Kabylake soc can make use of common
CSE code in order to perform global reset using HECI interface.

TEST=Build and boot on soraka/eve/reef/cnl-rvp

Change-Id: I49b89be8106a19cde1eb9b488ac660637537ad71
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-10 16:37:38 +00:00
Subrata Banik 330dc10cfd soc/intel/apollolake: Include HECI BAR0 address inside iomap.h
This ensures HECI1_BASE_ADDRESS macro is coming from respective
SoC dirctory and not hardcoded inside common cse code. As per
firmware specification HECI1_BASE_ADDRESS might be different
between different socs.

Change-Id: I502b5b41b449bb07f14f07435bf311bbd4f943b6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-10 16:37:32 +00:00
Richard Spiegel cb01efcda1 src/soc/amd/stoneyridge/southbridge.h: Fix prototypes
Some prototypes types don't match the actual function type, though there's
no error message due to the types being alias. For clarity, types should
match between prototypes and actual functions.

BUG=b:68007655

Change-Id: I9573a68f7153dbbad2fc6551d5dab000760c871e
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-11-10 16:30:53 +00:00
Ben Chan eeb475c5c8 mainboard/google/coral: power off EN_PP3300_DX_LTE_SOC when entering S5
On Astronaunt, after the system enters the S5 power state, there is a
10-second timeout before the system transitions the power state from S5
to G3. The EN_PP3300_DX_LTE_SOC signal, which is controlled by GPIO_78
on the APL platform, remains on during that period. If the system is
powered back on before going to G3, the built-in modem won't go through
a power cycle as EN_PP3300_DX_LTE_SOC is never de-asserted.

Keeping the modem, and indirectly the SIM, powered during a quick system
power cycle may sometimes be undesirable. For instance, we would like a
SIM with PIN lock enabled to require unlocking each time the system is
powered on. After the SIM receives a PIN, it may remain unlocked until
its next power cycle.

Also, it is often desirable to power cycle the modem when the system
goes through a power cycle. For instance, a user may power cycle the
system to recover a wedged modem.

BUG=b:68365029
TEST=Tested the following on an Astronaunt device:
1. Verify that the modem is powered on after the system boots from cold.
2. Suspend the system to S0ix. Verify that the modem remains powered on
   when the system is in S0ix. After the system goes back to S0, verify
   that the SIM with PIN lock enabled doesn't request unlocking, and the
   modem can quickly reconnect to a network.
3. Configure the system to suspend to S3 instead of S0ix, and then
   repeat (2).
4. Perform a quick system power cycle, verify that the modem is powered
   cycle and the SIM with PIN lock enabled requests unlocking.

Change-Id: Ie60776d5d9ebc6a69aa9e360bd882f455265dfa2
Signed-off-by: Ben Chan <benchan@chromium.org>
Reviewed-on: https://review.coreboot.org/22415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-11-10 09:49:18 +00:00
Aaron Durbin 6f1e8d24af device: untangle device_t from struct device some more
This further allows compilation units to be re-used without
having to add macro guards because of declarations not being
around in the __SIMPLE_DEVICE__ case. These declarations are for
functions that operate on struct device. struct device is a known
type so just expose the functions using the correct type. Also,
DEVTREE_CONST is empty while in ramstage so there's no reason
to separate the declarations. They compile regardless of stage.

Change-Id: Idd4180437d30e7dfaa9f735416c108841e43129f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-11-10 06:33:28 +00:00
Richard Spiegel 7a39e02cfd soc/amd/stoneyridge: Fix and clean lpc.c
Rename set_lpc_resource to set_child_resource. Fix EC child resource not
recognized as already set. Remove code that's not needed.

BUG=b:62200877

Change-Id: I6e2bf9f8214b5f660084ccd622e3fe2c0cba7656
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-11-09 21:49:26 +00:00
Nick Vaccaro 8fc694ff25 mainboard/google/zoombini: add dptf.asl and gpio.h
Add dptf.asl (copied from reef) to baseboard variant includes,
instruct zoombini variant to use the baseboard's dptf.asl,
instruct zoombini variant to use the baseboard's gpio.h.

BUG=b:64395641
BRANCH=None
TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x
-a" compiles successfully.

Change-Id: I9aa37f5afc35dab372917a4c84ff3121ec569546
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/22381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-09 19:12:19 +00:00
Richard Spiegel 3e4aeec5f4 src/soc/amd/stoneyridge/southbridge.h: Remove unused prototypes
Remove unused s3_resume_init_data prototype from southbridge,h

BUG=b:68007655

Change-Id: If022f873813070aac6cc9090c2212178a4e66354
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-09 19:11:26 +00:00
Duncan Laurie 469af7b1d7 drivers/i2c/tpm/cr50: Increase init delay to 30 seconds
In case the TPM is doing a long crypto operation the initial probe
could be very delayed.  Rather than end up in recovery make the delay
long enough to accommodate the (current) long crypto times.

BUG=b:65867313, b:68729265
TEST=Verified that Soraka no longer hangs during EC reboot test.

Change-Id: I3bccff70e001dfc065c24be8ad34ef239a144db1
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-09 19:05:32 +00:00
Nick Vaccaro 605c2dc251 mainboard/google/zoombini: fix EC_SCI_GPI gpio define
Change EC_SCI_GPI to GPE0_ESPI.

BUG=b:69011806
BRANCH=master
TEST=none

Change-Id: I5d07bc0ef295d776635ff3a585c8de9028bd3f6a
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/22380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-09 19:04:23 +00:00
Furquan Shaikh d37107e130 mb/google/{poppy,nautilus,soraka}: Disable deep S3
Poppy and variants won't be using deep S3. This change disables deep
S3 option in devicetree.

BUG=b:69053636

Change-Id: I5fb4a6a0e4216a3648b5ed888f6dc6618f1a9fc4
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22378
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-09 19:02:03 +00:00
Gaggery Tsai 2ecf3f8cb9 mb/google/fizz: Enable NIC leds
This patch enables customized NIC leds as follows:

	Green	Orange (Amber)
100M	off	blinking
1000M	on	blinking

BUG=b:65437780, b:68284778
TEST=Make sure the registers are programmed as expected and observe the
     LEDs are behaving as expected. Perform suspend/resume test and the
     LEDs are still working as expected.

Change-Id: I9bb1367a4c742c2755d620e14ee6dfe70ee7f34b
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/22293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-09 18:39:12 +00:00
Martin Roth e0a6ee8880 mainboard/google/kahlee: Move usb_oc.asl into variant/acpi
This compares to the acpi directory in other variants.

BUG=b:68293392
TEST=Build and boot kahlee

Change-Id: I05d402995b280d6f020bc2575063dbffefa30670
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-09 18:19:11 +00:00
Martin Roth 95afc46382 mainboard/google/kahlee: Define MEM_CONFIG3 for Kahlee variant
Even though this GPIO isn't used for Kahlee, it needs to be defined
so that the weak version of the variant_board_id() function can
compile.

BUG=b:68293392
TEST=Build and boot kahlee

Change-Id: Ia8daf70fbafe02ec37c6b5eb8421cdb11de3be8b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-09 17:23:24 +00:00
Marshall Dawson 07132a4c32 amd/stoneyridge: Add PSP definitions southbridge and iomap
Define the PSP's BAR3 and BAR3 enable bit.  Define a default base
address for BAR3.

Change-Id: I59a0ec59b7c6bbc6468b3096ec8d025832349f44
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-08 21:59:14 +00:00
Marshall Dawson 5f0520a909 amd/stoneyridge: Add SMU firmware blobs to cbfs
Stoney Ridge supports two different sets of SMU firmware, one for
either fanless OPNs and one for fanned.

Add a Kconfig mechanism to select the proper set and add the blobs
into cbfs.

BUG=b:66339938

Change-Id: I8510823e2232b74ec6fe001cc28953f53b2aa520
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-08 21:59:08 +00:00
Marshall Dawson 596ecec009 soc/amd/common/psp: Add command to load fw blobs
An upcoming PSP firmware change will allow coreboot to load the two
SMU firmware blobs (one runs in SRAM and the other in DRAM).  The
traditional method is for the PSP to control most of the process,
e.g. loading the SRAM version prior to releasing the x86 reset.

Add a new command that can instruct the PSP to load a firmware blob
from a location in the flash.

The definition for commands 19 and 1a differ from others in that they
do not use a command/response buffer.  Instead, the PSP will look in
the command/response pointer registers directly for the blob's
address.

BUG=b:66339938

Change-Id: I8431af341930f45ac74f471628b4dc4ede7735f4
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-08 21:58:59 +00:00
Marshall Dawson 154239aff1 amd/stoneyridge: Remove fixme.c
Move the two functions in fixme.c to places where they make more sense.
Coincidentally fix the todo in amd_initcpuio() and use bsp_topmem()
instead of explicitely reading the MSR.

BUG=b:62241048

Change-Id: Ica80b92f48788314ad290ccf72e6847fb6d039c3
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-08 19:24:49 +00:00
Marshall Dawson 22bb2bee60 amd/stoneyridge: Remove amdlib functions from fixme.c
Convert functionality to use coreboot-centric functions and defined
values.  This change should have no functional effect.

BUG=b:62241048

Change-Id: I87b258f3187db4247b291c848b5f0366d3303c75
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-08 19:24:28 +00:00
Marshall Dawson 2d69d75749 amd/stoneyridge: Add northbridge register macros
Add helpers for determining the D18F1 offset for MMIO base and limit,
and I/O base/limit registers.

Change-Id: I3f61bff00b8f3ada3e1bbfb163e1f223708bd47d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-08 19:23:49 +00:00
Shelley Chen b838256a51 google/fizz: add VBOOT_PHYSICAL_REC_SWITCH config
Now that recovery button has been enabled through cr50,
we can add VBOOT_PHYSICAL_REC_SWITCH config and treat
the recovery button like on any other chromebox.

BUG=b:37751915, b:63893483
BRANCH=None
TEST=With DUT in normal mode, boot into recovery, press ctrl+d
     followed by pressing the recovery button.  Should successfully
     boot into dev mode.
CQ-DEPEND=CL:737477

Change-Id: I72fb42508083295e317dd06900796dc0cda753f6
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/22368
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-08 16:26:26 +00:00
Martin Kepplinger 677d261519 payloads/seabios: Update stable from 1.10.2 to 1.10.3
SeaBIOS 1.10.3 was tagged on October 12th, 2017 with the following
changes.

```
$ git log --oneline rel-1.10.2..rel-1.10.3
b7661dd tcgbios: Fix use of unitialized variable
6055583 boot: Increase description size in boot menu
3551613 resume: Don't attempt to use generic reboot mechanisms on QEMU
```

Change-Id: I3a9ebf10a55118fc35aed688ea7ec794333c8227
Signed-off-by: Martin Kepplinger <martink@posteo.de>
Reviewed-on: https://review.coreboot.org/22358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-11-08 15:25:19 +00:00
Maximilian Schander ae848f8719 util/inteltool: Add Skylake definition to MCHBAR reading
Taken from
   * 6th Generation Intel Processor Families for S-Platform 
       Volume 2 of 2
   * Page 56
   * 332688-003EN

Change-Id: I46c8dd77823870b55cc040f7f6c557cb5a2562a1
Signed-off-by: Maximilian Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/22351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-11-08 11:42:45 +00:00
Maximilian Schander 798564333d util/inteltool: Add PCIEXBAR and PXPEPBAR reading for Skylake
Both registers behave the same as on the previous generation

Taken from
 * 6th Generation Intel Processor Families for S-Platform
     Volume 2 of 2
 * Page 55 and 62
 * 332688-003EN

Change-Id: Id02a38a7ab51003c9d0f16ebb2300a16b66a15f9
Signed-off-by: Maximilian Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/22350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-11-08 11:42:26 +00:00
Maximilian Schander 98c11ddc9e util/inteltool: Add Skylake DMIBAR register dumping
Register definitions were taken from
 * 6th Generation Intel Processor Families for S-Platform Volume 2 of 2
 * Page 117
 * 332688-003EN
As well as
 * 6th Generation Intel Processor Families for H-Platform Volume 2 of 2
 * Page 117
 * 332987-002EN

Tested on a 6th gen skylake mobile cpu and capability registers do match up
with the default values.

Change-Id: I636f6c3d045e297f1439d3e88e43f41e03db4c8e
Signed-off-by: Maximilian Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/22345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-11-08 11:42:20 +00:00
Maximilian Schander bf94292522 util/autoport: Fix VGA register warning
The warning is printed using Printf syntax but actually Println is used
resulting in printing the format string first and the arguments second:
"%s. (%s) Default:%s WARNING: [...]"

Change-Id: I411fc47832dd7a82752f233c4909b98190340ccb
Signed-off-by: Maximilian Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/22352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-11-08 11:42:00 +00:00
Naveen Manohar 5bcb23ebbb mb/google/poppy/variants/nautilus: Enable Dialog DA7219 support
Enable Dialog DA7219 codec i2c device and add required SSDT parameters

BUG=b:68686020
TEST=With req'd driver support in kernel v4.4 verify audio on headset

Change-Id: Ic815c929f29bec0d26a2981e9933b752c2d84c70
Signed-off-by: Naveen Manohar <naveen.m@intel.com>
Signed-off-by: Shruthi Sudhakar <shruthi.sudhakar@intel.com>
Reviewed-on: https://review.coreboot.org/22264
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-07 23:37:38 +00:00
Naveen Manohar 351059a0b4 mb/google/poppy/variants/nautilus: add nhlt support
Nautilus board uses Dialog da7219 headset codec,
Select the appropriate NHLT blob to be packaged in CBFS.
Also generate the required ACPI NHLT table for codec
and the supported topology in nautilus.
Removes unwanted DMIC blob pick for nautilus

BUG=b:68686020
TEST=With the required driver support in kernel verify that
the Audio plays on headset and recording on headset mic

Change-Id: I104889f54da1de38854bcb72aabbc88b739d6c09
Signed-off-by: Naveen Manohar <naveen.m@intel.com>
Reviewed-on: https://review.coreboot.org/22325
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-07 23:37:19 +00:00
Naveen Manohar 83670c5176 soc/intel/kabylake: Add Dialog da7219 NHLT blob support
Add APIs and required parameters for creating Dialog da7219 SSP
endpoints in NHLT table.

The use of a NHLT table is required to make audio work
on the kabylake SoCs employing the internal DSP. The table
describes the audio endpoints (render vs capture) along with
their supported formats.

BUG=b:68686020
TEST=check that NHLT table for da7219 is created properly

Change-Id: I57b88873f1c59c8aadf8eec3c80a9d95165a2cc3
Signed-off-by: Naveen Manohar <naveen.m@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/22324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-07 23:37:01 +00:00
Lijian Zhao a5b88e442b intel/cannonlake_rvp: Clean up GPIO programming
Since we move from cannonlake U DDR 4 platform to cannonlake U LPDDR4
platform, it is also critical to revisit the GPIO settings as they are
different. Remove unused GPIO setting for old platform, and clean up the
native function definition. PAD_CFG_NF can only select NF1,NF2 ..., set
to GPIO mode is illegal.

TEST=Boot up in chromeos successfully.

Change-Id: I0022b791bd8459ea2afdcd0241b603ce81408785
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2017-11-07 21:05:27 +00:00
Shaunak Saha d038d53a33 src/mainboard/intel/glkrvp: Fix Lid switch support
SCI trigger logic had to be inverted.
This patch enables the system to wake up from S3 when lid is opened
when the system is in suspend state.We are trying to match what a
external EC card running ChromeEC FW is sending on the signal.

TEST = Verified that system wakes up from S3 on toggling lid switch
back to open state.

Change-Id: Ib42a38088ee028eddc6769921b0552c569da25a9
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/22117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Schander <coreboot@mimoja.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-07 20:28:21 +00:00
Martin Roth 3ce678367c util/release: Update genrelnotes script for 4.7 release
- Fix initial tool check.
- Admit that the script is coreboot specfic.  Remove coreboot check.
- Fix some whitespace issues.
- Get rid of pushd/popd.
- Add keywords for section logging.
- Move code for getting SLOC into a subroutine.
- Find submodules to get patch count instead of having them hardcoded.
- Update specific change areas for 4.7 release

Change-Id: I115659a75604c24780c09605d7643e83e481f6a1
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/22343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-11-07 12:43:32 +00:00
Lann Martin b879ad9dfb mainboard/google/kahlee: Add MAINBOARD_FAMILY
BUG=b:68865273

Change-Id: Ia2e9b10035e9dd502a563cdf8324ea8ea1922db3
Signed-off-by: Lann Martin <lannm@chromium.org>
Reviewed-on: https://review.coreboot.org/22359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-11-07 12:35:10 +00:00
Mario Scheithauer 7ab5dcd5c8 siemens/mc_apl1: Select CONFIG_NC_FPGA_NOTIFY_CB_READY
For internal measurements this mainboard needs a marking inside the NC
FPGA when coreboot is ready and payload has been loaded.

Change-Id: I37908b21e2a077dec7fa99b0db6d1fd9b6878341
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/22356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-11-07 12:34:13 +00:00
Mario Scheithauer a39aedec9d src: Fix all Siemens copyrights
Some Siemens copyright entries incorrectly contain a dot at the end of
the line. This is fixed with this patch.

Change-Id: I8d98f9a7caad65f7d14c3c2a0de67cb636340116
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/22355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-11-07 12:33:51 +00:00
Julien Viard de Galbert 66c210ae37 mainboard/intel/harcuvar: update to set the HSIO lines configuration
Change-Id: Ifc3423ff983fb631edcab087d04742937b25ef86
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/22310
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-07 12:33:18 +00:00
Julien Viard de Galbert f528195bdf soc/intel/denverton_ns: re-factor HSIO configuration
The main goal is to allow configuring the HSIO lines from the mainboard code.
Also share the code for both romstage and ramstage.
Remove explicit dependency on the harcuvar mainboard.

Change-Id: Iec65472207309eae878d14eef5bc644b80fdbb1d
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/22309
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-07 12:32:53 +00:00
Patrick Rudolph 6a81184058 device/device_util: Add string for DEVICE_PATH_NONE
Add string for DEVICE_PATH_NONE in dev_path. The enum DEVICE_PATH_NONE
can be translated to string and shouldn't be translated by
"Unknown device path type: 0".

Makes console output a lot prettier and readable.

Note: DEVICE_PATH_NONE is used on dummy devices for hotpluggable slots.

Change-Id: I08d471d8217f966e80daefe2d9971e357defde62
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/22272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-11-07 12:32:13 +00:00
Maximilian Schander 12217f2878 autoport: Fix nil pointer deref when run without bd82x6x
When autoport is run on a system without supported southbridge
it won't populate the coresponding data structure. By sanitiy
checking after PCI detection autoport can exit cleanly and
provide a sufficient error message.

Error was:
panic: runtime error: invalid memory address or nil pointer dereference
[signal SIGSEGV: segmentation violation code=0x1 addr=0x30 pc=0x4be595]
goroutine 1 [running]:
main.FIXMEEC(0xc42014af80, 0x14, 0xc42014afe0, 0x1a, 0xc4200a914f,
	0x4, 0xc4200a916f, 0xf, 0xc420149e60, 0x28, ...)
/coreboot/util/autoport/ec_fixme.go:14 +0x105

Change-Id: I6b0fcda76d33b0d3a0379c279f492160ce5add84
Signed-off-by: Maximilian Schander <maxschander@googlemail.com>
Reviewed-on: https://review.coreboot.org/22203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2017-11-07 12:31:21 +00:00
Jonathan Neuschäfer 67b3268fac RISC-V boards: Stop using the config string
RISC-V is moving towards OpenFirmware-derived device trees, and the old
functions to read the config string don't work anymore. Use dummy values
for the memory base and size until we can query the device tree.

Change-Id: Ice13feae4da2085ee56bac4ac2864268da18d8fe
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-11-07 12:31:00 +00:00
Jonathan Neuschäfer 5a6e389747 arch/riscv: Use a separate trap stack
This is the lazy solution, as explained in the comment, but it works for
now.

Change-Id: I46e18b6d633280d6409e42462500fbe7c6823b4d
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-11-07 12:30:38 +00:00
Jonathan Neuschäfer c90f1d7be0 arch/riscv: gettimer: Don't use the config string
Accessing the config string doesn't work anymore on current versions of
spike. Thus return dummy pointers until we have a better solution.

Change-Id: I684fc51dc0916f2235e57e36b913d363e1cb02b1
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-11-07 12:30:07 +00:00
Jonathan Neuschäfer 140a827daa arch/riscv: Drop mret workaround
Our toolchain can compile mret now, and once the encoding changes, we'll
have to adjust the code anyway.

Change-Id: Ic37a849f65195006fa15d74f651a8aa9a9da5b5c
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21762
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-11-07 12:29:27 +00:00
Jonathan Neuschäfer 92f0513a0c arch/riscv: mprv_read_*: Mark result as earlyclobber
This fixes a case of mstatus corruption, where GCC generated code that
used the same register for the mprv bit and the result.

GCC inline assembly register modifiers are documented here:
https://gcc.gnu.org/onlinedocs/gcc/Modifiers.html

Change-Id: I2c563d171892c2e22ac96b34663aa3965553ceb3
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-11-07 12:29:08 +00:00
Jonathan Neuschäfer 0c42cd3240 arch/riscv: Fix return type of mprv_read_u64
Change-Id: I3dc12feefe5f0762e27d2ad0234371e91313c847
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-11-07 12:28:37 +00:00
Patrick Rudolph 3dbd28470b lib/ramtest: Add comment
Add a comment about the tested RAM region size.

Change-Id: I29e99a06777bd21a65aa67049ceede4fd8adb603
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/22199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Maximilian Schander <coreboot@mimoja.de>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2017-11-07 12:28:20 +00:00
Bill XIE 54f45c684c ec/lenovo/h8: Clear EC output queue before enablement
Sometimes (observed on Thinkpad T400s during cold boot) a few (only one
observed) garbage bytes may detained in the output queue of EC after power
up, and they should be cleared otherwise later communications will be
disrupted.

Change-Id: Id1733f7350232d0b10ac0d1bc912b62e7fa4da75
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/22181
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Schander <coreboot@mimoja.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-11-07 12:26:51 +00:00
Bill XIE eb4ded6925 ec/acpi: add mechanisms to clear EC output queue
EC's output could be considered as a queue, and sometimes (observed on
Thinkpad T400s during cold boot) a few (only one observed) garbage bytes
may detained in such queue after power up. Those garbage bytes should be
checked and discarded first before real interactions, otherwise they may
disrupt the interaction during EC's enablement, causing a locked rfkill.

Change-Id: Iee031306c02f5211a4512c6b4ec90f7f0db196ae
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/22180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-11-07 12:26:42 +00:00