AMD has rewritten AGESA (now at v9) for direct inclusion into UEFI
build environments. Therefore, unlike the previous Arch2008
(a.k.a. v5), it can't be built without additional source, e.g. by
combining with EDK II, and it has no entry points for easily
building it into a legacy BIOS.
AGESA in coreboot now relies on the FSP 2.0 framework published
by Intel and uses the existing fsp2_0 driver.
* Add fsp_memory_init() to romstage.c. Although Picasso comes out
of reset with DRAM alive, this call is added to maximize
compatibility and facilitate internal development. Future work
may look at removing it. AGESA reports the memory map to coreboot
via HOBs returned from fsp_memory_init().
* AGESA currently sets up MTRRs, as in most older generations.
Take ownership back immediately before running ramstage.
* Remove cbmem initialization, as the FSP driver handles this.
* Add chipset_handle_reset() for compatibility.
* Top of memory is determined by the FSP driver checking the HOBs
passed from AGESA. Note that relying on the TOM register happens
to be misleading when UMA is below 4GB.
BUG=b:147042464
TEST=Boot trembyle to payload
Change-Id: Iecb3a3f2599a8ccbc168b1d26a0271f51b71dcf0
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34423
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Perform the P2SB hide/unhide trick. This is needed so that BAR0
(0xfd000000) is not reclaimed by resource allocator, since it can
not deal with a device that does not exist (hidden).
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Change-Id: I5db0ae4e31d72ba86efba5728b2afc68d3180d5d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Use common P2SB driver. This is needed to address a problem when
enumerator does not see p2sb device (since it is hidden) but it
is active and BAR is decoded.
Change-Id: I9cb821a5684f15f1e1486872bf806a6ee3d0676f
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40920
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These parameters were found to work fine for 2-socket configuration,
for FSP based on tag 16.D.21.
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Change-Id: I466a7f2951ef307036ddaed0be0aacf98dd2710f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40917
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
It is necessary to rename the file gpio.h so that there are no conflict
with another file (src/include/gpio.h)
Change-Id: I4e3ef5882d6cb0ddbcb8357b54106ff2f47e4c51
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40733
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If the current pad configuration can not be defined using standard
macros from the gpio_defs.h [1], then the intelp2m utility generates
"advanced" _PAD_CFG_STRUCT() macros. However, often this configuration
in the vendor’s firmware is erroneous. Change the extended macros to
standard ones taking into account the information based on the schematic
diagram and the previous GPIO configuration for FSP-M [2].
[1] src/soc/intel/common/block/include/intelblocks/gpio_defs.h
[2] src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h
Change-Id: I56e45b1df77acbdd67e6325c3745a7ad137f8805
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40732
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
This format of PCH GPIOs configuration, unlike the raw DW0 and DW1
registers values from the inteltool dump, is more understandable and
makes the code much cleaner. The gpio.h file with PAD_CFG macros was
automatically generated using the util/intelp2m [1] utility:
./intelp2m -p lbg -file tiogapass/vendorbios/inteltool_gpio.log
According to the documentation [2], the Host Software Pad Ownership
register only affects the pads that are configured as input (GPI).
The intelp2m utility takes this into account when converting macros
and ignores bits from this register for the corresponding pads.
[1] https://review.coreboot.org/c/coreboot/+/35643
[2] Intel Document Number: 549921
Change-Id: I21e98721e58b00be9196927837daa2b5d2560822
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40731
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to changes in the soc/xeon_sp code [1,2], server motherboards
with Lewisburg PCH can use the soc/intel/common/gpio driver to configure
GPIO controller. This patch adds pads configuration map, which has the
format required by the GPIO driver. The data for this was taken from the
inteltool register dump with AMI firmware. The gpio.h file with pad
configuration was generated automatically using the util/intelp2m [3]:
./intelp2m -raw -p lbg -file tiogapass/vendorbios/inteltool_gpio.log
[1] https: //review.coreboot.org/c/coreboot/+/39425
[2] https: //review.coreboot.org/c/coreboot/+/39428
[3] https: //review.coreboot.org/c/coreboot/+/35643
Change-Id: I818d040fa33f3e7b94b73c9bbbafca5df424616d
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39427
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since CPX FSP headers are not released yet, populate certain
settings with hard-coded offsets. Provided values are probably
not correct and I do not understand what they mean and there is
no documentation available yet. However they were found to work
to a certain degree.
TEST=tested on OCP Sonora Pass EVT
Change-Id: I0f78cde69cb8a49a388a412b97bf8713e5b380ea
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40554
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Just a minimal set of board files needed to get it to boot
in 1 CPU mode.
Signed-off-by: Ryback Hung <ryback.hung%quantatw.com@gtempaccount.com>
Change-Id: Ia7b45c78b38d091bd9535899b681746e13efb4fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
The AMD64 Architecture Programmer's Manual, Volume 2: Systems
Programming says the following about variable MTRRs:
Variable Range Size and Alignment.
The size and alignment of variable memory-ranges (MTRRs) and I/O ranges
(IORRs) are restricted as follows:
* The boundary on which a variable range is aligned must be equal to the
range size. For example, a memory range of 16 Mbytes must be aligned on a
16-Mbyte boundary (i.e., naturally aligned).
* The range size must be a power of 2 (2^n , 52 > n > 11), with a minimum
allowable size of 4 Kbytes. For example, 4 Mbytes and 8 Mbytes are
allowable memory range sizes, but 6 Mbytes is not allowable.
Print out errors if these conditions are violated. I didn't assert since
`set_var_mtrr` can be used in boot block before the serial console is
enabled.
BUG=b:147042464
TEST=Boot trembyle and see MTRR errors:
MTRR Error: base 0xcc800000 must be aligned to size 0x1000000
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I8b8c734c7599bd89cf9f212ed43c2dd5b2c8ba7b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40762
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Let's gather some documentation ideas for the season of docs. I reused
the project ideas style (thanks Patrick). Feel free to add yourself as a
mentor here. Also if you have more ideas, please add them to the
document.
Change-Id: I72221cbd53b99cdc946109753cf72af9c865a1e5
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40662
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add GPIO_PCH_WP (GPP_C11) to associate GPP_PCH_WP with community
zero.
TEST=Build coreboot, flash, boot to
and log into kernel, execute "wp enable" in console,
execute "crossystem" at kernel prompt and verify that "wpsw_cur"
shows as being "1", Execute "wp disable" in console, execute
"crossystem" at kernel prompt and verify "wpsw_cur" is 0.
Change-Id: Ie4ae1365a7611b8be3e795798c171e3f7ea9e417
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40744
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Harrison Peak (HrP) 9560 module needs a reset pin for BT power sequence.
BUG=b:155248677
TEST=Boot into OS and check BT is functional.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I55ed1b095ba53c414c44088f4a6e7720b970e2f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
An array of 64bit integers is passed to acpi_dp_add_integer_array() but
it is not const so can't take a const array without a compiler error.
The function does not modify the array so it can be made const without
breaking anything and allowing a const array to be passed in the future.
BUG=b:146482091
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: I98ecdaef5ddfa2026390e2812f5ea841ee51f073
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40882
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently if a child table is created and added to a property list
without adding any properties to that child it will generate an
empty package. For example:
struct acpi_dp *dsd = acpi_dp_new_table("_DSD");
struct acpi_dp *prop = acpi_dp_new_table("PROP");
acpi_dp_add_child(dsd, "dsd-prop", prop);
acpi_dp_write(dsd);
Results in an empty PROP package:
Name (_DSD, Package (2)
{
ToUUID("dbb8e3e6-5886-4ba6-8795-1319f52a966b")
Package (1) {
Package (2) {
"dsd-prop",
"PROP"
}
}
}
Name (PROP, Package (0)
{
}
Empty packages don't seem to be explicitly forbidden, but they don't
serve a purpose with device properties. Instead, if packages without
any properties or children are skipped then this empty package is not
written and the added child property can refer to another property that
is already defined.
This allows creating property references to existing tables, which can
save duplication and namespace collision issues with nested properties.
BUG=b:146482091
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: I9fee2ceb8a4496b90c7210533eee8c2b186cdfff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
BUG=b:152019429
BRANCH=None
TEST=1. provision dram_part_num field of CBI
2. modify mainboard - dedede to report DRAM part number from CBI
3. check DRAM part number is correct in SMBIOS for memory device
Change-Id: I509d06a81bd005c5afe6e74a2da2ca408dee7b29
Signed-off-by: Marco Chen <marcochen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Separate specific setting to variant from baseboard.
baseboard/romstage.c in current release is only utilized by
careena, we could remove it from the rest of variant build.
BUG=b:154357210,b:154848243
BRANCH=master
TEST=emerge-grunt coreboot
Change-Id: I658526e44aadc47bdc5538f506a1bfe2e5f20f63
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Fix FSP CAR on platforms that have ROM_SIZE of 32MiB.
CodeRegionSize must be smaller than or equal to 16MiB
to not overlap with LAPIC or the CAR area at 0xfef00000.
Tested on Intel CFL, the new code allows to boot using FSP-T.
Change-Id: I4dfee230c3cc883fad0cb92977c8f5570e1a927c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
LTE module is lost after idle overnight, with this workaround,
host will not initiate U3 wakeup at the same time with device,
which will avoid the race condition.
Disable XHCI LFPS power management.
If the option is set in the devicetree, the bits[7:4] in
XHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated
from default 9 to 0.
BUG=b:146768983
BRANCH=octopus
TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash
the image to the device. Run following command to check if
bits[7:4] is set 0:
>iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"
Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: Ib8e5ae79e097debf0c75ead232ddbb2baced2a2a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Running commit aee0baf069 on
Facebook fbg1701 results in an error:
VB2:vb2_rsa_verify_digest() ERROR - vboot2 work buffer too small!
ERROR: HASH table verification failed!
The actual vboot structures require more space.
Workbuffer size needs to be increased.
We didn't determine the commit causing the issue because this change
fixes the issue.
BUG=N/A
TEST=Build and boot Facebook fbg1701
Change-Id: I5caebc643eb493f4285c2f2fc164ff3a5d35e24e
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Add unit test for src/device/i2c.c module.
This patch is also used as an example for incorporating Cmocka mocking
feature (-wrap linker flag).
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: I2eeb565aacc724ae3b9f5c76ef4b98ef695416d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Show a basic example of how unit testing can be applied for the coreboot
project. Add a test harness for lib/string.c module.
TEST=Install cmocka via appropriate command:
sudo apt-get install -y libcmocka-dev
sudo emerge dev-util/cmocka
yum install libcmocka-devel
* Build and run unit tests via `make unit-tests`
* Check the output to see that tests passed.
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: Ibf5554d1e99a393721a66bdd35af0122c2e412c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Add a subsystem which will be used for writing, building and running
unit tests for different coreboot's modules. This work is built using
Cmocka unit testing framework. Description of what unit testing means
(for the author) and how unit testing framework evaluation was performed
may be found in Documentation/technotes/2020-03-unit-testing-coreboot.md
Makefiles structure is very similar to this used for building coreboot
images. Every directory has its own Makefile.inc were tests' names,
sources, subdirs and multiple other test-related attributes are defined
in form of variables.
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: I9b0220b84b9a6e448476ca3eb3ccccc5fb829ad1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39894
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Unlike prior AMD devices, picasso cannot rely on the cache-as-RAM
setup code to properly enable MTRRs. Add that capability to the
bootblock_c_entry() function. In addition, enable an MTRR to cache
(WP) the flash boot device and another for WB of the non-XIP bootblock
running in DRAM.
BUG=b:147042464
TEST=Boot trembyle to payload and make sure bootblock isn't abnormally
slow.
Change-Id: I5615ff60ca196e622a939b46276a4a0940076ebe
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38691
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Marshall Dawson