As acpi_write_hpet() uses CONFIG_HPET_ADDRESS in the HPET table we
need to use CONFIG_HPET_ADDRESS when assigning it to the device.
Change-Id: I656f917658f1c1717bb3653fa048a6d36fca2454
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/10925
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Some FSF addresses found their way back into our tree.
Change-Id: I34b465fc78734d818eca1d6962a1e62bf9d6e7f3
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/11145
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
1. Add functions to support fan control.
2. When IMC firmware is added, the current firmwares' layout
cause build error. There is not enough space to add some firmwares,
so HUDSON_PSP_OFFSET is added to fix this problem.
Change-Id: Ie470a88cb9da256d9f72ea56bf268c15df195784
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Reviewed-on: http://review.coreboot.org/10720
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Fix typo. Use the correct math helper int-lt.
Change-Id: Ia5e722020c75595dfcfb853ea8238fb8391f9a04
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/10980
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The new attributes increase the header size, breaking this assumption.
Change-Id: Ib23862f27650b39133deafb74a24327b098b6e86
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10942
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I08f7251f8fc42b9028b1fdb830546f9922ef43aa
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: YongGon Kim <ilios86@gmail.com>
Reviewed-on: http://review.coreboot.org/10914
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
For hex and int type kconfig symbols, IS_ENABLED() doesn't work. Instead
check to make sure they're defined and not zero. In some cases, zero
might be a valid value, but it didn't look like zero was valid in these
cases.
Change-Id: Ib51fb31b3babffbf25ed3ae4ed11a2dc9a4be709
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10886
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Platforms selecting the HUDSON_DISABLE_IMC symbol were showing the
warning:
warning: (BOARD_SPECIFIC_OPTIONS && BOARD_SPECIFIC_OPTIONS &&
CPU_AMD_AGESA_BINARY_PI) selects HUDSON_DISABLE_IMC which has unmet
direct dependencies (SOUTHBRIDGE_AMD_PI_AVALON ||
SOUTHBRIDGE_AMD_PI_BOLTON || SOUTHBRIDGE_AMD_PI_KERN)
By moving the definition of the symbol outside of the if block
and removing the default n, we can get rid of the warning without
changing the value for any platform.
Change-Id: I5c1bdfbcf3c5c44ee05b8c5e679f6854d784d8dc
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10680
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Display a warning if CONFIG_HUDSON_FWM_POSITION is not inside CBFS.
This can be extended to other Kconfig values for CBFS.
Change-Id: I2423f7b361dda8aac5dab409fa7b656de486f635
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10683
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This patch calculates the address where the chipset firmware descriptor
should be located and compares it against the actual value from Kconfig.
If the two don't match, it puts up a warning.
This could probably replace the config variable completely, but I wanted
to see how other people felt before doing that. I seem to recall that
the value used to be calculated, so I figure that there must be a reason
it's done this way at this point.
If we do want to keep the Kconfig setting, this patch could also be
modified to just verify that the HUDSON_FWM_POSITION is inside the ROM
space.
Change-Id: I94addf463e2c694a94eef218ec855103a3bb5da5
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10682
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Besides the first five DWORDs, the offsets 0x40 & 0x41
are used to save SPI settings. They should only be 0xFF
for being written.
Other parts in ROMSIG are also changed to 0xFF for potential
requirement.
Change-Id: I61ea8295d5ee8ffbbd0cfcf9e4bece770d70e1f2
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/10651
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
AMD Kern uses PspSecureOs_prod_CZ.csbin rather than PspSecureOs_prod_CZ.sbin.
PspSecureOs_prod_CZ.csbin is the firmware in CarrizoPI v1.0.0.7.
Change-Id: Idf54ee808dd6965aec9b979be00b7f890a88b06d
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Reviewed-on: http://review.coreboot.org/10639
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Kern is the southbridge of AMD Merlin Falcon(Carrizo).
This add support of HD audio, lpc, sata and usb for Kern.
Change-Id: Ie47e38bc1099cdb72002619cb1da269f3739678b
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Reviewed-on: http://review.coreboot.org/10418
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
sata.asl and superio.asl are empty files. Remove them.
Change-Id: Icd3e990aa713281e46dcbd8e0847166c77656b1c
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Reviewed-on: http://review.coreboot.org/10505
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Resync together, backporting a fix for the initialization of
8254 and 8259, as in commit 8d9a1bd5. Also fix a typo and
reduce out useless whitespace differences.
Change-Id: I9a9b1fb9083c5417a8d061f90a89074f2a601ddf
Signed-off-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Reported-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/10453
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Used command line to remove empty lines at end of file:
find . -type f -exec sed -i -e :a -e '/^\n*$/{$d;N;};/\n$/ba' {} \;
Change-Id: I816ac9666b6dbb7c7e47843672f0d5cc499766a3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: http://review.coreboot.org/10446
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
`device_t device` is missing as argument. Every device_op function
should have a `device_t device` argument.
Change-Id: I7fca8c3fa15c1be672e50e4422d7ac8e4aaa1e36
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: http://review.coreboot.org/9598
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The input/output value max is no longer used for tracking the
bus enumeration sequence, everything is handled in the context
of devicetree bus objects.
Change-Id: I545088bd8eaf205b1436d8c52d3bc7faf4cfb0f9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8541
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Use of scan_static_bus() and tree traversals is somewhat convoluted.
Start cleaning this up by assigning each path type with separate
static scan_bus() function.
For ME, SMBus and LPC paths a bus cannot expose bridges, as those would
add to the number of encountered PCI buses.
Change-Id: I8bb11450516faad4fa33b8f69bce5b9978ec75e5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8534
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
All boards now use per-device ACPI. This patch finishes migration
by removing transitional kludges.
Change-Id: Ie4577f89bf3bb17b310b7b0a84b2c54e404b1606
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7372
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
As per discussion with lawyers[tm], it's not a good idea to
shorten the license header too much - not for legal reasons
but because there are tools that look for them, and giving
them a standard pattern simplifies things.
However, we got confirmation that we don't have to update
every file ever added to coreboot whenever the FSF gets a
new lease, but can drop the address instead.
util/kconfig is excluded because that's imported code that
we may want to synchronize every now and then.
$ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} +
$ find * -type f
-a \! -name \*.patch \
-a \! -name \*_shipped \
-a \! -name LICENSE_GPL \
-a \! -name LGPL.txt \
-a \! -name COPYING \
-a \! -name DISCLAIMER \
-exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} +
Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9233
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
There's now room for other repositories under 3rdparty.
Change-Id: I51b02d8bf46b5b9f3f8a59341090346dca7fa355
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10109
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
To move 3rdparty to 3rdparty/blobs (ie. below itself
from git's broken perspective), we need to work around
it - since some git implementations don't like the direct
approach.
Change-Id: I1fc84bbb37e7c8c91ab14703d609a739b5ca073c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10108
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This change switches all southbridge vendors and southbridges
to be autoincluded by Makefile.inc, rather than having to be
mentioned explicitly in southbridge/Makefile.inc or in
southbridge/<vendor>/Makefile.inc.
In order to be able to drop southbridge/amd/Makefile.inc, some
scattered source files had to be moved to a southbridge/amd/common
directory, in accordance to what we are doing on other architectures
already.
This means, vendor and southbridge directories are now "drop
in", e.g. be placed in the coreboot directory hierarchy
without having to modify any higher level coreboot files.
The long term plan is to enable out of tree components to be
built with a given coreboot version (given that the API did not
change).
Change-Id: I79bd644a0a3c4e8320c80f8cc7a7f8ffd65d32f2
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/9796
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
In agesa code for hudson southbridge LPC_DEV is not defined,
but used. Define LPC_DEV as done in southbridge/amd/cimx/sb800.
This fixes it.
Change-Id: Ie7db791e9eb607008e70e446fc6fd28114742750
Signed-off-by: Sergej Ivanov <getinaks@gmail.com>
Reviewed-on: http://review.coreboot.org/9292
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
With kconfig understanding wildcards, we don't need
Kconfig files that just include other Kconfig files
anymore.
Change-Id: I7584e675f78fcb4ff1fdb0731e340533c5bc040d
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/9298
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Restructure get_option() calls to avoid unnecessary return value checks
by pre-assigning defaults to the options being retrieved.
Change-Id: I9159afe149a8eeed0785d1efd6eee8420b88b8f4
Signed-off-by: Varad Gautam <varadgautam@gmail.com>
Reviewed-on: http://review.coreboot.org/8631
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
This moves the initialization of the 8254 and 8259 out
of the (unmerged) lamar mainboard romstage.c file and into
the southbridge code as it is done in the other AMD
southbridges.
Change-Id: I73b375754ee4a9bf15981f2cd31056d7e04db23e
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/9182
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
And this path is already included properly elsewhere.
Change-Id: I9fc6887fc047a9df1c4cb6fa4f841abb16f6d548
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9174
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Our target is to get rid of backup_top_of_ram() and get_top_of_ram()
entirely so only declare these with LATE_CBMEM_INIT=y.
Change-Id: I54f549fe774996f4d803f9ec527e0fac46f6576f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8749
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
The AMD RS780 early initialization code originally used the
CF8/CFC I/O method for PCI configuration space access. After
the default configuration access method was changed to MMIO
(http://review.coreboot.org/#q,aad07472), booting would hang
at "PCI: pci_scan_bus for bus 01". Fix the problem by changing
function rs780_nb_gfx_dev_table() so that it no longer borrows
the BAR3 address needed for PCIe MMIO config usage.
Change-Id: I8816b94c848e1b50f8c880e5867a96ca2a33a8a7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8394
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
The GCC 4.9.2 update showed that the boot_state_init_entry
structures were being padded and assumed to be aligned in to an
increased size. The bootstate scheduler for static entries,
boot_state_schedule_static_entries(), was then calculating the
wrong values within the array. To fix this just use a pointer to
the boot_state_init_entry structure that needs to be scheduled.
In addition to the previous issue noted above, the .bs_init
section was sitting in the read only portion of the image while
the fields within it need to be writable. Also, the
boot_state_schedule_static_entries() was using symbol comparison
to terminate a loop which in C can lead the compiler to always
evaluate the loop at least once since the language spec indicates
no 2 symbols can be the same value.
Change-Id: I6dc5331c2979d508dde3cd5c3332903d40d8048b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8699
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The decode of UART addresses down to the LPC bus needs
to occur early to allow romstage console messages to
be seen. This enables the decode of most of the I/O
ports typically seen in a system.
Change-Id: I6636946af4ad5320a5a46c2920b4f06345b5f806
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8661
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
During the development of commit bde6d30 (x86: Change MMIO addr
in readN(addr)/writeN(addr, val) to pointer), there were several iterations
and patterns tried. An intermediate pattern was the use of u32 pointers,
and division by sizeof(u32). Some of these did not get properly
changed to pointer types of length 1, causing a regression in
the Intel Ibex Peak SATA driver, fixed in commit 9b5f137
(Intel ibexpeak: Fix SATA configuration).
Other regressions of this pattern are fixed here. I audited all changes
to u32 types, and the other ones are safe.
Change-Id: I9e73ac8f4329df8bf0cdd1a14759f0280f974052
Signed-off-by: Kevin Paul Herbert <kph@meraki.net>
Reviewed-on: http://review.coreboot.org/8530
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Some GPIO pins are shared with PCI bridge 0:14.4.
As our PCI subsystem currently does not configure PCI bridges that are
marked disabled, but remain visible in the hardware, simply setting 0:14.4
disabled in the devicetree does not work here yet.
Change-Id: Ib9652e12a888e1d797d879d97737ba4101b7029a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8495
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Tested-by: build bot (Jenkins)
The existing code generated invalid ACPI processor objects
if the core number was greater than 9. The first invalid
object instance was autocorrected by Linux, but subsequent
instances conflicted with each other, leading to a failure
to boot if more than 10 CPU cores were installed.
The modified code will function with up to 99 cores.
Change-Id: I62dc0eb61ae2e2b7f7dcf30e9c7de09cd901a81c
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8422
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
On x86, change the type of the address parameter in
read8()/read16/read32()/write8()/write16()/write32() to be a
pointer, instead of unsigned long.
Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330
Signed-off-by: Kevin Paul Herbert <kph@meraki.net>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7784
Tested-by: build bot (Jenkins)
PCIe root ports on devices 0:15.0 to 0:15.3 should at first all
appear visible in hardware. The real configuration will be done by
vendorcode once we call sb_Before_Pci_Init().
Change-Id: I01a46c630aa6d55a94af45da6b78c97df7553e4f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8387
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This has nothing to do with SATA controller. We only need to
fill the table with defaults before we parse devicetree for
changes to device configuration.
Change-Id: Ic4b28b5992ec9bfdf252f61b1c86b0162243cc95
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8386
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
A set of pins can be configured for GPIO or (parallel) PCI bridge use.
When requested configuration is 0:14.4 enabled, register programming
must be done before attempting to enumerate devices behind the bridge.
When requested configuration is 0:14.4 disabled, we must not even
temporarily enable pins for PCI use to avoid spurious GPIO state changes.
As our PCI subsystem currently does not configure visible PCI bridges
that are marked disabled, we cannot mark 0:14.4 disabled just yet but
need to handle pcengines/apu1 as a special case.
Drop related dead code.
Change-Id: I8644ebae43b33121ef2a7ed30f745299716ce0df
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8329
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
These sb800_enable() messages without newline mess up the log.
Change-Id: I1689b68702e08e2a287083835f310f52f495c451
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8384
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This combines the Avalon and Bolton tables of text descriptions
of the IRQ assignments. It also corrects the text string for
the SD controller on Bolton.
Test: This was verified on amd/lamar.
Change-Id: Ibc74641eb4e1f7581f26d260ba3d33201bcbf5e7
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8374
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
This copies what was done in southbridge/amd/agesa in:
commit 56f46d8 agesa/family15tn: Switch to per-device ACPI
TEST: amd/lamar.
Change-Id: Id8890ccd4a1ea783ad4740333ae6b061b6bbd7fc
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8288
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This adds the PCI and interrupt related definitions
for the bolton specific features.
Change-Id: Ia6530c57ec5a4a5c4525bfbae0eb5db04c0bef9e
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8286
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
To maintain consistancy with southbridge/amd/agesa/hudson rename
pi/avalon to pi/hudson in advance of adding support for the
base hudson southbridge.
Change-Id: Icff8c4c06aae2d40cbd9e90903754735ac3510c3
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8251
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
These were probably accidentally missed when the move
from southbridge/amd/agesa/hudson to amd/pi/avalon occured.
Change-Id: I4cf6e2f8b25899d6d342452cb1b15e694dae35c8
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8248
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Because we had no stack on romcc boards, we had a separate, not as
powerful clone of printk: print_*. Back in the day, like more than
half a decade ago, we migrated a lot of boards to printk, but we never
cleaned up the existing code to be consistent. instead, we worked around
the problem with a very messy console.h (nowadays the mess is hidden in
romstage_console.c and early_print.h)
This patch cleans up the southbridge code to use printk() on all non-ROMCC
boards.
Change-Id: I312406257e66bbdc3940e206b5256460559a2c98
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/8110
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Somewhere along the line, the sb_cfg parameter name was changed to
config, but this wasn't carried into the documentation or the function
prototypes everywhere.
Change-Id: Iccb0829c2f50370dddb70af915a6759316c4727a
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/8098
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
These comments are left over and are not relevent in the coreboot
code, but created a new section titled "Release Content" in the
doxygen documentation produced by the coreboot code. In an effort
to clean up the output, I'm removing these doxygen comments.
Change-Id: I4d7be3313a2ab6c140b4f3afe70dffc4abba7bca
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/8069
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This patch has a rather twisted history. It was originally split off
from a chromium patch, which moved ALTCENTURY to Kconfig. However,
since we have no user without ALTCENTURY, we've agreed that the best
way to proceed is to eliminate the non-ALTCENTURY case entirely.
The old commit message and identifiers are kept below for reference:
The availability of "ALTCENTURY" is now set through a kconfig
variable so it can be available to the RTC driver without having to have a
specialized interface.
BUG=None
TEST=Built and booted on Link with the event log code modified to use the RTC
interface. Verified that the event times were accurate.
BRANCH=nyan
Original-Change-Id: Ifa807898e583254e57167fd44932ea86627a02ee
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/197795
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
This is the second half the following patch.
(cherry picked from commit 9e0fd75142d29afe34f6c6b9ce0099f478ca5a93)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I8e871f31c3d4be7676abf9454ca90808d1ddca03
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7987
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
These are not wrappers for AGESA as they do not enter vendorcode at all.
We expect most of the added fixme.c file to be written without use of AMDLIB.h
and parts relocated as northbridge enable_resources().
Change-Id: Iba6d59e2a7672349208e9a65fcd2cb1094ab7d50
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7815
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
The new AMD PSP and SMU BLOBs currently have fixed sizes in the
southbridge Makefile. Future PSP and SMU updates may require more
space and thereby cause the make to fail with cryptic error messages.
Change the makefile to compute CBFS locations and the corresponding
PSP pointer table entry values based on the actual file sizes.
Additionally, the FWM directory has expanded to 4096 bytes. The
Avalon makefile is modified to zero-pad the FWM directory using
the "dd" system command.
There is dead code in the makefile to allow hardware validated boot
ROMs, but the option is hard-coded to be disabled. Remove the HVB
dead code.
Change-Id: I4705cede8ed001a71bb4f49598444255c9609d52
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/7726
Reviewed-by: Marshall Dawson <marshall.dawson@se-eng.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Along with the spelling fixes, it was requested that I correct this
comment. Updating "LocateImage() take minutes" to
"LocateImage() takes minutes" everywhere that comment occurs.
Change-Id: I28cd47476cb42ba3e404e064695a7fd97d581834
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7848
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Trivial fixes, but the editor highlights them, and it's easy to go
through a bunch of files while I'm otherwise idle.
Change-Id: I5a5af71ea49152accd92dc331a19e57f3717e4ff
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7841
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Trivial fixes, but the editor highlights them, and it's easy to go
through a bunch of files while I'm otherwise idle.
Change-Id: I5d2d4ba098d2a95f7643f000f4b48b3349a8e6cf
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7839
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Trivial fixes, but the editor highlights them, and it's easy to go
through a bunch of files while I'm otherwise idle.
Change-Id: Ice5d8ce9408356c866a9a2ee5a03f704f55ddc2a
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7842
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Trivial fixes, but the editor highlights them, and it's easy to go
through a bunch of files while I'm otherwise idle.
Change-Id: I31333742d9c90cf6d7ae3d2f324880ed53807d7f
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7840
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
There is no Cache As Ram for these boards, let's get rid of them.
Change-Id: Ib41f8cd64fc9a440838aea86076d6514aacb301c
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/7117
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
It appears the decimal value was used instead of the hexadecimal value.
Apply commit 59919ad1 (southbridge/amd/agesa/hudson: Correct incorrect
#define) to AMD Avalon, whose `pci_devs.h` was copied from AMD Hudson.
The incorrect define was introduced in commit 2093c4f7 (AMD/agesa: Add
functions for AMD PCI IRQ routing).
Change-Id: I7ccc060e8fa032080375259c3b11d39e2deb8e9e
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/7800
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
It appears the decimal value was used instead of the hex value.
Change-Id: I04acde9e5b2a9e08ed01b0564c3d561b0385a392
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/7799
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
They were only used internal to the SPI drivers and, according to the comment
next to their prototypes, were for when the SPI controller doesn't control the
chip select line directly and needs some help.
BUG=None
TEST=Built for link, falco, and rambi. Built and booted on peach_pit and nyan.
BRANCH=None
Original-Change-Id: If4622819a4437490797d305786e2436e2e70c42b
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/192048
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 1e2deecd9d8c6fd690c54f24e902cc7d2bab0521)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ida08cbc2be5ad09b929ca16e483c36c49ac12627
Reviewed-on: http://review.coreboot.org/7708
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Correct mask to select bits 4-6 inclusively as per comment and use
bitwise operations while working with bits. Be sure to write back out
the data on the retrain.
See:
commit cab9efb2 southbridge/amd/rsXY0/cmn.c: Fix bitwise logic and mask in loop
Change-Id: I95d1799514157b7849f3e473837aaf2fd9bd59b9
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7692
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
Don't build in non-essential blobs by default. However, if the user
selected to use the blobs repository, then default to including the
blobs.
Change-Id: Ie90f00d7c18d725f24fe1503fadaf098d3cefa4a
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7638
Tested-by: build bot (Jenkins)
GPP config from devicetree.cb is not implemented for fam15tn/fam16kb.
Also only for asus/f2a85-m the configuration value matched the actual
programming.
Change-Id: Ic7a9aa1360f4ba35d202f3f7dd1fc3c20a52dde0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7600
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Change-Id: I2adb5a8fe2cede988cc6fdef5ff81da86d267175
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7624
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Avalon support now lives under pi/avalon so we can restore Hudson
to the state before it was added there.
Change-Id: Id96973f3458fae162232c160e602595b58c43027
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7389
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
To backport features introduced with recent Chromebooks and/or Intel
boards in general, heavy work on the AMD AGESA platform infrastructure
is required. With the AGESA PI available in binary form only, community
members have little means to verify, debug and develop for the said
platforms.
Thus it makes sense to fork the existing agesawrapper interfaces, to give
AMD PI platforms a clean and independent sandbox. New directory layout
reflects the separation already taken place under 3rdparty/ and vendorcode/.
Change-Id: Ia730f0e45e7c1bdfc0c91e95eb6729a77773e2b9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7388
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Tested-by: build bot (Jenkins)
To backport features introduced with recent Chromebooks and/or Intel
boards in general, heavy work on the AMD AGESA platform infrastructure
is required. With the AGESA PI available in binary form only, community
members have little means to verify, debug and develop for the said
platforms.
Thus it makes sense to fork the existing agesawrapper interfaces, to give
AMD PI platforms a clean and independent sandbox. New directory layout
reflects the separation already taken place under 3rdparty/ and vendorcode/.
Change-Id: Ib60861266f8a70666617dde811663f2d5891a9e0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7149
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Tested-by: build bot (Jenkins)
There are too many differences, and calculating relatively
large integer using floats might not be the brightest idea
anyway.
Also avoid relying on ls(1) output format to determine file sizes.
Change-Id: I5f96c036737b74e20f525c3dc9edc011ad403662
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7447
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
