Commit Graph

20639 Commits

Author SHA1 Message Date
Martin Roth 1a693958eb payloads/external/iPXE: Update stable version
Update from commit 2afd66eb - Fri Jul 29, 2016
([pixbuf] Enable PNG format by default)

To commit fd6d1f46 -  Fri Mar 31, 2017
([thunderx] Use ThunderxConfigProtocol to obtain board configuration)

This moves the stable iPXE commit forward 144 commits.

Change-Id: Ia0c97f863be39632c9206ca95b3857047fc37e26
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/19221
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-04-14 16:27:42 +02:00
Arthur Heymans 2f6b52e3a0 nb/intel/i945: Fix PEG port on 945gc
Vendor BIOS leaves UPMC1 untouched (on 945gc the default is 0x0203).

Not running PCIEx16 init which is valid for 945gm seems to fix all
issues and instabilities related to the PEG port.

According to lspci the link width is at the desired x16.
It is unknown if devices requesting a lower width work automatically
or need more configuration.

What happens is that IGD gets disabled by the disable function in
gma.c when an external GPU is found unless
CONFIG_ONBOARD_VGA_IS_PRIMARY is set.

Setting IGD as secondary makes Linux (4.10) hang, so this behavior is
a requirement for now.

TESTED on P5GC-MX with a discrete GPU and both
CONFIG_ONBOARD_VGA_IS_PRIMARY set and unset.

Change-Id: I6da8aa7714073f4b34df5ae3c1eb4c19e27ddc97
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18549
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-04-14 13:26:01 +02:00
Duncan Laurie f13e250152 mainboard/google/eve: Remove ACPI ALS device
Remove the ACPI ALS device from the EC configuration because this system
has an ALS that is presented through the new EC sensor interface rather
than the legacy ACPI interface.

BUG=b:37179776
BRANCH=none
TEST=Boot an Eve device and ensure that 'acpi-als' device is not present
in /sys/bus/iio/devices.

Change-Id: Ie18b8a661e4d16464784ca8a227586036e7631de
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/19265
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-14 04:21:52 +02:00
Duncan Laurie e49b866c7c mainboard/google/eve: Set UART0 to skip initialization in FSP
Set UART0 to "PchSerialIoSkipInit" so the pins for this device are not
set back to native mode by FSP when configured as GPIO input by coreboot.

Now that FSP is not touching the pins I also removed the workaround to
reconfigure the pins after FSP.

BUG=b:35647877
BRANCH=none
TEST=Verify that GPP_C8-GPP_C11 are configured as GPIO input once the OS
is booted and they are not set back to native function by FSP.

Change-Id: Ifec4fa3e66ceeb660bad00c66bc7bd44bb457a01
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/19264
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-04-14 04:21:37 +02:00
Duncan Laurie 30783d84cf mainboard/google/eve: Enable internal pull-down on USB_C{0,1}_DP_HPD
These lines act as inputs to both EC and AP and when the corresponding
TCPC mux is in low power mode the line is floating.  Add an internal
pull-down to each GPIO to prevent it from floating in this state.

BUG=b:35775012
BRANCH=none
TEST=Verify that the kernel does not see a device present on DP when
the TCPC mux is in low power mode.

Change-Id: Ie229f84871e9994467c0ab660cc7e271a51d9cbb
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/19263
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-04-14 04:20:09 +02:00
Furquan Shaikh a0729d9a56 soc/intel/apollolake: Change IOSF_BASE_ADDRESS to PCR_BASE_ADDRESS
With recent change to use common block PCR (ccd8700c),
IOSF_BASE_ADDRESS was renamed to PCR_BASE_ADDRESS. However, SD card
change (99ce8a9b) was not rebased on top of it, so IOSF_BASE_ADDRESS
slipped into the tree. Fix this by replacing all occurrences of
IOSF_BASE_ADDRESS by PCR_BASE_ADDRESS.

Change-Id: I40eb07be306035c940fc960896e0807d6c73bafa
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19277
Tested-by: build bot (Jenkins)
Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-13 22:16:21 +02:00
Nicola Corna 5ad939679f mainboard/sapphire/pureplatinumh61: Enable EuP and PME
With EuP and PME enabled the USB power turns off during S5.

Change-Id: I8b9fd7bb308f544401f90f8aa5ffaec61251b2b3
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/19073
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2017-04-13 21:38:16 +02:00
Venkateswarlu Vinjamuri 415949ac50 mainboard/google/reef: Configure sdcard card detect (CD) pin GPIO_177
This configures GPIO_177 as native function.

This enables OS to boot from sdcard.

BUG=b:35648535
TEST=Check OS boot from sdcard.

Change-Id: I73901d4a1b39752cbc452f3286d494587dac95d4
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/18948
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
2017-04-13 19:51:32 +02:00
Venkateswarlu Vinjamuri 99ce8a9bba soc/intel/apollolake: Set sdcard card detect (CD) host ownership
Currently sdcard CD host ownership is always owned by the GPIO driver.
Due to this sdcard detection fails during initial boot process and OS
fails to boot from sdcard.

This implements change in host ownership from acpi to GPIO driver when
kernel starts booting.

BUG=b:35648535
TEST=Check OS boot from sdcard.

Change-Id: I042a8762dc1f9cb73e6a24c1e7169c9746b2ee14
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/18947
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
2017-04-13 19:50:34 +02:00
Wisley Chen 9c30d06bfc mainboard/google/snappy: Increase weida touchscreen reset delay
Weida touchscreen controller needs 130 ms delay after reset

BUG=b:35586513
BRANCH=reef
TEST=Verified that touchscreen works on power-on and suspend/resume
on snappy.

Change-Id: I8418e742a69a2d6395baa2799a4da42a9bb5b312
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/19245
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-13 17:28:10 +02:00
Duncan Laurie 73ff0fbd2e google/eve: Disable Deep S3 in AC mode
In order to support a standard "docked" config disable Deep S3 when
connected to AC power.  This allows USB devices to wake the device
from suspend if it is externally powered, but still retains the
lower power state when running on battery.

BUG=b:36723679
BRANCH=none
TEST=manual testing on Eve for USB wake behavior:
1) when suspended on battery USB keyboard does not wake
2) when suspended while connected to AC a USB keyboard does wake
3) if suspended with AC, and then AC is removed, system does not
wake with USB keyboard
4) if suspended without AC, and then AC is added, system does not
wake with USB keyboard (it cannot get enabled without waking and
re-suspending)

Change-Id: I670e39d42cdb5b80612206da899be82ef3b2cbf2
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/19240
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-13 09:11:29 +02:00
Duncan Laurie 654c8de9f1 google/eve: Enable WiFi SAR feature
Enable the Intel WiFi SAR feature for Eve, which will be used to
provide wifi power tables based on values read from VPD.

This is enabled based on CONFIG_CHROMEOS because it relies on the
presence of VPD code from vendorcode/google/chromeos.

BUG=b:36727652
BRANCH=none
TEST=test on Eve by setting "wifi_sar" in VPD and ensuring that
the ACPI WIFI device gets the expected "WRDS" and "EWRD" tables
with the values that were set in VPD.

Change-Id: I11c129baca891221177575108ac09ba1707b516e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/19241
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-13 09:09:45 +02:00
Duncan Laurie 1fe32d6bb2 soc/intel/skylake: Split AC/DC settings for Deep Sx config
Currently when enabling Deep S3 or Deep S5 it unconditionally gets enabled
in both DC and AC states.  However since using Deep S3 disables some
expected features like wake-on-USB it is not always desired to enable the
same state in both modes.

To address this split the setting and add a separate config for Deep Sx in
AC and DC states.

All motherboards that set this config were updated, but there is no actual
change in behavior in this commit.

BUG=b:36723679
BRANCH=none
TEST=This commit has no runtime visible changes, I verified on Eve that the
Deep SX config registers are unchanged, and it compiles for all affected boards.

Change-Id: I590f145847785b5a7687f235304e988888fcea8a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/19239
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-13 09:09:16 +02:00
Furquan Shaikh bcbba801b8 mainboard/google/poppy: Enable internal pull-down on USB_C{0,1}_DP_HPD
These lines act as inputs to both EC and AP. Thus, add internal
pull-downs to prevent them from floating.

BUG=b:35648530

Change-Id: I42326c810775d5449e99e52e81870970247ce335
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19243
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-13 05:05:05 +02:00
Furquan Shaikh 82010835bf mainboard/google/poppy: Add support for cr50 SPI TPM
Put all configs required for enabling cr50 SPI TPM on poppy under
POPPY_USE_SPI_TPM so that it can be enabled any time for testing SPI
TPM on this board.

Also, add required callback for irq status and devicetree config for
GSPI0.

BUG=b:36873582

Change-Id: I67793093c006c1325fc16f669a96126525f83243
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19238
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-13 05:04:36 +02:00
Furquan Shaikh 260b297a89 drivers/spi/tpm: Clean up SPI TPM driver
1. Move common TIS macros to include/tpm.h.
2. Use common TIS macros while referring to status and access registers.
3. Add a new function claim_locality to properly check for required
access bits and claim locality 0.

BUG=b:36873582

Change-Id: I11bf3e8b6e1f50b7868c9fe4394a858488367287
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19213
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-04-13 05:04:13 +02:00
Aamir Bohra bf6dfaefc2 intel/soc/apollolake: Use intel/common/uart driver
Change-Id: I6829eca34d983cfcc86074ef593cd92236b25ac5
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/19204
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-11 17:04:13 +02:00
Aamir Bohra c1f260e49a soc/intel/skylake: Use intel/common/uart driver
Change-Id: Id132df15ae5a6aef75d6434df18fc71d8d28c3ca
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/19003
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-11 17:03:20 +02:00
Aamir Bohra 01d75f4172 soc/intel/common/block: Add Intel common UART code
Create Intel Common UART driver code. This code does
below UART configuration for bootblock phase.

* Program BAR
* Configure reset register
* Configure clock register

Change-Id: I3843fac88cfb7bbb405be50d69f555b274f0d72a
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/18952
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-11 17:01:46 +02:00
Aamir Bohra 138b2a03be soc/intel/apollolake: Use LPSS common library
Use lpss common library to program reset and
clock register for lpss modules

Change-Id: I75f9aebd60290fbf22684f8cc2ce8e8a4a4304b0
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/19154
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-11 17:00:43 +02:00
Aamir Bohra 015c64335d soc/intel/skylake: Use LPSS common library
Use lpss common library to program reset and
clock register for lpss modules.

Change-Id: I198feba7c6f6d033ab77ed25a5bd9ea99411a1e4
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/19153
Tested-by: build bot (Jenkins)
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-11 16:59:30 +02:00
Martin Roth ccfea16cd4 Documentation: Reflow Kconfig.md
The original document was written and committed with no regard to line
lengths.  This makes it easier to write.  Now it needs to be easier to
read, so wrap the lines at 80 characters where possible.

- A couple of headings had to be rewritten to keep them under 80
characters.  This required the addition of a new paragraph that had
the old header.
- Remove URL text that was just duplicating the URL.
- All other text is the same, just wrapped.

Change-Id: I44833c28750714fccb87296868c1ff78ab7f1d07
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/19076
Tested-by: build bot (Jenkins)
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-04-11 16:18:57 +02:00
Arthur Heymans 2a7c519c89 sb/intel/i82801gx: Add i2c_block_read to smbus.h
Using i2c_block_read speeds up reading SPD four to fivefold compared
to sequential byte read.

TESTED on Intel D945GCLF.

Change-Id: I6d768a2ba128329168f26445a4fca6921c0c8642
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18927
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-04-11 11:51:04 +02:00
Shunqian Zheng 4f4410dcbc scarlet/gru: skip display because mipi driver not ready
Scarlet don't have eDP and MIPI driver is not ready, skipping
display for now or else Scarlet would be stuck in
reading eDP HPD because there even not power for it.

TEST=boot to kernel on Scarlet

Change-Id: I02ab4ef21bf77b98414f537aca57b46c11922348
Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Reviewed-on: https://review.coreboot.org/19237
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-04-11 04:22:09 +02:00
Duncan Laurie 08117c412c google/eve: Limit memory SKU 5 to 1600MHz
Due to issues with stability limit the SKU with K4EBE304EB-EGCF
memory to 1600MHz instead of 1866MHz.

BUG=b:37172778
BRANCH=none
TEST=pass stress testing on devices with this memory

Change-Id: I02af7e9c35e2c5b0b85223d58025cbd29841d973
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/19227
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-11 04:04:32 +02:00
Arthur Heymans f170e71630 nb/amdk8/(pre_)f.h: Don't declare global variable in header
This is needed if one wants to use the header more than once.

Change-Id: I375d08465b6c64cd91e7563e3917764507d779ba
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19029
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-04-10 20:53:00 +02:00
Aamir Bohra 237a93c43e soc/intel/common/block: Add LPSS function library
LPSS function library implements common register
programming under lpss.

Change-Id: I881da01be8191270d9505737f68a6d2d8cd8cc69
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/19001
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-10 20:46:17 +02:00
Subrata Banik 8bf69d3078 soc/intel/apollolake: Use RTC common code
This patch uses common RTC library to enable
upper 128 byte bank of RTC RAM.

Change-Id: I55e196f6c5282d7c0a31b3980da8ae71764df611
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/18700
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2017-04-10 20:44:41 +02:00
Subrata Banik e0268d3e1a soc/intel/skylake: Use RTC common code
This patch uses common RTC library to enable
upper 128 byte bank of RTC RAM.

Change-Id: Ibcbaf5061e96a67815116a9f7a03be515997be6d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/18701
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2017-04-10 20:40:01 +02:00
Barnali Sarkar 8e84723e02 soc/intel/common/block: Add Intel common RTC code support
Create Intel Common RTC code. This code currently only
contains the code for configuring RTC required in Bootblock phase
which has the following programming -
* Enable upper 128 bytes of CMOS.

Change-Id: Id9dfcdbc300c25f43936d1efb5d6f9d81d3c8453
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/18558
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Tested-by: build bot (Jenkins)
2017-04-10 20:07:01 +02:00
Subrata Banik ccd8700cac soc/intel/apollolake: Use common PCR module
This patch use common PCR library to perform CRRd and CRWr operation
using Port Ids, define inside soc/pcr_ids.h

Change-Id: Iacbf58dbd55bf3915676d875fcb484362d357a44
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/18673
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-10 20:05:35 +02:00
Subrata Banik e7ceae7950 soc/intel/skylake: Use common PCR module
This patch use common PCR library to perform CRRd and CRWr operation
using Port Ids, define inside soc/pcr_ids.h

Change-Id: Id9336883514298e7f93fbc95aef8228202aa6fb9
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/18674
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-10 20:04:01 +02:00
Subrata Banik d579199f96 soc/intel/common/block: Add Intel common PCR support
IOSF_SB message space is used to access registers mapped
on IOSF-SB. These registers include uncore CRs (configuration
registers) and chipset specific registers. The Private
Configuration Register (PCR) space is accessed on IOSF-SB
using destination ID also known as Port ID.

Access to IOSF-SB by the Host or System Agent is possible
over PSF via the Primary to Sideband Bridge (P2SB). P2SB will
forward properly formatted register access requests as CRRd and
CRWr request via IOSF-SB.

Change-Id: I78526a86b6d10f226570c08050327557e0bb2c78
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/18669
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-10 20:00:35 +02:00
Duncan Laurie 92dde2fdd7 google/eve: Update I2C bus timing
Update the I2C rise/fall timings based on newly measured values
on a new board with updated pull-up resistor values.

Touchscreen: rise time 98ns, fall time 38ms
Touchpad: rise time 111ns, fall time 41ns
TPM: rise time 112ns, fall time 34ns

BUG=b:35583133
BRANCH=none
TEST=Each I2C bus frequency was verified on a scope to be ~400MHz

Change-Id: Ibb3a15fa0cc862f36c1b9c63ac7847221020c4c0
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/19202
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-04-10 10:07:33 +02:00
Furquan Shaikh 5bda642bcb drivers/spi: Get rid of spi_get_config
There is only one user for spi_get_config i.e. SPI ACPI. Also, the
values provided by spi_get_config are constant for now. Thus, get rid
of the spi_get_config call and fill in these constant values in SPI
ACPI code itself. If there is a need in the future to change these,
appropriate device-tree configs can be added.

BUG=b:36873582

Change-Id: Ied38e2670784ee3317bb12e542666c224bd9e819
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19203
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2017-04-09 21:35:53 +02:00
Aaron Durbin bc17cdef0d arch/x86: remove CAR global migration when postcar stage is used
When a platform is using postcar stage it's by definition not
tearing down cache-as-ram from within romstage prior to loading
ramstage. Because of this property there's no need to migrate
CAR_GLOBAL variables to cbmem.

Change-Id: I7c683e1937c3397cbbba15f0f5d4be9e624ac27f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19215
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-04-08 23:22:02 +02:00
Kyösti Mälkki acc599b839 AGESA: Add helpers to track heap relocation
Change-Id: Ib43e59e4d4ee5e48abf7177b36cb06fdae40bde9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18627
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-08 15:19:43 +02:00
Kyösti Mälkki e522258907 AGESA f14: Fix memory clock register decoding
Bottom five LSBs are used to store the running frequency
of memory clock.

Change-Id: I2dfcf1950883836499ea2ca95f9eb72ccdfb979c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19042
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-08 15:19:09 +02:00
Nico Huber e223c3aee9 ec/roda/it8518: Do EC write manually with long timeout
The EC may take very long for the first command on a cold boot (~180ms
witnessed). Since this needs an incredibly long timeout, we do this
single command manually.

Change-Id: I3302622a845ac6651bc7f563370d8f0511836f94
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/18707
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-08 13:17:56 +02:00
Nico Huber 105d8e8b01 ec/acpi: Add function to read EC status register
Change-Id: I7b690d1f23ecf4083952c173be1d3a1246bc1593
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/18706
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-08 13:16:52 +02:00
Nico Huber 0ee130a5a2 libgfxinit: Select CONFIG_VGA when needed
This wasn't caught earlier because many boards select it manually.

Change-Id: I245ef8f44923b5384123bd549570db7c348e03b8
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/18771
Tested-by: build bot (Jenkins)
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-08 13:03:52 +02:00
Nico Huber 989aae9f61 3rdparty/libgfxinit: Update submodule pointer
Some renamings force us to update our code:

  * Scan_Ports() moved into a new package Display_Probing.

  * Ports Digital[123] are called HDMI[123] now (finally!).

  * `Configs_Type` became `Pipe_Configs`, `Config_Index` `Pipe_Index`.

Other noteworthy changes in libgfxinit:

  * libgfxinit now knows about ports that share pins (e.g. HDMI1 and
    DP1) and refuses to enable any of them if both are connected
    (which is physically possible on certain ThinkPad docks).

  * Major refactoring of the high-level GMA code.

Change-Id: I0ac376c6a3da997fa4a23054198819ca664b8bf0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/18770
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-08 13:02:44 +02:00
Balaji Manigandan B fe41ae936a KBL: Update FSP headers - upgrade to FSP 2.0.0
Updating headers corresponding to FSP 2.0.0

Below UPDs are added to FspmUpd.h
* PeciC10Reset
* PeciSxReset
rest of the changes are update to comments

CQ-DEPEND=CL:*340004,CL:*340005,CL:*340006
BUG=None
BRANCH=None
TEST=Build and test on Poppy

Change-Id: Id8ecea6fa5f4e7a72410f8da535ab9c4808b3482
Signed-off-by: Balaji Manigandan B <balaji.manigandan@intel.com>
Reviewed-on: https://review.coreboot.org/19109
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-07 21:59:53 +02:00
Naresh G Solanki fb7937918a soc/intel/skylake: Enable XHCI clock gate control in ACPI
Enable SS link trunk clock gating & D3hot when device enters
D3 state.
Similarly disable SS link trunk clock gating & D3hot when device enters
D0 state

TEST=Build & boot Poppy board. Check working for XHCI wake when DUT
is in S3.

Change-Id: Ida2afa2e5f9404c0c15d7027480a28a003ad9a40
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/18879
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-07 21:44:29 +02:00
Brenton Dong 44ff10eaa6 intel/minnow3: Clean up Kconfig, devicetree and FMAP
This patch cleans up the code by:
o adding necessary default definitions to Kconfig
o removing incorrect definitions from devicetree
o removing irrelevant entries from FMD file

devicetree.cb and minnow3.fmd carried over a lot of code from google/reef
which is not correct for Minnow3 hardware.  Minnow3 is not intended to
boot Chrome OS and does not need Chrome related flash regions. The
erroneous code is removed.

These changes are the same as those done for leafhill in commit:
6a48923 mainboard/intel/leafhill: Clean up

This was tested by building with the new configuration and
booting to UEFI Payload

Change-Id: I620dcbcd622f9326917c74b2a38984d9e49cff2b
Signed-off-by: Brenton Dong <brenton.m.dong@intel.com>
Reviewed-on: https://review.coreboot.org/18963
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-07 21:43:06 +02:00
Martin Roth 9931f66581 mainboard/intel: Fix checkpatch errors in minnowmax
This fixes the following issues, with no functional changes:

ERROR:POINTER_LOCATION: "foo * bar" should be "foo *bar"
ERROR:SPACING: space required after that ',' (ctx:VxV)
WARNING:LONG_LINE_COMMENT: line over 80 characters
WARNING:SPACE_BEFORE_TAB: please, no space before tabs
ERROR:FUNCTION_WITHOUT_ARGS: Bad function definition
ERROR:SPACING: space prohibited before that close parenthesis ')'
WARNING:RETURN_VOID: void function return statements are not generally
useful

2 unfixed issues:
ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in
parentheses

Verified that the binary was the same before and after the changes.

Change-Id: Ie9afb50e268f4140872e39fe8bede231a43d5cc6
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/19078
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: York Yang <york.yang@intel.com>
2017-04-07 21:41:19 +02:00
Patrick Rudolph 46cf5c29b3 nb/intel/i945: Move INTEL_EDID
All boards select INTEL_EDID, move it to nb folder.

Change-Id: I35f075a87f2d841856b208f9440cf41af6a3c8e6
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19086
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-07 21:37:16 +02:00
Paul Kocialkowski 038818f00c libpayload: Add gru config
This adds a gru libpayload config, that should fit all gru-based
devices such as kevin.

As gru-based devices are CrOS devices, select the associated config
to enable CrOS-specific features.

Change-Id: I6e79b763fc497c126612b8786a669a33b57ea29f
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/19137
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-04-07 21:33:19 +02:00
Patrick Rudolph 19c3dad0ad nb/intel/sandybridge/raminit: Fix odt stretch
Move odt stretch into own function.
Apply workaround on SandyBridge C-stepping CPU only.
Apply odt stretch on all other CPU types.
Don't depend on empty DIMM detection, as in case one slot
is empty ref_card_offset is zero.

Change-Id: I4320f14e0522ec997b1f9f3b12ba2c2070ee8e9e
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/17616
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-04-07 20:01:17 +02:00
Patrick Rudolph 77db3e153b nb/intel/sandybridge/raminit: Always run quick_ram_check
quick_ram_check doesn't change contents of memory.
Run it in S3 resume, too.

Change-Id: Icaf3650fadbb3bb87d8c780a9e79737c3cf7eb06
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/17615
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-04-07 19:59:23 +02:00