Commit Graph

30088 Commits

Author SHA1 Message Date
Kyösti Mälkki 9fc12e0d4e arch/x86: Enable POSTCAR_CONSOLE by default
Almost all platforms force it on. Make it enabled by
default but under user control to optionally disable it.

Change-Id: I6b0f19c8bfd6ffed93023d57a1d28ca6acc06835
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-08-11 03:07:36 +00:00
Frans Hendriks 7ca7dbc0f5 vendorcode/eltan/security/lib: Add missing vb2ex_printf()
Build error on missing vb2ex_printf() in bootblock stage
Add the file vboot_logic.c which contains the missing vb2ex_printf().

BUG=N/A
TEST=Boot Linux 4.20 and verify logging on Facebook FBG-1701

Change-Id: I3f649f3faf1e812d592e4981bc75698e2cad1cc8
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
2019-08-11 03:03:33 +00:00
Paul Fagerburg d366f54744 kohaku: add TEMP_SENSOR_3 and TEMP_SENSOR_4 to DPTF
The Kohaku V24 schematic adds two additional temperature sensors
to the EC. Add these to the DPTF tables.

Cq-Depend: chromium:1742914
BRANCH=none
BUG=b:138578073
TEST=Rebuild EC and BIOS, look for new thermal sensors in kernel.
1. Build EC
``cd ~/trunk/src/platform/ec``
``make -j BOARD=kohaku``
2. Program EC
``./util/flash_ec --board=kohaku``
3. Reboot device
4. Rebuild BIOS
``cd ~/trunk/src/third_party/coreboot``
``FEATURES="noclean" FW_NAME=kohaku emerge-hatch chromeos-ec depthcharge
vboot_reference libpayload coreboot-private-files intel-cmlfsp
coreboot-private-files-hatch coreboot chromeos-bootimage``
5. Use flashrom to program the BIOS
6. Reboot device
7. Log into the root console (ctrl-alt-F2 or servo)
8. Example thermal sensor information
``grep . /sys/class/thermal/t*/type``
Look for "TSR0" through "TSR3" in the output.

Change-Id: Ib8f38beae6392855927ce1249c229d7a114c72b2
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34765
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-11 03:01:30 +00:00
Tim Wawrzynczak 0caf834c8f mb/google/hatch: Fix Kohaku pen GPIO configuration
Oops, I missed this in the last CL.
The pin needs to be configured as owned by GPIO, so that the kernel
driver can bind it with an IRQ.

BUG=b:139165490
TEST=Ensure kernel nastygram about inability to claim the IRQ is gone

Change-Id: I26c08d75d8b4e3b834db6e90868239899605fa5b
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-11 03:00:35 +00:00
Jacob Garber 3a323808f6 include, lib: Add <inttypes.h> printf macros
In general, third party code (such as vboot) doesn't know what the
underlying types are for the integers in <stdint.h>, so these macros are
useful for portably printing them. Of these definitions, coreboot so far
has only used PRIu64 (in one place), which isn't needed anymore since we
know what the underlying type of a u64 is.

Change-Id: I9e3a300f9b1c38e4831b030ff8af3fed2fa60f14
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-08-10 08:47:08 +00:00
Frans Hendriks d073a0b983 mb/facebook/fbg1701: Select SOC_INTEL_COMMON_BLOCK_HDA_VERB
HDA is not configured.
Enable SOC_INTEL_COMMON_BLOCK_HDA_VERB to configure the HDA using
cim_verb_data[] table.

BUG=N/A
TEST=Boot Embedded Linux 4.20 on Facebook FBG-1701

Change-Id: I9bb542091ad200833894431f5b840f48dd388173
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34655
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-10 01:41:29 +00:00
Wisley Chen a23ff7c8ed mb/google/octopus: Add G2touch touchscreen support
Add G2touch touchscreen support for Dorp/Vortinija/Vorticon.

BUG=b:139110164
BRANCH=octopus
TEST=emerge-octopus coreboot chromeos-bootimage, and check touchscreen by
evtest.

Change-Id: Ia42757c881ec78b1c676ac984507732717af94a9
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
2019-08-10 01:35:25 +00:00
Jacob Garber 5cf9ccc57d src: Include <stdint.h> instead of <inttypes.h>
The <inttypes.h> header currently does nothing but include the
definitions from <stdint.h>, so let's #include that directly instead.

Change-Id: I9d83ad37d0d7300a093001596ce3f0b3830c5701
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-08-10 01:33:58 +00:00
Yuji Sasaki 6b212d8fcf string: implement strspn, strcspn, atol
Change-Id: Id8fa880357124b620bde8884949bd8ffff7d0762
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-10 01:32:19 +00:00
Marshall Dawson e2c24f783d soc/amd/picasso: Update i2c support
Change the stoneyridge definitions into picasso.  The named 0 and 1
buses are controlled by the PSP and not directly accessible by host
firmware.  I2C4 operates only in slave mode so is not added to to
the bus clear-after-reset sequence.

The I2C controller is fundamentally the same as on Stoney Ridge so
the ability to clear a potentially jammed bus is still required.

Program Picasso's new pad control registers in the MISC AcpiMmio
space according to the recommended settings.

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Ibbc5504ebc36654e28c79fe3ae17cc0d9255118f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-08-09 20:46:41 +00:00
Marshall Dawson 34c30565b0 soc/amd/picasso: Update CPU support
Change the Stoney Ridge ID to Picasso.  Rename family 15h.  Get the
number of cores/threads from CPUID as all D18 registers are new.

Change-Id: I44c45db637897f6caf320032c9f79a3a1ab4d6c9
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34421
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-08-09 20:24:59 +00:00
Marshall Dawson 0bd0806d2f soc/amd/picasso: Reduce 48M out configuration
Picasso has only a single 48M output.  Simplify the setup function.
Note that while the feature is similar to older products, the register
definition and Enable bit has changed.

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Iebaf5219fdcd3145a4faf906f656a7fbdc7e0c36
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33768
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-08-09 20:23:50 +00:00
Marshall Dawson ad1fdac987 soc/amd/picasso: Remove IOAPIC2
Remove the Family 15h device.  It's not in Family 17h documentation
and isn't detectable with HDT.

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Ifa9c06f78f39a3ec3b555d4ecc542172cd44a0b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33990
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-09 20:22:46 +00:00
Marshall Dawson d881367c08 soc/amd/picasso: Update SMI sources
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I42bb0edb6fa2c6fa92829ef5d3623483aa448a5c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33771
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-09 20:21:58 +00:00
Marshall Dawson 40bc485745 soc/amd/picasso: Update machine check support
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Iae48a0c3fb2abf2aa3fb78af8d50431c8533f76f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33769
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-09 20:21:16 +00:00
Marshall Dawson c17cc63e48 src/amd/picasso: Update reset code
Remove the scratch register indicators.  Per AMD, AGESA no longer
uses these.  Use a new IO register to determine whether a warm
reset should occur.

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I0ff7935004b3d1ac5204d3ef575cfa98116a57fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33989
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-09 20:20:31 +00:00
Marshall Dawson 48c5d29cde soc/amd/common: Add new GPIO 8K pull-up definition
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: If24bed8b3f10d945b9988445025409c8420dd07a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33762
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-08-09 20:19:34 +00:00
Marshall Dawson 2e0f2788a8 src/soc/amd/picasso: Update GPIO configuration
Make the definitions match Picasso's definitions.  Add/remove pins
that differ from stoneyridge, update GEVENTs for the FCH mapping.

Change-Id: I59f958151f27ed4ca0eb1a87ade6102eec1e5061
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-08-09 20:19:05 +00:00
Aamir Bohra 4c81167ce4 src/vendorcode/intel: Update Cometlake FSP headers as per FSP v1263
Change-Id: Ia29769f1fc9947d9e37de2534c9486d21a4c9eae
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-09 18:28:28 +00:00
Kyösti Mälkki bd7b245ff0 google/drallion: Fix build issue due to recent merge
One case slipped past the review and rebase of 733c28fa42
(soc/intel/{cnl,icl}: Use new power-failure-state API).

Change-Id: Id01df30d10e202e9672bf5be799a84f4f202fe24
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34812
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-09 16:03:07 +00:00
Kyösti Mälkki 2e3aff8d86 cpu/x86/smm: Drop SMI handler address from struct
Change-Id: Ib925b11ba269e0f3a9a0a7550705bf2a6794c5b1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34747
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-08-09 13:13:41 +00:00
Kyösti Mälkki 544369ebf3 amd/stoneyridge,picasso: Open TSEG earlier
Don't make assumptions about which subregion will
be accessed first.

Change-Id: I558fa4acc5068014b3748be6fc1bc34999054c0a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34775
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-09 13:12:45 +00:00
Nico Huber 6bbabef388 soc/intel/common: Set power-failure-state via option table
Allow get_option() to override the Kconfig choice.

Change-Id: Ie91b502a38d1a40a3dea3711b017b7a5b7edd2db
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34729
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-09 09:37:45 +00:00
Nico Huber 3e786b5546 soc/intel: Drop pmc_soc_restore_power_failure()
Get rid of this function and its dangerous, weak implementation.
Instead, call pmc_set_power_failure_state() directly from the SMI
handler.

Change-Id: I0718afc5db66447c93289643f9097a4257b10934
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-09 09:37:32 +00:00
Nico Huber 2fe596e677 soc/intel/apl: Implement power-failure-state API
Needed some Makefile changes to be able to compile for SMM.

Change-Id: Ibf218b90088a45349c54f4b881e895bb852e88bb
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-09 09:37:09 +00:00
Nico Huber 733c28fa42 soc/intel/{cnl,icl}: Use new power-failure-state API
pmc_soc_restore_power_failure() is only called from SMM, so add
`pmc.c` to the `smm` class. Once all platforms moved to the new
API, it can be implemented in a central place, avoiding the weak-
function trap.

Change-Id: Ib13eac00002232d4377f683ad92b04a0907529f3
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34726
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-09 09:35:22 +00:00
Nico Huber 04ce8fe6e3 soc/intel/skylake: Use new power-failure-state API
Also move pmc_soc_restore_power_failure() which was guarded twice to
not be included in SMM, where the only call lives. Once all platforms
moved to the new API, it can be implemented in a central place, avoi-
ding the weak-function trap.

Change-Id: Ie72753764ecd876e6cb999fa0074d1114ae5efcf
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34725
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-09 09:35:04 +00:00
Nico Huber ef19ce5346 soc/intel/common: Implement power-failure-state handling
This is a consolidation of the respective feature in `soc/intel/*lake/`,
including additional support for MAINBOARD_POWER_STATE_PREVIOUS.

For the latter, firmware has to keep track of the `previous` state. The
feature was already advertised in Kconfig long ago, but not implemented.

SoC code has to call pmc_set_power_failure_state() at least once during
boot and needs to implement pmc_soc_set_afterg3_en() for the actual
register write.

Change-Id: Ic6970a79d9b95373c2855f4c92232d2aa05963bb
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-09 09:32:28 +00:00
Yongqiang Niu 84d5d65bce soc/mediatek/mt8183: Add display controller driver
The MT8183 SOC has a DISP (display controller) that supports
overlay, read/write DMA, ... etc. The output of DISP goes to
display interface DSI, DPI or DBI directly.

Reference: MT8183 Application Processor Functional Spec,
 6.1 Display Controller

BUG=b:80501386,b:117254947
BRANCH=none
TEST=Boots correctly on Kukui

Change-Id: Ic4aecc58d081f14f5d136b9ff8e813e6f40f78eb
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-09 05:42:29 +00:00
Hung-Te Lin 7ece24634c soc/mediatek/mt8173: Refactor display driver to share common parts
Move those will be shared by other MTK SOCs (for example, MT8183) to
common/ddp.c.

BUG=b:80501386,b:117254947
BRANCH=none
TEST=Boots correctly on Oak

Change-Id: Ie5709ab6e263caa21fdf7e799dc2ee884ffaf800
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-09 05:42:05 +00:00
Hung-Te Lin 1c6e5a6e9d soc/mediatek/mt8173: Remove dual DSI mode
The 'dual DSI mode' was never used by any real boards running coreboot
and is introducing lots of complexity when it comes to refactoring.

In order to create a common display stack for MTK SOCs, we want to first
drop dual DSI mode so 8173 and 8183 DSI/DDP implementation will be more
similar to each other.

BUG=b:80501386,b:117254947
TEST=emerge-oak coreboot

Change-Id: I357c30cc687803ca8045d0b055dec2e22eef4291
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34693
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-09 05:41:22 +00:00
Sumeet Pawnikar ca38fbcdbf mb/google/sarien/variants/sarien: Set PCH Thermal Trip point to 77 degree C
PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and
DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal Shutdown
when S0ix is enabled.

BUG=None
BRANCH=None
TEST=Verified Thermal Device (B0: D20: F2) TSPM offset 0x1c [LTT (8:0)]
value is 0xFE on Sarien.

Change-Id: Ibc336be0523ff4e65a818474907faf20fc417ff4
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-09 01:32:53 +00:00
Sumeet Pawnikar dacd5b9a6a mb/google/sarien/variants/arcada: Set PCH Thermal Trip point to 77 degree C
PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and
DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal shutdown
when S0ix is enabled.

BUG=None
BRANCH=None
TEST=Verified Thermal Device(B0: D18: F0) TSPM offset 0x1c [LTT (8:0)]
value is 0xFE on Arcada.

Change-Id: I1915b974b10638b0f6ab97c6fb9b7a58d2cabc59
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-09 01:32:32 +00:00
Tim Wawrzynczak 680027edf6 soc/nvidia/tegra210: Fix potential NULL pointer dereference
Recent Coverity scan indicated potential NULL deference; if either
spi->dma_in or spi->dma_out are NULL, the fifo_error() check could
dereference a NULL pointer.

Also fixed what appears to be a logic bug for the spi->dma_out case,
where it was using the todo (count) from spi->dma_in.

Found-by: Coverity CID 1241838, 1241854
Change-Id: Icd1412f0956c0a4a75266d1873d5e9848aceee32
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34787
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-09 01:28:04 +00:00
Marshall Dawson 98f43a1f75 cpu/x86 mp_init: Add option for AMD INIT SIPI sequence
The common code adheres to the Intel requirement of bringing up the
cores with INIT SIPI SIPI.  This sequence is tolerated on some AMD
AMD CPUs but fails on others.  Add a way to skip the second SIPI.

TEST=Mock up on grunt and verify no errors
BUG=b:138919564

Change-Id: I201869003ddc7d04d332cd5734ac6d63979d89e0
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34759
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-09 01:26:18 +00:00
Tim Wawrzynczak 08eca5dcc3 mb/google/hatch: Refactor override_early_gpio_table
There was the potential for misuse of the override early GPIO table,
because if the override early GPIO table did not have a corresponding
entry in the base table, it would not get overridden, and there was
no way to know except manual inspection (this has already happened
here), so now all hatch mainboards are required to explicitly list out
all of their required early GPIOs.

TEST=booted several hatch boards, verified that they can communicate
with TPM and successfully train memory

Change-Id: I0552b08a284fd6fb41a09fef431a0d006b0cf0bd
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-08-09 01:25:46 +00:00
Karthikeyan Ramasubramanian c6e3708174 soc/intel/common/gspi: Use GSPI bus id to map to the controller
Currently SPI bus id is used to map to the controller in order to set
the controller state. In certain platforms SPI bus id might not be
exactly the same as GSPI bus id. For example, in Intel platforms SPI bus
id 0 maps to fast spi i.e. SPI going to the flash and SPI bus id 1 .. n
map to GSPI bus id 0 .. n-1. Hence using SPI bus id leads to mapping to the
GSPI controller that is not enabled. Use the GSPI id bus so that the right
controller is set to active state. This fixes the regression introduced
by CB:34449

BUG=b:135941367
TEST=Boot to ChromeOS.

Change-Id: I792ab1fa6529f5317218896ad05321f8f17cedcd
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-08-09 01:23:19 +00:00
Jonathan Neuschäfer 3a4511eb6c arch/riscv: Enable FIT support
Tested on qemu-riscv.
Depends on OpenSBI integration and proper memory detection in qemu.

Boots into Linux until initrd should be loaded.

Tested on SiFive/unleashed:
Boots into Linux until earlycon terminates.

Change-Id: I5ebc6cc2cc9e328f36d70fba13555386bb8c29d6
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30292
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-08 13:03:59 +00:00
Joel Kitching 2a20d13c39 vboot: fix conditional using vboot_setup_tpm return value
vboot_setup_tpm returns (TPM_SUCCESS == 0) on success.
In this case, call antirollback_read_space_firmware.

This regression was introduced in CB:34510.

BUG=b:139101213
TEST=make clean && make test-abuild
BRANCH=none

Change-Id: Ifdea1d85167a50a1ada5afe9b107408e3a2e0d6f
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34790
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-08 07:03:24 +00:00
Subrata Banik 2524928f5d soc/intel/{APL, BSW, SKL}: Remove unused CPU_ADDR_BITS kconfig
This patch removes CONFIG_CPU_ADDR_BITS kconfig from
soc/intel/<soc>/Kconfig as not getting used anymore.

Change-Id: Ie7fa386c9c0aae19da1fbd09407494d9812247a4
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34768
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-08 04:57:28 +00:00
Subrata Banik 6c8a040ec5 cpu/x86/mtrr: Replace CONFIG_CPU_ADDR_BITS with cpu_phys_address_size()
This patch helps to generate correct MTRR mask value while
using set_var_mtrr().

example:
set_var_mtrr(1, 0x99000000, 16*MiB, WP)

without CL :
0x0000000099000005: PHYBASE2: Address = 0x0000000099000000, WP
0x0000000fff000800: PHYMASK2: Length  = 0x0000007001000000, Valid

with CL :
0x0000000099000005: PHYBASE1: Address = 0x0000000099000000, WP
0x0000007fff000800: PHYMASK1: Length  = 0x0000000001000000, Valid

Change-Id: Ie3185dd8d4af73ec0605e19e9aa4223f2c2ad462
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34753
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-08 04:57:09 +00:00
Kyösti Mälkki 41d9b65149 soc/intel: Fix SMRAM base MSR
Previous setting was correct but assumed SMI handler is
always located at the beginning of TSEG. Break the assumption.

Change-Id: I5da1a36fc95f76fa3225498bbac41b2dd4d1dfec
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34730
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-08 04:57:03 +00:00
Kyösti Mälkki d157b3e1e0 arch/x86: Handle smm_subregion() failure
The callers don't necessarily check return value of
function. Make sure the parameters are not left
uninitialised in that case.

Change-Id: Ic02db2d35b2ec88506320e7df609940de4aef005
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34708
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-08 04:56:03 +00:00
Kyösti Mälkki 14222d8678 arch/x86: Change smm_subregion() prototype
Do this to avoid some amount of explicit typecasting
that would be required otherwise.

Change-Id: I5bc2c3c1dd579f7c6c3d3354c0691e4ba3c778e1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-08-08 04:53:18 +00:00
Kyösti Mälkki 9970b61ad3 arch/x86: Move TSEG_STAGE_CACHE implementation
This is declared weak so that platforms that do not
have smm_subregion() can provide their own implementation.

Change-Id: Ide815b45cbc21a295b8e58434644e82920e84e31
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-08 04:51:32 +00:00
Kyösti Mälkki 0a4457ff44 lib/stage_cache: Refactor Kconfig options
Add explicit CBMEM_STAGE_CACHE option. Rename
CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM to TSEG_STAGE_CACHE.

Platforms with SMM_TSEG=y always need to implement
stage_cache_external_region(). It is allowed to return with a
region of size 0 to effectively disable the cache.

There are no provisions in Kconfig to degrade from
TSEG_STAGE_CACHE to CBMEM_STAGE_CACHE.

As a security measure CBMEM_STAGE_CACHE default is changed to
disabled. AGESA platforms without TSEG will experience slower
S3 resume speed unless they explicitly select the option.

Change-Id: Ibbdc701ea85b5a3208ca4e98c428b05b6d4e5340
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-08 04:50:33 +00:00
Raul E Rangel cccb815c5e util/abuild: Clean up the missing_arches check
This change adds the following improvements:
* Easier to read.
* Checks to see if .xcompile is complete.
* Checks the make return code. This will catch if .xcompile is missing.

BUG=b:112267918
TEST=Modified my .xcompile and ran abuild and verified that
missing_arches got set correctly. Also deleted .xcompile and verified
there was a failure.

Change-Id: I7604d431f398fc0c80a857a0c7c21e164004cc99
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-08-08 03:42:24 +00:00
Frans Hendriks f4d2c8714f vendorcode/eltan/security: Use config VENDORCODE_ELTAN_XXX
To avoid confusion use VENDORCODE_ELTAN_VBOOT and
VENDORCODE_ELTAN_MBOOT config values.

Include verfied_boot and mboot subdirectories as CPPFLAGS when
measured boot or verified boot is enabled. This allows to generate
binary with measured boot enabled only.

BUG=N/A
TEST=Boot Linux 4.20 and verify logging on Facebook FBG-1701

Change-Id: Iaaf3c8cacbc8d2be7387264ca9c973e583871f0a
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33442
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-08 03:37:51 +00:00
Dawei Chien bab69c3fe2 3rdparty/blobs: Update submodule for MT8183
Update the 3rdparty/blobs submodule to the newest HEAD, which
contains the SPM binary for MT8183 platforms
( https://review.coreboot.org/c/blobs/+/34543 ).

Change-Id: I505ec9fffd9ddd62fffbe9514cbba50625825693
Signed-off-by: Dawei Chien <dawei.chien@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34734
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-08 03:29:07 +00:00
Patrick Rudolph 3d41a13990 drivers/ipmi: Add option to wait for BMC
The BMC on Supermicro X11SSH takes 34 seconds to start the IPMI KCS, but
the default timeout of the IPMI KCS code is just 100 msec.

Add a configurable timeout option to wait for the BMC to become ready.
As it only should boot very long after power on reset, it's not a
problem on reset or warm boot.

Tested on Supermicro X11SSH.
The IPMI driver doesn't fail with a time-out any more.

Change-Id: I22c6885eae6fd7c778ac37b18f95b8775e9064e3
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-08-08 03:24:18 +00:00