Use shared gpio code from common folder, except for
INTEL_LYNXPOINT_LP, which has it's own gpio code.
Needs test on real hardware !
Change-Id: Iccc6d254bafb927b6470704cec7c9dd7528e2c68
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/13615
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Use shared gpio code from common folder.
Bd82x6x's gpio.c and gpio.h is used by other southbridges
as well and will be removed once it is unused.
Change-Id: I8bd981c4696c174152cf41caefa6c083650d283a
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/13614
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Having two separate memlayouts is an unnecessary complication.
Contributors need to make sure that their code fits into the vboot one
(with smaller stage sizes) either way, and the Tegras have plenty of
SRAM anyway. Let's just make the vboot layout the default (as it was
done on other SoCs) to keep things easier to maintain. The empty SRAM
holes on non-vboot systems where the verstage and work buffer would've
been won't hurt them.
BRANCH=None
BUG=None
TEST=Ran abuild with and without --chromeos on Foster, Rush, Ryu and
Smaug.
Change-Id: If37228facb4de1459cc720dca10bf03e04eb9930
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13667
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This makes the test IDs the default, taken from depthcharge
master (board/*/fmap.dts, hwid property).
Change-Id: I25793962ac16f451f204dbba6ede6a64c847cfd5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13634
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
Those aren't used anymore.
Change-Id: If7baf2d03c47bcc6f69d63a349bbf9d5e749aeac
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13685
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This was copied from mrc structure despite them having fields in different
order.
Change-Id: If10ffa3316c5fdc538a6fabf2409512bc8c3e676
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13661
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
veyron_speedy was deduplicated as sub-board into google/veyron, so the
addition of chromeos.fmd (identical btw) wasn't useful.
Change-Id: Ic4eb6f5fefb0812cae1b9c0475e3a296d7fa65b6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13646
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This is needed for stout EC init.
Change-Id: I5c73499c17763229840152a473a2d820802ee2f6
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13535
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
For devices with Chrome EC, state the "board" name(s), so they're built
as part of the image.
A number of EC boards aren't supported in the Chrome EC master branch,
they're brought along but commented out, waiting for a port to master
in the Chrome EC code base.
Change-Id: Ic6ab821de55cf9b4e8b48fe5ebc603adeb8bb28b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13548
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
As the audio card needs 1.8V I2C operation. This patch adds
entry into devicetree.cb to set I2C port 4 operate at 1.8V.
TEST=Built & booted lars board. Verified that I2C
port 4 is operating at 1.8V level
Change-Id: Ia77841a26d024785d53251ca4b17afcf77f36a5b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e431e7acd85f6d7bf9d47f54ed41c48b8276071c
Original-Change-Id: Iccc85a5e3bbf2b5362665036e1294a6635e38fbe
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/321000
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/13627
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Enable the option to back up Vboot non-volatile data from CMOS
to flash as these boards have the necessary nvram fmap region
and are using vboot2 which does not backup to the TPM.
BUG=chrome-os-partner:47915
BRANCH=glados
TEST=manually tested on chell
Change-Id: I7bfe88f2cb7826f3315987aaf56f77df708896ce
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 35df03c5ef24406129cba920ee9af6d55458cd45
Original-Change-Id: Ia7c014fe2768c55941a65ec5605ef4fbc986151c
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/324123
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13601
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
The developer mode gpio switch on rialto is always hardcoded (through a
resistor) as developer mode. We need to ignore it to allow transitions to
verified mode with the virtual developer mode stuff.
TEST=We can now exit dev mode on rialto
Change-Id: I94a949f0973132de5fd008224af79cf612151193
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e78bb8f81eaa9c082e47ad818b64843c2565d00b
Original-Change-Id: If11d752d58a5f26fc270ef01b529dad18b4cce46
Original-Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/325861
Original-Commit-Ready: Alexandru Stan <amstan@chromium.org>
Original-Tested-by: Alexandru Stan <amstan@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13626
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
These devicetree patches set the ACPI PM Disabled variable to 1.
This will disable the ACPI PM timer and remove from FADT table.
BRANCH=none
BUG=chrome-os-partner:48646
TEST=Build for skylake board with the PmTimerDisabled policy in
devicetree set to 1.
iotools mmio_read32 0xfe0000fc should return 0x2.
cat /sys/devices/system/clocksource/clocksource0/available_clocksource
should list only "tsc hpet". acpi_pm should be removed from this list.
Change-Id: Ia66f37e13f0f2f527651418b8b5c337b56c25c7f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: db3e8130495038850c7034b89701b4a5fcf88dce
Original-Change-Id: Ib1b876cfa361b8cbdde2f9e212e3da4fd724e498
Original-Signed-off-by: Archana Patni <archana.patni@intel.com>
Original-Signed-off-by: Subramony Sesha <subramony.sesha@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/319362
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13589
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
In order to support both separate verstage and a verified boot after
romstage one needs to ensure the proper GPIO and EC configuration
been complete. Therefore, move that logic to
car_mainboard_post_console_init() in car.c file which gets called
in the early flow of a CAR stage (either verstage or romstage).
BUG=chrome-os-partner:44827
BRANCH=glados
TEST=None
Change-Id: I331f25ad4764cab972af7198f6154f604d2dbeae
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2c1cb04645cbf34696e6adf48acec9d396e87ca9
Original-Change-Id: I8d14ea16b2d07bbf04c5c33e4205a85d9f21847b
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/324075
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/13585
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
In order to support both separate verstage and a verified boot after
romstage one needs to ensure the proper GPIO and EC configuration
been complete. Therefore, move that logic to
car_mainboard_post_console_init() in car.c file which gets called
in the early flow of a CAR stage (either verstage or romstage).
BUG=chrome-os-partner:44827
BRANCH=glados
TEST=Built glados w/ separate verstage and booted.
Change-Id: I626a500c183d21f94d976e24f09af15a242fba9c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b564514a8b93f53a919fcdac3589e30dbac82124
Original-Change-Id: Icc989ec5700b3f1a144a6b41198b7dd2c2aac6f7
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/324073
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/13583
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
In order to support both separate verstage and a verified boot after
romstage one needs to ensure the proper GPIO and EC configuration
been complete. Therefore, move that logic to
car_mainboard_post_console_init() in car.c file which gets called
in the early flow of a CAR stage (either verstage or romstage).
BUG=chrome-os-partner:44827
BRANCH=glados
TEST=Built chell w/ separate verstage and booted.
Change-Id: Ic728c2904006376fdc2b27b512f72173a2260be3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 42d190af8996fea894305ebe686afbfda5f2b8a5
Original-Change-Id: I95aeb97737d0ddfa6c53269c9d14db16ed5e47cc
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/324072
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/13582
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Move the default select of "Use native graphics initialization" for
Peppy to the ChromeOS section as SeaBIOS (default payload) requires a
vBIOS and takes twice as long to load with this option enabled. For the
same reasons, this option shouldn't be enabled by default (def_bool y).
Change-Id: I1f2163e0a1e4bf8e5041dad150bdf7de804fb4db
Signed-off-by: Jean Lucas <jean@4ray.co>
Reviewed-on: https://review.coreboot.org/13493
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Some trivial cleanup.
Change-Id: I866efc4939b5e036ef02d1acb7b8bb8335671914
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13427
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Disabling S5 wake from touch panel and trackpad
TEST=Build and boot the platform.
TEST=Poweroff platform -> enter PG3 -> remove AC -> close Lid
Plug AC in -> EC boots up and AP will shutdown the platform
and open Lid -> platform boots to OS.
Change-Id: I7b661a9f1327b97d904bac40e78612648f353e39
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/288970
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Divagar Mohandass <divagar.mohandass@intel.com>
Original-Tested-by: Divagar Mohandass <divagar.mohandass@intel.com>
Reviewed-on: https://review.coreboot.org/13425
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The codec clock frequency was incorrectly set to 25MHz.
The only available frequency is 19.2MHz through external clock and PLL.
Original-Reviewed-on: https://chromium-review.googlesource.com/295768
Original-Tested-by: Hannah Williams <hannah.williams@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I9bef334a5a3aaee28fcc4937180896ff49969bc5
Signed-off-by: Felix Durairaj <felixx.durairaj@intel.com>
Reviewed-on: https://review.coreboot.org/12732
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
BRANCH=none
BUG=chrome-os-partner:47609
TEST=remove servo board connection and insert/remove an empty SD card
in recovery mode.
Change-Id: I89a1cb6914d634f07ff71b9793eb29b711381524
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d21bf091a576574cb9e976447ee2b9a69748d2b6
Original-Change-Id: I2083605c9ad88841885dfaad48dcd27e6fb5161d
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/313073
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13099
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
BRANCH=none
BUG=none
TEST=boot to kernel
Change-Id: I0630d7c172e97f81abb1722afe028542e9e7f106
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 608c66df0543c76be7e811b06718464776631b55
Original-Change-Id: I03426085121bfa44c99c351d63db28f567d0ee1d
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/313969
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13097
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
BRANCH=none
BUG=none
TEST=build pass and verified on rev3
Change-Id: I3849342e59c2b022db723ef0281cdd5153ae27cb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 495e978cd7381bd393099315ac6d60fe4446dd9f
Original-Change-Id: I9626d06746e5d0bf6698a9b8e7594c58e7ff213a
Original-Signed-off-by: Ben Lok <ben.lok@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292689
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13096
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Since backlight is controlled in depthcharge, we only configure
control pins as output pin and set them power-off in the coreboot
stage.
BRANCH=none
BUG=none
TEST=Saw DEV screen during boot process.
Change-Id: I3ed95e133417194ec8e774f42770bc61d879295f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e9628781801943903ba99ba1071aa374c6fc0754
Original-Change-Id: Ifd101f3e08698561d8516d83bc7d502d210e3b66
Original-Signed-off-by: YH Huang <yh.huang@mediatek.com>
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292686
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13093
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
BRANCH=none
BUG=none
TEST=build and verified pass on oak board
Change-Id: I01eb059a3525bbbc5d17335cf43bc01be4355142
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bc2bb9f5b461ec848df8aba07940b895401004f8
Original-Change-Id: I848468cec04a36659fbb4b898dff9368305d72ac
Original-Signed-off-by: Koro Chen <koro.chen@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292683
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13092
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Add support for verstage
[pg: split original commit into multiple commits]
Change-Id: I8c9fe02f26bf8fa8381a7502a778bed300684986
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2827aa08ff8712c0245a22378f3ddb0ca054255d
Original-Change-Id: I94a9ee2c00e25a37a92133f813d0cd11a3503656
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292662
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13052
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
WRDD method in wifi.asl returns the regulatory domain code. This value
is read from VPD in wifi_regulatory_domain() and saved to global nvs if
CONFIG_HAVE_REGULATORY_DOMAIN is enabled. It returns default code if
CONFIG_HAVE_REGULATORY_DOMAIN is not enabled.
Change-Id: I6e96bdf0fe93ae30a3afdcb63a0f89ce21023704
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/13055
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Updating EC+PD takes long enough to update that it is good to
show the "critical update" screen when doing an EC/PD update.
BUG=chrome-os-partner:49650
BRANCH=glados
TEST=Build and boot on chell in normal mode with an EC update payload
and ensure that it reboots to enable graphics, shows the "critical
update" screen, and then reboots to disable graphics init again.
Change-Id: I436b96b95595b68273e594bdcfe2db0789ee26b2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 08e45decd066f8f57ad103ff8b76cb7a916afa9e
Original-Change-Id: Ie250f4531437e4a0ce14b5aeb0fe564e9461fe4d
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/322783
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13075
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This is a follow-up to CL:320623 to make veyron DRAM configs
uniform (except for Rialto).
As discussed in chrome-os-partner:43626, the mr[3] value and ODT
are set diffently for Mickey, thus the .inc files for other boards
have mr[3] = 1 and ODT disabled.
BUG=none
BRANCH=veyron
TEST=compile tested for veyron
Change-Id: I61798cfef779b0a3a510fd354ab53ffc63ca6c95
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3b7cea6331bcec8aba09a204060e093d3dd732cb
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: Iacf821645a2dcceaed1c1c42e3e1b1c312b31eab
Original-Reviewed-on: https://chromium-review.googlesource.com/321870
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13109
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
These are generated from depthcharge's board/*/fmap.dts using the
dts-to-fmd.sh script.
One special case is google/veyron's chromeos.fmd, which is used for a
larger set of boards - no problem since the converted fmd was the same
for all of them.
Set aside 128K for the bootblock on non-x86 systems (where the COREBOOT
region ends up at the beginning of flash). This becomes necessary
because we're working without a real cbfs master header (exists for
transition only), which carved out the space for the offset.
Change-Id: Ieeb33702d3e58e07e958523533f83da97237ecf1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/12715
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Update Hynix memory configuration for mickey
so that it can boot on Hynix board.
BUG=chrome-os-partner:48637
BRANCH=master
TEST=Boot on mickey hynix board
Change-Id: Ibbf90cf76793005e23a720b97540b268ebf0864d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 071167b667685c26106641e6899984c7bd91e84b
Original-Change-Id: Id63d74cac36b9fd84bdb88969291982e14fa7d01
Original-Signed-off-by: Lang Zhang <kingsley_zhang@asus.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/320623
Original-Commit-Ready: lang zhang <kingsley_zhang@asus.com>
Original-Tested-by: lang zhang <kingsley_zhang@asus.com>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://review.coreboot.org/13048
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Migrate google/tidus (Lenovo ThinkCentre Chromebox) from Chromium
tree to upstream, using google/guado as a baseline.
TEST=built and booted tidus with full functionality
Change-Id: I9d7a976345566bee63226d1a44ba7d5ec137a742
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/12801
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Set "nuvoton,sar-threshold" property to thresholds
based on tuning with the Android Wired Headphone
Compatibility Kit and Chell EVT.
Also set properties nuvoton,sar-compare-time and
nuvoton,sar-sampling-time.
The values of compare and sampling time align with
the ones from this CL:
https://chromium-review.googlesource.com/306372
Signed-off-by: Benson Leung <bleung@chromium.org>
BUG=chrome-os-partner:49333
BRANCH=none
TEST=Run evtest, selecting the input event for sklnau8825adi
Using the Nominal headphones from the kit, check that the
buttons for "KEY_VOLUMEDOWN", "KEY_VOLUMEUP", "KEY_MEDIA",
and code 582 (?) (should be voice search, but evtest doesn't understand)
All of these buttons should work properly.
Change-Id: I43dc1957f7d95744f41039a306d323806e66c56a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2bb545500afeb5b4fa0d1cd02dbf6453f19901ab
Original-Change-Id: I126aae1e5ed1b9e1a2429e8c94fe08b3ba3ca736
Original-Reviewed-on: https://chromium-review.googlesource.com/322243
Original-Commit-Ready: Benson Leung <bleung@chromium.org>
Original-Tested-by: Benson Leung <bleung@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13013
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
After comparing datasheets it appears to have the same geometry
and timings as the K4E6E304EE-EGCF part with just a new part number.
BUG=chrome-os-partner:49357
BRANCH=glados
TEST=build and boot on chell EVT (new part is not used until DVT)
Change-Id: Ia1e67080b1d79600e00c3ea8bee088ecafea2ab2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fb1488ca5ff780b5f1f937dbf0d23610c28204b2
Original-Change-Id: I09e1ce1a45a217afc88f422cf7db7924fad6b6f9
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/321956
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13011
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
- Enable serial irq configuration in FSP.
- Set minimum assertion width values for FSP to configure.
- Set I2C4 voltage to 1.8V.
- Enable SaGv feature to dynamically train memory frequency.
BUG=chrome-os-partner:47688
BRANCH=none
TEST=build and boot on chell EVT
Change-Id: If6955c9ee4f08d1ebc6e98e0ba0786073919856f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7403149299ec2c6c66c2066a5dd8294608e71409
Original-Change-Id: Ia182396ad4eb7a283e183fce7c50c98f6d2de57c
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/321212
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13009
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
- Enable serial irq configuration in FSP.
- Set minimum assertion width values for FSP to configure.
- Set I2C4 voltage to 1.8V.
- Enable SaGv feature to dynamically train memory frequency.
- Disable Deep S3 to match chell so DeepSx story is consistent
on skylake-y boards.
BUG=chrome-os-partner:47688
BRANCH=none
TEST=emerge-glados coreboot (tested on chell board)
Change-Id: Ied6bda6a3f2108df7167e0970abe71977d8d2a5c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fbf353288edc9629ad03b17d0a582e3042d5a5e1
Original-Change-Id: I1619dd5316060793f38b74f8f0bcaf23d8ab2552
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/321211
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13008
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The keyboard backlight is very bright at 100% so be more
subtle when turning it on at boot time.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=build and boot on chell EVT
Change-Id: I3925b94b4a455eb7d3bbb6eee414d21cf6d3bb93
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 52da1456527bfa6e0a3290c87c4886e2b3111e21
Original-Change-Id: Ia3412b4052c96f5de8e8aef59f69f6b346b9aca8
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/321210
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13007
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Below are the correct RCOMP Target Values:
Samsung K4E6E304EB part = {100, 40, 40, 21, 40}
The rest of the DIMMs should have RCOMP set to
{100, 40, 40, 23, 40}
LARs EVT has new DIMM configurations, and the earlier RCOMP
settings are not correct for the newly added DIMM cards,
causing reboot issues.
With this patch all the DIMMs get the required values programmed.
BRANCH=None
BUG=None
TEST=Built for Lars EVT SKU1/2/3 and verified Boot to OS.
No Reboot after this change.
Change-Id: I5fa5ce47b4b47198b0ae8d0b57f7729cb57d23bf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d29cc8a4ad9bc2b7680e4df146ce281738e4a3c4
Original-Change-Id: I15195b748213553907ff22dbc74651d70f3c7bb6
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/320527
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13005
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Kingston eMMC can now run under HS400 mode.
BUG=chrome-os-partner:48017
BRANCH=none
TEST=run consecutive boot 100 times on Lars proto Kingston SKU, and
MMC errors didn't happen.
Change-Id: I3c16db6111273fbbabbfba1c315edc780fe23525
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ac474bd7bd33f11904a27691e9eb61bdaf212c6b
Original-Change-Id: I9e47b6ba64ac94acff7673fca86fa62bfb30edd9
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/320194
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/13004
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This change enables SaGv feature for skylake
platform. As a result of this patch the skylake
platform will train memory at both low & high
frequency points. This will be used to
dynamically scale the work point
(voltage/frequencies).
The value "3" here means enable. Following
is the table for same.
0=Disabled (SaGv disabled)
1=FixedLow (Fixed to low frequency)
2=FixedHigh (Fixed to High frequency)
3=Enabled( SaGv Enabled.Dynamically changes)
BRANCH=None
BUG=chrome-os-partner:48534
TEST=Build and boot lars
Change-Id: I82b1a428d2d3dce47f46de576f677cf2249b6b5d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8e252123cc73543d0f1b320af9d8873f99a45ab1
Original-Change-Id: I1a545ff2f38df23964378c0d833e29006b2c5557
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/320022
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-by: Haridhar Kalvala <haridhar.kalvala@intel.com>
Reviewed-on: https://review.coreboot.org/13002
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
MP init is already handled in coreboot, but it is also part of FSP
FSP has a implemented a provision to allow FSP to skip MP init and
let coreboot handle it.
BRANCH=none
BUG=chrome-os-partner:44805
TEST=none
CQ-DEPEND=CL:319353
Change-Id: I22c1add182b299e2ad9d413bc13c5a5acc6a3179
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ccf89c9d1fe18b74c385e7d12a6aef5b63d7b243
Original-Change-Id: I53b754fd10a140588ad67d9292d9bc04a6d43677
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/319194
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13000
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
MP init is already handled in coreboot, but it is also part of FSP
FSP has a implemented a provision to allow FSP to skip MP init and
let coreboot handle it.
BRANCH=none
BUG=chrome-os-partner:44805
TEST=Build and booted in Lars with SkipMpInit enabled from CB
CQ-DEPEND=CL:319353
Change-Id: Ib35d9072b883592d22466dfeb1fd45403c0479d4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 91cf59ea7865568eca2ce242d81c4c486076d5ac
Original-Change-Id: Ibb46fc6bc7e862c9ea8bc9f9b0d508c3707282a2
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/319257
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12999
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
MP init is already handled in coreboot, but it is also part of FSP.
FSP has a implemented a provision to allow FSP to skip MP init and
let coreboot handle it.
BRANCH=none
BUG=chrome-os-partner:44805
TEST=none
CQ-DEPEND=CL:319353
Change-Id: I81c54582a3c980ecdcf329347bcd5982802d681c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e60ee81acaeb1062a31a3e78ed2ba4ccfe816ec5
Original-Change-Id: I71dd07559dffb7886e489274ffc8e71686ca730f
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/319370
Original-Commit-Ready: Preetham Chandrian <preetham.chandrian@intel.com>
Original-Tested-by: Preetham Chandrian <preetham.chandrian@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12994
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Lars has an ambient light sensor connected to the EC which
is presented to the OS as a standard ACPI0008 device.
BUG=none
BRANCH=none
TEST=emerge-lars coreboot
Change-Id: I406b634176dac3f4cf1894e6b386af3306d11ffa
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 37d96458a11c33899f210cc04d3bdab07ec18746
Original-Change-Id: I017aeed1a8684676557e483ffa895dc4bb125d26
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/319364
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12990
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Use the Kunimitsu settings as baseline, except Psi4Enable set to 0 due
to a known issue (not able to hit S0ix) on glados. The VR settings will
then need to be updated per the board VR design.
BRANCH=none
BUG=chrome-os-partner:48466
TEST=Build and booted chell
Change-Id: Ieb014e2a0cee1cb02a1c095da273b5ac1a19ef5d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fcd47a2fb2b369a93d2992fa1c17c2ce91c0e948
Original-Change-Id: Iac197314702fe5897359afc1ad1636bbcdafa204
Original-Signed-off-by: robbie zhang <robbie.zhang@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/317870
Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/12985
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Use the Kunimitsu settings as baseline, except Psi4Enable set to 0 due
to a known issue (not able to hit S0ix) on glados. The VR settings will
then need to be updated per the board VR design.
BRANCH=none
BUG=chrome-os-partner:48466
TEST=Build and booted glados
Change-Id: I42d360657ab7c47d66043f39b79540b69a9072d1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d06397c1c32136d1b6a1c1346ed722ad6926ce1a
Original-Change-Id: Ib0746cd84c2c8af29f53a65a0a7b85966c918869
Original-Signed-off-by: robbie zhang <robbie.zhang@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/317910
Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/12984
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Copy changes from chell to add 20K pull-up to LPC address lines
and setup the PCH_WP signal early so it is set correctly in VBNV.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-glados coreboot
Change-Id: I3337cb9e5ee445471c7a0b61ee22869f66189b63
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c99dae3729636790c2ad457ec3271d2bd99fb1c4
Original-Change-Id: I7627ec263e710ce186cea15c805203395acf3e99
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/317244
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12982
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
- Add pullup on LPC address lines for leakage
- Configure PCH_WP early so it gets set properly in VBNV
- Disable SD card reader in favor of USB
BUG=chrome-os-partner:47346
BRANCH=none
TEST=build and boot on chell EVT
Change-Id: Ibac79c6cbef0515b1e8a513cfde5fee184e4c70a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ebd0c16a6009b74d3c6c36878c502fda9bb3020d
Original-Change-Id: If2bc4eb546a1aab50d3688b6e92f8c38214c9cca
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/317241
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12979
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Follow kunimitsu setting of
https://chromium-review.googlesource.com/#/c/313068/
BRANCH=none
BUG=chrome-os-partner:48459
TEST=Build and boot in lars
Change-Id: Iffa9e1307f478b1d72befd3e5af71e7d40bb55ef
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6c669014d0773d6790656dd6f957d2c860d00781
Original-Change-Id: I615d53a33ad8e750d4382e2a9ec397c5b6ff55e1
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/317222
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12978
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The write protect GPIO is not being configured early enough.
This is leading to coreboot reading incorrect value, and
writing the incorrect value in vboot shared file.
This is leading to "crossystem wpsw_boot" always returning 0
even with the write protect screw in place during boot.
BRANCH=none
BUG=chrome-os-partner:48292
TEST=Build and boot on lars
Change-Id: I28fbbd690ca6efb539422e9ba02f10e07cd35346
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d229ba9d8934dcb5f22b27ce0ad27601ec87d6ff
Original-Change-Id: I64f2497a6bb3a50b0f58c67e2ab6751c4836fd89
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/317130
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12966
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The HeciEnabled decides the state of Heci1 at end of boot. Setting to 0
(default) disables Heci1 and hides the device from OS. It internally uses
the FSP Psf Unlock policy to disable the Heci1. It also adds the p2sb
device in the devicetree which is necessary for hiding and unhiding the
device.
BRANCH=none
BUG=chrome-os-partner:45618
TEST=build for kunimitsu.
CQ-DEPEND=CL:*238451
Change-Id: Ieba2ab3b4ac518cce8371069028170ba99aaf079
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cbefe9d6e9a981594534d346be67a5cd94483d05
Original-Change-Id: I8c95b5b9b28ba8441ca031f4e9ec523d913990d6
Original-Signed-off-by: Archana Patni <archana.patni@intel.com>
Original-Signed-off-by: Subramony Sesha <subramony.sesha@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/311913
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12977
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Enable the config option for TPM to use PIRQ instead of SERIRQ
and enable the MAINBOARD_HAS_LPC_TPM option.
BUG=none
BRANCH=none
TEST=tested this patch with TPM ACPI driver(tpm_tis.force=0)
Change-Id: I761d623d1064b8030f2703500d174259bb20ca79
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2f7bdb1091b7dd62a3c0b4a2272ab9f56fd7acc9
Original-Change-Id: Id1a867980d2e28a1f328aa36bed3c846b2137bec
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/317471
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/12974
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
At S0, S0ix and S3 LPC LAD signals are
floated at 400~500mV.
BRANCH=none
BUG=chrome-os-partner:48331
TEST=Build and boot on lars
Change-Id: I5582007e5caaf444740fa71c9761c27614aafee2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b855fd5834056a3f7d4aef91d634066006990a38
Original-Change-Id: I3a54f9f83f055e433cc1fea38169437ee7f9188f
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/317071
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12965
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Remove the WakeConfigWolEnableOverride to disable WOL override
configuration in the General PM Configuration B (GEN_PMCON_B) register
BRANCH=none
BUG=none
TEST=Build and boot on lars
Change-Id: I48d3b706517b6ea6bda44800f61bb11da64503fb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: eab69f2d725df739e5e0e5901a581ad58732cdf9
Original-Change-Id: I42c5a87150638171526ee67f194c1cd9d155203b
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/317080
Original-Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12962
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Provide an option for including the NHLT blobs within the
lars mainboard directory while also adding the ACPI NHLT
table generation that the current hardware supports.
BUG=chrome-os-partner:44481
BRANCH=None
TEST=Built and booted lars board.
Audio worked with MAXIM audio card.
Change-Id: I1b7836c685ebbe1498f3dbaa2eb64d5e0d4faabb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 401f1a7b23dca19712517ed1588e1390769d1271
Original-Change-Id: I6a937872a9e10d2c5ea15d5952d23e98416df092
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/316092
Original-Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12961
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Make sure the latest & greatest Intel targets actually
build in our build system.
intel/sklrvp is still failing for reasons unrelated to the rest
of the skylake boards. Leaving that disabled for now.
Change-Id: Ie784628a57257cea30e5e47074648198b884f6db
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12857
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
DPTF may power off the system when it starts if the CPU temp is >90C.
Since TJmax is 100C set the critical threshold to just below that value.
BRANCH=none
BUG=none
TEST=Build and boot on lars.
Change-Id: I3abf946ae09c3c691480e468d0c1d74730dc6c06
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7c2230009edb840e88a20c2d8a87f942c09b6bf3
Original-Change-Id: Iee1a3596dbbe934f68637f012c02c078c3751eeb
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/316102
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/12955
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Disable kepler device, it is removed and was not used on proto anyway.
BUG=none
BRANCH=none
TEST=build and boot on lars proto
Change-Id: I137b82b8dca23f5b40adcc6a056e77a4ff54d4d5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 44d63453a9b31331d13d05f8f86d4218af0f0aa1
Original-Change-Id: Ib0892bf93b1d0cda1c0143d2b16cd58aeda83131
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/315950
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/12950
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Currently, the Power Limit 1 (PL1) value is 6W which is
low for high performance KPIs. This patch updates PL1
value as TDP. SKL-U has 15W TDP.
BRANCH=none
BUG=none
TEST=Build and booted on lars.
Change-Id: Ic1313385e0aa1760b473a34c853a95c76257eecf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a47faee53e08da81602b485937621fd49eb2ddbf
Original-Change-Id: I7c91dcdc82525a6d2b706f8f504ba48601097ef7
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/316370
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/12953
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
modify the P/N in samsung K4E6E304EE-EGCF SPD from K4E6E304ED-EGCE to
K4E6E304EE-EGCF
BRANCH=none
BUG=chrome-os-partner:48299
TEST=build chell and use gooftool to probe and P/N match
Change-Id: Ie560e5c0d4b9a3cfb34c3856911930fb8159764e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: dabe5eaa8abf54f4e4a5492062adca6ef9b4634d
Original-Change-Id: Ie8d44ac6032e5213928bfae2a2ac5877d4193d62
Original-Signed-off-by: Wisley <wisley.chen@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/316100
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/12951
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Provide an option for including the NHLT blobs within the
glados mainboard directory while also adding the ACPI NHLT
table generation that the current hardware supports.
BUG=chrome-os-partner:44481
BRANCH=None
TEST=Built and booted. Headphones, speakers, and mic on camera
emits and creates sound albeit not the greatest.
Change-Id: Iaf910041453695b7125b254ca5d71e8ccbd0b02f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ea77d326ba1c33b100c34066ed361a55dfa14ce3
Original-Change-Id: I5d93c3a7fa4cf68ba91f1398b4bd04504a28fef2
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/315520
Original-Tested-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/12948
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Provide an option for including the NHLT blobs within the
glados mainboard directory while also adding the ACPI NHLT
table generation that the current hardware supports.
BUG=chrome-os-partner:44481
BRANCH=None
TEST=Built and booted. Headphones, speakers, and mic on camera
emits and creates sound albeit not the greatest.
Change-Id: I6e36c0a99a73cdcb2bf6ccfbfc886a594f989a39
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5b0383a93f054011dd7c18519ece4e6f1944366d
Original-Change-Id: I6f8bd15c72fa89756382af99bddb6cb6abe89905
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/313794
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/12939
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This continues what was done in commit a73b93157f
(tree: drop last paragraph of GPL copyright header)
Change-Id: Ifb8d2d13f7787657445817bdde8dc15df375e173
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12914
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Because these platforms haven't been getting build testing, they've
missed out on some of the improvements that the other platforms have
gotten.
Enable MAINBOARD_HAS_LPC_TPM so that they will build.
Change-Id: I5e44135b6dfa800fa14e5b08c3e3e5921d50b082
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12865
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Migrate google/guado (Asus Chromebox CN62) from Chromium tree to upstream,
using google/auron and google/panther as refs.
TEST=built and booted guado with full functionality
Change-Id: If7a500fb408197a61c9619b9d5ea1458d1f4d702
Tested-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/12800
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
The Braswell CPU seems to have two different Video BIOS roms, one for
the C0 revision, and one for other revisions. Build them both into
the coreboot image, and let coreboot sort out which one should be used
at runtime. This should allow one rom to be used for all revisions.
The initial reason for this patch was that the Kconfig symbol
C0_DISP_SUPPORT didn't exist, and was causing issues. This
seems like the best way to eliminate the need for that symbol.
Change-Id: I5b9f225c0daf4e02fda75daf9cd07bb160bf0e0f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12826
Tested-by: build bot (Jenkins)
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The RPU Clock register defaults to on for all clocks.
This is modified to OFF, and the MIPS clock control modified to ON,
by default. This is because the linux kernel will manage the
clocks at all times, but the RPU can only disable clocks if the WIFI
module has been loaded.
Change-Id: I155fb37afd585ca3436a77b97c99ca6e582cbb4f
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12773
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This requires changes the interface that sets up the system
PLL to support a given reference devider value and given
feedback value.
Also, this requires a change in the dividers used for UART,
USB, I2C setup.
Change-Id: I98cf7c655dbb3e95b8fcee3c7f468122021c70b5
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12765
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This is to make towiki pick that information, to make
these boards end up in the laptop list at:
http://www.coreboot.org/Supported_Motherboards
Change-Id: Ibf8bf4bf6566080a34687e36675d4c4c8b89f334
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: https://review.coreboot.org/12716
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The symbols CHROMEOS_VBNV_EC, EC_SOFTWARE_SYNC, and VIRTUAL_DEV_SWITCH
should only be selected if CHROMEOS is selected.
Change-Id: I07ef631d63be53cf99a6bf61d0e91b88728dbba3
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12659
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The Chrome OS verified boot path supported multiple CBFS
instances in the boot media as well as stand-alone assets
sitting in each vboot RW slot. Remove the support for the
stand-alone assets and always use CBFS accesses as the
way to retrieve data.
This is implemented by adding a cbfs_locator object which
is queried for locating the current CBFS. Additionally, it
is also signalled prior to when a program is about to be
loaded by coreboot for the subsequent stage/payload. This
provides the same opportunity as previous for vboot to
hook in and perform its logic.
BUG=chromium:445938
BRANCH=None
TEST=Built and ran on glados.
CQ-DEPEND=CL:307121,CL:31691,CL:31690
Change-Id: I6a3a15feb6edd355d6ec252c36b6f7885b383099
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12689
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
We never defined the flash size for this board, so the (too small)
default was used. Instead, adopt the size given in depthcharge's fmap
description.
Change-Id: I63782922ee05a9595d6c0de56750460ebb67aec6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/12674
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
