In FSP-S, the driver constructs its pointer to UPD using the offset
in the header. Similarly, use the header's cfg_region_size for
allocating memory and copying the default configuration.
Add sanity checks for unexpedted configuration and UPD header
conditions.
TEST=Verify OK on Mandolin, verify a mock error condition
BUG=b:140648081
Change-Id: I20fad0e27a2ad537898b6d01e5241e1508da690c
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Leverage already used eax register in bootblock_protected_mode_entry.
Avoid another register ebx just for preserving eax value as it is not
needed and is not used at all after moving the value into mm0.
Allow EBX to be preserved for other usage.
Change-Id: Ia668b78f2f97cf026692f1fe63ff8a382a162474
Signed-off-by: Himanshu Sahdev <himanshusah@hcl.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35292
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
drallion_ish.bin is updated for drallion GPIO changes
and not compatible with arcada_cml.
TEST=Build and boot arcada_cml
Signed-off-by: Selma BENSAID <selma.bensaid@intel.com>
Change-Id: Idb35c33425bfd50533df74349dd645db18a65bc5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
FSP BIOS 212 / 07.00.6C.40 for CNL/WHL supports FSP to use coreboot stack.
This change selects common stack config, that enables coreboot to support
share stack with FSP.
TEST=Boot to OS on WHL platform
Change-Id: I0778ee21cb4f66b8ec884b77788c05a73c609be6
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Even though GT7375P programming guide rev0.4 only requires a reset delay
of 120ms, in practice, we have to increase the reset delay to 500ms, or
Goodix FW update would fail.
This is a workaround. In the long run, we hope Goodix can fix the power
sequence in touch firmware.
BUG=b:138795891, b:138796844
TEST=boot helios board and verify Goodix FW update succeeded
Signed-off-by: Philip Chen <philipchen@google.com>
Change-Id: Ic0049bf240de0a1c7f1b1f39bf155d48bb76fb86
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35350
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replace the raw register definitions with device numbers and macros
for determining the register offsets. Rewrite the source to refer
to AOAC device numbers instead of a structure.
Remove the calculated offset for the console UART. Picasso's UARTs
are not contiguous so handle them separately.
Change-Id: Iffc87f39ebe38394a56d41bb0940e9701fd05db9
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
This will increase ME region size and reduce the BIOS region size.
BUG=b:140665483
TEST='compile successfully'
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Change-Id: I5be2580d280569421d0870a06f9b93124b564b6f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35304
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PchPwrOptEnable FSP UPD is for internal testing and not really available
in externally released FSP source hence assigning this UPD using devicetree
config dmipwroptimize doesn't do anything.
TEST=Build and boot sarien/arcada.
Change-Id: I6da2a088fb697e57d12008fa18bd1764b3da7765
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
With the current devicetree the kernel doesn't provide any serial
after serial init.
Update the devicetree to resolve this issue.
Tested on HiFive Unleashed.
Change-Id: I4427d34a12902e0eaa2186121a53152b719cadff
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>
This is necessary to get rid of a .c include.
Also do some cosmetic fixes to a table, now that the line length limit
has been raised.
Change-Id: I6fd7fa5c9b21368bde8f089060733df6de34b4fd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Host FW status 1 (FWSTS1/HFSTS1) register definition is common across SoCs,
hence move it to common. Also add below helper function,
* wait_cse_sec_override_mode() - Polls ME status for "HECI_OP_MODE_SEC_OVERRIDE".
It's a special CSE mode, the mode ensures CSE does not trigger any
spi cycles to CSE region.
* set_host_ready() - Clears reset state from host CSR.
TEST=Verified CSE recover mode on CML RVP & Hatch board
Change-Id: Id5c12b7abdb27c38af74ea6ee568b42ec74bcb3c
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35226
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Separate timestamp_sync_cache_to_cbmem() as it is only
used with ENV_ROMSTAGE.
Change-Id: Ibe18a5ecf09b2b87d8ee3e828728ad6a8a262206
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35280
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
CML FSP now provides a provision to configure the SATA devslp
GPIO pad reset configuration. This config would help set the
the required pad reset configuration.
BUG=b:133000685
Change-Id: I4eaea9c6da67f1274ad3e392046a68cddc1b99b6
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This patch helps to save additional ~19ms of booting time in
normal boot and s3 resume on CML-hatch.
BUG=b:140008206
TEST=Verified normal boot time on CML-Hatch with latest coreboot
Without this CL:
Total Time: 929ms
With this CL: (TSEG marked as WB)
Total Time: 910ms
For test marked TSEG as WP/WC:
Total Time: ~920ms
Change-Id: Ie92d2c9e50fa299db1cd8c57a6047ea3adaf1452
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35026
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit fdb9805d68.
CB:33252 wasn't reviewed by a TPM maintainer and breaks abstraction
layers (pulling TSS-details into TSPI, completely changing
interpretation of the arguments to tlcl_extend() based on TSS version).
It's also not clear why it was implemented the way it was (should have
been much easier and cleaner ways to achieve the same thing).
Since the author is not reacting, let's revert it for now. It can be
cleaned up and resubmitted later. (Not reverting the header changes
since those are not objectionable, and there are later patches dependent
on it.)
Change-Id: Ice44f55c75a0acc07794fe41c757a7bca75406eb
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
futility is built for the host. However, when cross-compiling,
the target's pkg-config is called to get the library paths which
can add paths from the cross-compilation tree instead of host.
e.g. /build/elm/usr/bin/pkg-config gets called instead of /usr/bin/pkg-config
. /build/elm/usr/bin/pkg-config adds the paths specific to the
cross-compilation target e.g. /build/elm/usr/lib instead of /usr/lib.
This causes linker to complain that files in library paths do not
match the architecture. BFD produces a warning while LLD errors out.
Fix this by passing PKG_CONFIG from host when building futility.
BUG=chromium:999217
TEST=coreboot builds
BRANCH=None
Cq-Depend: chromium:1778519
Change-Id: Id3afbf25001cf3daa72f36a290c93136cf9f162d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35316
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds new API for enabling caching for the TSEG region
and setting up required MTRR for next stage.
BUG=b:140008206
TEST=Build and boot CML-Hatch.
Change-Id: I59432c02e04af1b931d77de3f6652b0327ca82bb
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Drallion uses the same touch panel as Sarien. Copy the deivce
from Sarien.
BUG=b:140415892,b:138082886
BRANCH=N/A
TEST=N/A
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I8e6d2dcf4bd2ed2325137a05811af03692d40342
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35305
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
ITR2 is specified twice here, which leads to the following error message
in Linux:
[ 0.263591] ACPI BIOS Error (bug): Failure creating named object
[\_SB.PCI0.LPCB.SIO0.ITR2], AE_ALREADY_EXISTS (20190509/dsfield-633)
Add comments and fix duplicated field.
As there are no users of this code yet, just rename the fields.
Tested on Supermicro X11SSH-TF.
Change-Id: I4f3307d0992fcf5ad192f412c2bd15d02572a6b0
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35294
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
me_read_config32() is defined in multiple places, move it to common
location. Also, this function is usually used for reading HFSTS
registers, hence move the HFSTS register definitions to common location.
Also add a funtion to check if the CSE device has been enabled in the
devicetree and it is visible on the bus. This API can be used by
the caller to check before initiating any HECI communication.
TEST=Verified reading HFSTS registers on CML RVP & Hatch board
Change-Id: Icdbfb6b30a007d469b5e018a313c14586addb130
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35225
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Restrict the use of symbol names _car_global_[start|end]
to be used exclusively with CAR_GLOBAL_MIGRATION=y.
They just alias the start and end of .bss section in CAR.
Change-Id: I36c858a4f181516d4c61f9fd1d5005c7d2c06057
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35034
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
As code already used CBMEM hooks to switch from CAR to CBMEM
it was never necessary to have the structure declared inside
_car_relocatable_data.
Switch to use car_[get|set]_ptr is mostly for consistency, but
should also enable use of usbdebug with FSP1.0 romstage.
Change-Id: I636251085d84e52a71a1d5d27d795bb94a07422d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Keep track of the active timestamp table location using
a CAR_GLOBAL variable. Done this way, the entire table
can be located outside _car_relocatable_data and we only
switch the pointer to CBMEM and copy the data before
CAR gets torn down.
Fix comments about requirements of timestamp_init() usage.
Remove timestamp_cache from postcar and ramstage, as CBMEM
is available early on.
Change-Id: I87370f62db23318069b6fd56ba0d1171d619cb8a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35032
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
MT8183_DRAM_EMCP is enabled for devices using eMCP to run at a high DRAM
frequency (e.g., 3600Mbps).
BUG=b:80501386
BRANCH=none
TEST=Memory test passes on EMCP platform
Change-Id: Icf875427347418f796cbf193070bf047844d2267
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34433
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Devices using eMCP may run at a high DRAM frequency (e.g., 3600Mbs)
while those with discrete DRAM can only run at 3200Mbps. A new option
MT8183_DRAM_EMCP is added to Kconfig for a mainboard to select,
depending on whether it supports eMCP or not.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui
Change-Id: I9b73c8b512db5104896ea0d330d56e63eb50a44b
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
.editorconfig files are widely supported and offer basic configuration
options for the project.
This sets the indention style, line-ending, character set, tells the
editor to make sure there's a newline at the end of the file and to
strip trailing whitespace.
For directories within the coreboot directory that would prefer a
different setting, additional .editorconfig files can be placed in
those directories to override any of these settings.
See the EditorConfig website for more information.
https://web.archive.org/web/https://editorconfig.org
Change-Id: Iecf1c5450edb0db533569189aa45233b91997870
Signed-off-by: Martin Roth <martin@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
As discussed on the mailing list and voted upon, the coreboot project
is going to move the majority of copyrights out of the headers and into
an AUTHORS file. This will happen a bit at a time, as we'll be unifying
license headers at the same time.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Id6070fb586896653a1e44951a6af8f42f93b5a7b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
As discussed on the mailing list and voted upon, the coreboot project
is going to move the majority of copyrights out of the headers and into
an AUTHORS file. This will happen a bit at a time, as we'll be unifying
license headers at the same time.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I39f52764dc377c25953ef5dba16982a0b4637cdb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Guckian
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
As discussed on the mailing list and voted upon, the coreboot project
is going to move the majority of copyrights out of the headers and into
an AUTHORS file. This will happen a bit at a time, as we'll be unifying
license headers at the same time.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I77275adb7c15b242e319805b8a60b7755fa25db5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
As discussed on the mailing list and voted upon, the coreboot project
is going to move the majority of copyrights out of the headers and into
an AUTHORS file. This will happen a bit at a time, as we'll be unifying
license headers at the same time.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I2f350cc3008b17516b5a42cdf07e28d2da5995e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
As discussed on the mailing list and voted upon, the coreboot project
is going to move the majority of copyrights out of the headers and into
an AUTHORS file. This will happen a bit at a time, as we'll be unifying
license headers at the same time.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I4c9351652d81040cc4e7b85bdd1ba85709a74192
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
As discussed on the mailing list and voted upon, the coreboot project
is going to move the majority of copyrights out of the headers and into
an AUTHORS file. This will happen a bit at a time, as we'll be unifying
license headers at the same time.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ifd4329905847d9dd06de67b9a443c8ee50c0e7a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Setup EC_PCH_ARCORE_INT_L, tied to GPP_D17, and define as EC_SYNC_GPIO..
- change GPP_D17 definition to PAD_CFG_GPI_APIC_INVERT as
EC_PCH_ARCORE_INT_L is active low
- add EC_SYNC_GPIO to the group of chromeos_gpios for use by depthcharge
BUG=b:139384979
BRANCH=none
TEST="emerge_nocturne coreboot depthcharge chromeos-bootimage",
flash & boot nocturne in dev mode, verify that volume up and down
buttons work in the dev screen and that the device boots properly into
the kernel.
Change-Id: Ia43c622710fde8686c60b836fb8318931d79eb61
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Himanshu Sahdev